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m32c.cpu
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; Renesas M32C CPU description. -*- Scheme -*-
;
; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Renesas.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
; MA 02110-1301, USA.
(include "simplify.inc")
(define-arch
(name m32c)
(comment "Renesas M32C")
(default-alignment forced)
(insn-lsb0? #f)
(machs m16c m32c)
(isas m16c m32c)
)
(define-isa
(name m16c)
(default-insn-bitsize 32)
; Number of bytes of insn we can initially fetch.
(base-insn-bitsize 32)
; Used in computing bit numbers.
(default-insn-word-bitsize 32)
(decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
; fetches 1 insn at a time.
(liw-insns 1)
; executes 1 insn at a time.
(parallel-insns 1)
)
(define-isa
(name m32c)
(default-insn-bitsize 32)
; Number of bytes of insn we can initially fetch.
(base-insn-bitsize 32)
; Used in computing bit numbers.
(default-insn-word-bitsize 32)
(decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
; fetches 1 insn at a time.
(liw-insns 1)
; executes 1 insn at a time.
(parallel-insns 1)
)
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m16cbf)
(comment "Renesas M16C base family")
(insn-endian big)
(data-endian little)
(word-bitsize 16)
)
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m32cbf)
(comment "Renesas M32C base family")
(insn-endian big)
(data-endian little)
(word-bitsize 16)
)
(define-mach
(name m16c)
(comment "Generic M16C cpu")
(cpu m32cbf)
)
(define-mach
(name m32c)
(comment "Generic M32C cpu")
(cpu m32cbf)
)
; Model descriptions.
(define-model
(name m16c)
(comment "m16c") (attrs)
(mach m16c)
; `state' is a list of variables for recording model state
; (state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
(define-model
(name m32c)
(comment "m32c") (attrs)
(mach m32c)
; `state' is a list of variables for recording model state
; (state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
(define-attr
(type enum)
(name RL_TYPE)
(values NONE JUMP 1ADDR 2ADDR)
(default NONE)
)
; Macros to simplify MACH attribute specification.
(define-pmacro all-isas () (ISA m16c,m32c))
(define-pmacro m16c-isa () (ISA m16c))
(define-pmacro m32c-isa () (ISA m32c))
(define-pmacro MACH16 (MACH m16c))
(define-pmacro MACH32 (MACH m32c))
(define-pmacro (machine size)
(MACH (.sym m size c)) (ISA (.sym m size c)))
(define-pmacro RL_JUMP (RL_TYPE JUMP))
(define-pmacro RL_1ADDR (RL_TYPE 1ADDR))
(define-pmacro RL_2ADDR (RL_TYPE 2ADDR))
;=============================================================
; Fields
;-------------------------------------------------------------
; Main opcodes
;
(dnf f-0-1 "opcode" (all-isas) 0 1)
(dnf f-0-2 "opcode" (all-isas) 0 2)
(dnf f-0-3 "opcode" (all-isas) 0 3)
(dnf f-0-4 "opcode" (all-isas) 0 4)
(dnf f-1-3 "opcode" (all-isas) 1 3)
(dnf f-2-2 "opcode" (all-isas) 2 2)
(dnf f-3-4 "opcode" (all-isas) 3 4)
(dnf f-3-1 "opcode" (all-isas) 3 1)
(dnf f-4-1 "opcode" (all-isas) 4 1)
(dnf f-4-3 "opcode" (all-isas) 4 3)
(dnf f-4-4 "opcode" (all-isas) 4 4)
(dnf f-4-6 "opcode" (all-isas) 4 6)
(dnf f-5-1 "opcode" (all-isas) 5 1)
(dnf f-5-3 "opcode" (all-isas) 5 3)
(dnf f-6-2 "opcode" (all-isas) 6 2)
(dnf f-7-1 "opcode" (all-isas) 7 1)
(dnf f-8-1 "opcode" (all-isas) 8 1)
(dnf f-8-2 "opcode" (all-isas) 8 2)
(dnf f-8-3 "opcode" (all-isas) 8 3)
(dnf f-8-4 "opcode" (all-isas) 8 4)
(dnf f-8-8 "opcode" (all-isas) 8 8)
(dnf f-9-3 "opcode" (all-isas) 9 3)
(dnf f-9-1 "opcode" (all-isas) 9 1)
(dnf f-10-1 "opcode" (all-isas) 10 1)
(dnf f-10-2 "opcode" (all-isas) 10 2)
(dnf f-10-3 "opcode" (all-isas) 10 3)
(dnf f-11-1 "opcode" (all-isas) 11 1)
(dnf f-12-1 "opcode" (all-isas) 12 1)
(dnf f-12-2 "opcode" (all-isas) 12 2)
(dnf f-12-3 "opcode" (all-isas) 12 3)
(dnf f-12-4 "opcode" (all-isas) 12 4)
(dnf f-12-6 "opcode" (all-isas) 12 6)
(dnf f-13-3 "opcode" (all-isas) 13 3)
(dnf f-14-1 "opcode" (all-isas) 14 1)
(dnf f-14-2 "opcode" (all-isas) 14 2)
(dnf f-15-1 "opcode" (all-isas) 15 1)
(dnf f-16-1 "opcode" (all-isas) 16 1)
(dnf f-16-2 "opcode" (all-isas) 16 2)
(dnf f-16-4 "opcode" (all-isas) 16 4)
(dnf f-16-8 "opcode" (all-isas) 16 8)
(dnf f-18-1 "opcode" (all-isas) 18 1)
(dnf f-18-2 "opcode" (all-isas) 18 2)
(dnf f-18-3 "opcode" (all-isas) 18 3)
(dnf f-20-1 "opcode" (all-isas) 20 1)
(dnf f-20-3 "opcode" (all-isas) 20 3)
(dnf f-20-2 "opcode" (all-isas) 20 2)
(dnf f-20-4 "opcode" (all-isas) 20 4)
(dnf f-21-3 "opcode" (all-isas) 21 3)
(dnf f-24-2 "opcode" (all-isas) 24 2)
(dnf f-24-8 "opcode" (all-isas) 24 8)
(dnf f-32-16 "opcode" (all-isas) 32 16)
;-------------------------------------------------------------
; Registers
;-------------------------------------------------------------
(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2)
(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1)
(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1)
(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; SI mode gr encoding for m32c is as follows:
; register encoding index
; -------------------------
; r2r0 10'b 0
; r3r1 11'b 1
(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1)
(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2)
(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1)
(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1)
(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1)
(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1)
(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1)
(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; SI mode gr encoding for m32c is as follows:
; register encoding index
; -------------------------
; r2r0 10'b 0
; r3r1 11'b 1
(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1)
;-------------------------------------------------------------
; Immediates embedded in the base insn
;-------------------------------------------------------------
(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f)
(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f)
(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f)
(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f)
(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT
((value pc) (sub USI value 1)) ; insert
((value pc) (add USI value 1)) ; extract
)
(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT
(f-2-2 f-7-1)
(sequence () ; insert
(set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1))
(set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3))
)
(sequence () ; extract
(set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1)
(ifield f-7-1))
1))
)
)
;-------------------------------------------------------------
; Immediates and displacements beyond the base insn
;-------------------------------------------------------------
(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f)
(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f)
(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f)
(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f)
(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f)
(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f)
(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f)
(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f)
(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f)
(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f)
(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f)
(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f)
(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f)
(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f)
(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f)
(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f)
(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f)
(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f)
; Insn opcode endianness is big, but the immediate fields are stored
; in little endian. Handle this here at the field level for all immediate
; fields longer that 1 byte.
;
; CGEN can't handle a field which spans a 32 bit word boundary, so
; handle those as multi ifields.
;
; Take care in expressions using 'srl' or 'sll' as part of some larger
; expression meant to yield sign-extended values. CGEN translates
; uses of those operators into C expressions whose type is 'unsigned
; int', which tends to make the whole expression 'unsigned int'.
; Expressions like (set (ifield foo) X), however, just take X and
; store it in some member of 'struct cgen_fields', all of whose
; members are 'long'. On machines where 'long' is larger than
; 'unsigned int', assigning a "sign-extended" unsigned int to a long
; just produces a very large positive value. insert_normal will
; range-check the field's value and produce odd error messages like
; this:
;
; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]'
;
; Annoyingly, the code will work fine on machines where 'long' and
; 'unsigned int' are the same size: the assignment will produce a
; negative number.
;
; Just tell yourself over and over: overflow detection is expensive,
; and you're glad C doesn't do it, because it never happens in real
; life.
(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT
((value pc) (or UHI
(and (srl value 8) #xff)
(sll (and value #xff) 8))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #xff)
(sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; extract
)
(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT
((value pc) (or UHI
(and (srl value 8) #xff)
(sll (and value #xff) 8))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #xff)
(sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; extract
)
(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT
(f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8)
(ifield f-dsp-24-u8)))
)
)
(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT
(f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-24-u8)
(and (ifield f-dsp-24-s16) #xff))
(set (ifield f-dsp-32-u8)
(and (srl (ifield f-dsp-24-s16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-s16)
(ext INT
(trunc HI (or (sll (ifield f-dsp-32-u8) 8)
(ifield f-dsp-24-u8)))))
)
)
(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT
((value pc) (or UHI
(and (srl value 8) #xff)
(sll (and value #xff) 8))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #xff)
(sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; extract
)
(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT
((value pc) (or UHI
(and (srl value 8) #xff)
(sll (and value #xff) 8))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #xff)
(sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; extract
)
(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT
((value pc) (or UHI
(and (srl value 8) #xff)
(sll (and value #xff) 8))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #xff)
(sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; extract
)
(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT
((value pc) (or UHI
(and (srl value 8) #xff)
(sll (and value #xff) 8))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #xff)
(sll UHI (and UHI value #xff) 8))) ; extract
)
(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT
((value pc) (sub SI (xor (or SI (or (and (srl value 16) #xff)
(and value #xff00))
(sll (and value #xff) 16))
#x800000) #x800000))
((value pc) (sub SI (xor (or SI
(or (and (srl value 16) #xff)
(and value #xff00))
(sll (and value #xff) 16))
#x800000) #x800000))
)
(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
)
(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-16-u16 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16)
(ifield f-dsp-16-u16)))
)
)
(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-24-u8 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff))
(set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8)
(ifield f-dsp-24-u8)))
)
)
(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
(and (sll value 16) #xff0000))) ; insert
((value pc) (or USI
(or USI
(and USI (srl value 16) #x0000ff)
(and USI value #x00ff00))
(and USI (sll value 16) #xff0000))) ; extract
)
(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
(and (sll value 16) #x0f0000))) ; insert
((value pc) (or USI
(or USI
(and USI (srl value 16) #x0000ff)
(and USI value #x00ff00))
(and USI (sll value 16) #x0f0000))) ; extract
)
(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
(and (sll value 16) #xff0000))) ; insert
((value pc) (or USI
(or USI
(and USI (srl value 16) #x0000ff)
(and USI value #x00ff00))
(and USI (sll value 16) #xff0000))) ; extract
)
(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT
(f-dsp-40-u24 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff))
(set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff))
)
(sequence () ; extract
(set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff)
(and (sll (ifield f-dsp-64-u8) 24) #xff000000)))
)
)
(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT
(f-dsp-48-u16 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u8) 16) #x0f0000)))
)
)
(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-48-u16 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u8) 16) #xff0000)))
)
)
(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT
(f-dsp-16-u16 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff))
(set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff)
(and (sll (ifield f-dsp-32-u16) 16) #xffff0000)))
)
)
(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT
(f-dsp-24-u8 f-dsp-32-u24)
(sequence () ; insert
(set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff))
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff)
(and (sll (ifield f-dsp-32-u24) 8) #xffffff00)))
)
)
(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT
((value pc)
;; insert
(ext INT
(or SI
(or SI
(and (srl value 24) #x00ff)
(and (srl value 8) #xff00))
(or SI
(sll (and value #xff00) 8)
(sll (and value #x00ff) 24)))))
;; extract
((value pc)
(ext INT
(or SI
(or SI
(and (srl value 24) #x00ff)
(and (srl value 8) #xff00))
(or SI
(sll (and value #xff00) 8)
(sll (and value #x00ff) 24)))))
)
(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT
(f-dsp-48-u16 f-dsp-64-u16)
(sequence () ; insert
(set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff)
(sll (and (ifield f-dsp-64-u16) #xffff) 16)))
)
)
(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT
(f-dsp-48-u16 f-dsp-64-u16)
(sequence () ; insert
(set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff)
(sll (and (ifield f-dsp-64-u16) #xffff) 16)))
)
)
(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT
(f-dsp-56-u8 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-56-u8)
(and (ifield f-dsp-56-s16) #xff))
(set (ifield f-dsp-64-u8)
(and (srl (ifield f-dsp-56-s16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-56-s16)
(ext INT
(trunc HI (or (sll (ifield f-dsp-64-u8) 8)
(ifield f-dsp-56-u8)))))
)
)
(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #xff)
(sll (and value #xff) 8))))) ; extract
)
;-------------------------------------------------------------
; Bit indices
;-------------------------------------------------------------
(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3)
(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3)
(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3)
(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT
(f-bitno16-S f-dsp-8-u8)
(sequence () ; insert
(set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7))
(set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3)
(ifield f-bitno16-S)))
)
)
(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7))
(set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-unprefixed f-dsp-16-s8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7))
(set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-s11-unprefixed) (or (mul (ifield f-dsp-16-s8) 8)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u16)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7))
(set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-unprefixed f-dsp-16-s16)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7))
(set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-s19-unprefixed) (or (mul (ifield f-dsp-16-s16) 8)
(ifield f-bitno32-unprefixed)))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7))
(set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
(or (sll (ifield f-dsp-32-u8) 19)
(ifield f-bitno32-unprefixed))))
)
)
(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(ifield f-bitno32-prefixed)))
)
)
(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-prefixed f-dsp-24-s8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7))
(set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-s11-prefixed) (or (mul (ifield f-dsp-24-s8) 8)
(ifield f-bitno32-prefixed)))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (sll (ifield f-dsp-32-u8) 11)
(ifield f-bitno32-prefixed))))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff))
(set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (mul (ifield f-dsp-32-s8) 2048)
(ifield f-bitno32-prefixed))))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff))
(set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (sll (ifield f-dsp-32-u16) 11)
(ifield f-bitno32-prefixed))))
)
)
;-------------------------------------------------------------
; Labels
;-------------------------------------------------------------
(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT
(f-2-2 f-7-1)
(sequence ((SI val)) ; insert
(set val (sub (sub (ifield f-lab32-jmp-s) pc) 2))
(set (ifield f-7-1) (and val #x1))
(set (ifield f-2-2) (srl val 1))
)
(sequence () ; extract
(set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1)
(ifield f-7-1))
2)))
)
)
(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT
((value pc) (sub SI value (add SI pc 1))) ; insert
((value pc) (add SI value (add SI pc 1))) ; extract
)
(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT
((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8)
(srl (and (sub value (add pc 1)) #xff00) 8)))
((value pc) (add SI (sub (xor (or (srl (and value #xff00) 8)
(sll (and value #xff) 8))
#x8000)
#x8000)
(add pc 1)))
)
(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
)
(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
;-------------------------------------------------------------
; Condition codes
;-------------------------------------------------------------
(dnf f-cond16 "condition code" (all-isas) 12 4)
(dnf f-cond16j-5 "condition code" (all-isas) 5 3)