memtest.list

1011_0001_1010_1110  //LLB R1, 0xAE       PC = 0
1010_0001_0000_0001  //LHB R1, 0x01       PC = 1
1011_0010_1110_1111  //LLB R2, 0xEF       PC = 2
1010_0010_1011_1110  //LHB R2, 0xBE       PC = 3
// R1: 0x01AE
// R2: 0xBEEF

1001_0010_0000_0010  //SW: M[2] <- R2     PC = 4
1000_0011_0000_0010  //LW: R3 <- M[2]     PC = 5
// R3: 0xBEEF

1001_0001_0000_0011  //SW: M[3] <- R1     PC = 6
1000_0100_0000_0011  //LW: R4 <- M[2]     PC = 7
// R4: 0x01AE

1001_0001_0000_0100  //SW: M[4] <- R1     PC = 8
1001_0010_0000_0100  //SW: M[4] <- R2     PC = 9
1000_0110_0000_0100  //LW: R6 <- M[4]     PC = 10
1000_0111_0000_0100  //LW: R7 <- M[4]     PC = 11
1001_0110_0000_0101  //SW: M[5] <- R6     PC = 12
1000_1010_0000_0101  //LW: R10 <- M[5]    PC = 13

1111_0000_0000_0000	// halt instruction

//Expected Output: 0000 01ae beef beef 01ae xxxx beef beef xxxx xxxx beef xxxx xxxx xxxx xxxx xxxx