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Generate some VHDL, yo. #1

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cakesmith opened this issue Oct 9, 2014 · 0 comments
Open

Generate some VHDL, yo. #1

cakesmith opened this issue Oct 9, 2014 · 0 comments
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enhancement
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VHDL

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I want to be able to output valid VHDL for each chip. If the chip is synthesizable, it should be able to output VHDL that can be directly imported into another program to generate a netlist and program a logic device without too much (preferably any) tweaking.
@cakesmith cakesmith self-assigned this Oct 9, 2014
@cakesmith cakesmith added this to the VHDL milestone Oct 9, 2014
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