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swarm_cs4297a.c
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swarm_cs4297a.c
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/*******************************************************************************
*
* "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver.
*
* Copyright (C) 2001 Broadcom Corporation.
* Copyright (C) 2000,2001 Cirrus Logic Corp.
* -- adapted from drivers by Thomas Sailer,
* -- but don't bug him; Problems should go to:
* -- tom woller ([email protected]) or
* ([email protected]).
* -- adapted from cs4281 PCI driver for cs4297a on
* BCM1250 Synchronous Serial interface
* (Kip Walker, Broadcom Corp.)
* Copyright (C) 2004 Maciej W. Rozycki
* Copyright (C) 2005 Ralf Baechle ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module command line parameters:
* none
*
* Supported devices:
* /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
* /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
* /dev/midi simple MIDI UART interface, no ioctl
*
* Modification History
* 08/20/00 trw - silence and no stopping DAC until release
* 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
* 09/18/00 trw - added 16bit only record with conversion
* 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
* capture/playback rates)
* 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
* libOSSm.so)
* 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
* 11/03/00 trw - fixed interrupt loss/stutter, added debug.
* 11/10/00 bkz - added __devinit to cs4297a_hw_init()
* 11/10/00 trw - fixed SMP and capture spinlock hang.
* 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
* 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
* 12/08/00 trw - added PM support.
* 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
* (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
* 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
* 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
* defaultorder-100 as power of 2 for the buffer size. example:
* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
*
*******************************************************************************/
#include <linux/list.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/sound.h>
#include <linux/slab.h>
#include <linux/soundcard.h>
#include <linux/ac97_codec.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/mutex.h>
#include <linux/kernel.h>
#include <asm/byteorder.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_dma.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250_syncser.h>
#include <asm/sibyte/sb1250_mac.h>
#include <asm/sibyte/sb1250.h>
struct cs4297a_state;
static void stop_dac(struct cs4297a_state *s);
static void stop_adc(struct cs4297a_state *s);
static void start_dac(struct cs4297a_state *s);
static void start_adc(struct cs4297a_state *s);
#undef OSS_DOCUMENTED_MIXER_SEMANTICS
// ---------------------------------------------------------------------
#define CS4297a_MAGIC 0xf00beef1
// buffer order determines the size of the dma buffer for the driver.
// under Linux, a smaller buffer allows more responsiveness from many of the
// applications (e.g. games). A larger buffer allows some of the apps (esound)
// to not underrun the dma buffer as easily. As default, use 32k (order=3)
// rather than 64k as some of the games work more responsively.
// log base 2( buff sz = 32k).
//static unsigned long defaultorder = 3;
//MODULE_PARM(defaultorder, "i");
//
// Turn on/off debugging compilation by commenting out "#define CSDEBUG"
//
#define CSDEBUG 0
#if CSDEBUG
#define CSDEBUG_INTERFACE 1
#else
#undef CSDEBUG_INTERFACE
#endif
//
// cs_debugmask areas
//
#define CS_INIT 0x00000001 // initialization and probe functions
#define CS_ERROR 0x00000002 // tmp debugging bit placeholder
#define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
#define CS_FUNCTION 0x00000008 // enter/leave functions
#define CS_WAVE_WRITE 0x00000010 // write information for wave
#define CS_WAVE_READ 0x00000020 // read information for wave
#define CS_AC97 0x00000040 // AC97 register access
#define CS_DESCR 0x00000080 // descriptor management
#define CS_OPEN 0x00000400 // all open functions in the driver
#define CS_RELEASE 0x00000800 // all release functions in the driver
#define CS_PARMS 0x00001000 // functional and operational parameters
#define CS_IOCTL 0x00002000 // ioctl (non-mixer)
#define CS_TMP 0x10000000 // tmp debug mask bit
//
// CSDEBUG is usual mode is set to 1, then use the
// cs_debuglevel and cs_debugmask to turn on or off debugging.
// Debug level of 1 has been defined to be kernel errors and info
// that should be printed on any released driver.
//
#if CSDEBUG
#define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
#else
#define CS_DBGOUT(mask,level,x)
#endif
#if CSDEBUG
static unsigned long cs_debuglevel = 4; // levels range from 1-9
static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
module_param(cs_debuglevel, int, 0);
module_param(cs_debugmask, int, 0);
#endif
#define CS_TRUE 1
#define CS_FALSE 0
#define CS_TYPE_ADC 0
#define CS_TYPE_DAC 1
#define SER_BASE (A_SER_BASE_1 + KSEG1)
#define SS_CSR(t) (SER_BASE+t)
#define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
#define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
#define FRAME_BYTES 32
#define FRAME_SAMPLE_BYTES 4
/* Should this be variable? */
#define SAMPLE_BUF_SIZE (16*1024)
#define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
/* The driver can explode/shrink the frames to/from a smaller sample
buffer */
#define DMA_BLOAT_FACTOR 1
#define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
#define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES)
/* Use the maxmium count (255 == 5.1 ms between interrupts) */
#define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1)
/* Figure this out: how many TX DMAs ahead to schedule a reg access */
#define REG_LATENCY 150
#define FRAME_TX_US 20
#define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
static const char invalid_magic[] =
KERN_CRIT "cs4297a: invalid magic value\n";
#define VALIDATE_STATE(s) \
({ \
if (!(s) || (s)->magic != CS4297a_MAGIC) { \
printk(invalid_magic); \
return -ENXIO; \
} \
})
struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
typedef struct serdma_descr_s {
u64 descr_a;
u64 descr_b;
} serdma_descr_t;
typedef unsigned long paddr_t;
typedef struct serdma_s {
unsigned ringsz;
serdma_descr_t *descrtab;
serdma_descr_t *descrtab_end;
paddr_t descrtab_phys;
serdma_descr_t *descr_add;
serdma_descr_t *descr_rem;
u64 *dma_buf; // buffer for DMA contents (frames)
paddr_t dma_buf_phys;
u16 *sample_buf; // tmp buffer for sample conversions
u16 *sb_swptr;
u16 *sb_hwptr;
u16 *sb_end;
dma_addr_t dmaaddr;
// unsigned buforder; // Log base 2 of 'dma_buf' size in bytes..
unsigned numfrag; // # of 'fragments' in the buffer.
unsigned fragshift; // Log base 2 of fragment size.
unsigned hwptr, swptr;
unsigned total_bytes; // # bytes process since open.
unsigned blocks; // last returned blocks value GETOPTR
unsigned wakeup; // interrupt occurred on block
int count;
unsigned underrun; // underrun flag
unsigned error; // over/underrun
wait_queue_head_t wait;
wait_queue_head_t reg_wait;
// redundant, but makes calculations easier
unsigned fragsize; // 2**fragshift..
unsigned sbufsz; // 2**buforder.
unsigned fragsamples;
// OSS stuff
unsigned mapped:1; // Buffer mapped in cs4297a_mmap()?
unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
unsigned endcleared:1;
unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
unsigned ossfragshift;
int ossmaxfrags;
unsigned subdivision;
} serdma_t;
struct cs4297a_state {
// magic
unsigned int magic;
struct list_head list;
// soundcore stuff
int dev_audio;
int dev_mixer;
// hardware resources
unsigned int irq;
struct {
unsigned int rx_ovrrn; /* FIFO */
unsigned int rx_overflow; /* staging buffer */
unsigned int tx_underrun;
unsigned int rx_bad;
unsigned int rx_good;
} stats;
// mixer registers
struct {
unsigned short vol[10];
unsigned int recsrc;
unsigned int modcnt;
unsigned short micpreamp;
} mix;
// wave stuff
struct properties {
unsigned fmt;
unsigned fmt_original; // original requested format
unsigned channels;
unsigned rate;
} prop_dac, prop_adc;
unsigned conversion:1; // conversion from 16 to 8 bit in progress
unsigned ena;
spinlock_t lock;
struct mutex open_mutex;
struct mutex open_sem_adc;
struct mutex open_sem_dac;
mode_t open_mode;
wait_queue_head_t open_wait;
wait_queue_head_t open_wait_adc;
wait_queue_head_t open_wait_dac;
dma_addr_t dmaaddr_sample_buf;
unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes..
serdma_t dma_dac, dma_adc;
volatile u16 read_value;
volatile u16 read_reg;
volatile u64 reg_request;
};
#if 1
#define prog_codec(a,b)
#define dealloc_dmabuf(a,b);
#endif
static int prog_dmabuf_adc(struct cs4297a_state *s)
{
s->dma_adc.ready = 1;
return 0;
}
static int prog_dmabuf_dac(struct cs4297a_state *s)
{
s->dma_dac.ready = 1;
return 0;
}
static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
unsigned len, unsigned char c)
{
if (bptr + len > bsize) {
unsigned x = bsize - bptr;
memset(((char *) buf) + bptr, c, x);
bptr = 0;
len -= x;
}
CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
"cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
(unsigned)c, (unsigned)((char *) buf) + bptr, len));
memset(((char *) buf) + bptr, c, len);
}
#if CSDEBUG
// DEBUG ROUTINES
#define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
#define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
#define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
#define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
static void cs_printioctl(unsigned int x)
{
unsigned int i;
unsigned char vidx;
// Index of mixtable1[] member is Device ID
// and must be <= SOUND_MIXER_NRDEVICES.
// Value of array member is index into s->mix.vol[]
static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
[SOUND_MIXER_PCM] = 1, // voice
[SOUND_MIXER_LINE1] = 2, // AUX
[SOUND_MIXER_CD] = 3, // CD
[SOUND_MIXER_LINE] = 4, // Line
[SOUND_MIXER_SYNTH] = 5, // FM
[SOUND_MIXER_MIC] = 6, // Mic
[SOUND_MIXER_SPEAKER] = 7, // Speaker
[SOUND_MIXER_RECLEV] = 8, // Recording level
[SOUND_MIXER_VOLUME] = 9 // Master Volume
};
switch (x) {
case SOUND_MIXER_CS_GETDBGMASK:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
break;
case SOUND_MIXER_CS_GETDBGLEVEL:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
break;
case SOUND_MIXER_CS_SETDBGMASK:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
break;
case SOUND_MIXER_CS_SETDBGLEVEL:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
break;
case OSS_GETVERSION:
CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
break;
case SNDCTL_DSP_SYNC:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
break;
case SNDCTL_DSP_SETDUPLEX:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
break;
case SNDCTL_DSP_GETCAPS:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
break;
case SNDCTL_DSP_RESET:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
break;
case SNDCTL_DSP_SPEED:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
break;
case SNDCTL_DSP_STEREO:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
break;
case SNDCTL_DSP_CHANNELS:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
break;
case SNDCTL_DSP_GETFMTS:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
break;
case SNDCTL_DSP_SETFMT:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
break;
case SNDCTL_DSP_POST:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
break;
case SNDCTL_DSP_GETTRIGGER:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
break;
case SNDCTL_DSP_SETTRIGGER:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
break;
case SNDCTL_DSP_GETOSPACE:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
break;
case SNDCTL_DSP_GETISPACE:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
break;
case SNDCTL_DSP_NONBLOCK:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
break;
case SNDCTL_DSP_GETODELAY:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
break;
case SNDCTL_DSP_GETIPTR:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
break;
case SNDCTL_DSP_GETOPTR:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
break;
case SNDCTL_DSP_GETBLKSIZE:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
break;
case SNDCTL_DSP_SETFRAGMENT:
CS_DBGOUT(CS_IOCTL, 4,
printk("SNDCTL_DSP_SETFRAGMENT:\n"));
break;
case SNDCTL_DSP_SUBDIVIDE:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
break;
case SOUND_PCM_READ_RATE:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
break;
case SOUND_PCM_READ_CHANNELS:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_PCM_READ_CHANNELS:\n"));
break;
case SOUND_PCM_READ_BITS:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
break;
case SOUND_PCM_WRITE_FILTER:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_PCM_WRITE_FILTER:\n"));
break;
case SNDCTL_DSP_SETSYNCRO:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
break;
case SOUND_PCM_READ_FILTER:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
break;
case SOUND_MIXER_PRIVATE1:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
break;
case SOUND_MIXER_PRIVATE2:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
break;
case SOUND_MIXER_PRIVATE3:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
break;
case SOUND_MIXER_PRIVATE4:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
break;
case SOUND_MIXER_PRIVATE5:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
break;
case SOUND_MIXER_INFO:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
break;
case SOUND_OLD_MIXER_INFO:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
break;
default:
switch (_IOC_NR(x)) {
case SOUND_MIXER_VOLUME:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_VOLUME:\n"));
break;
case SOUND_MIXER_SPEAKER:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_SPEAKER:\n"));
break;
case SOUND_MIXER_RECLEV:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_RECLEV:\n"));
break;
case SOUND_MIXER_MIC:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_MIC:\n"));
break;
case SOUND_MIXER_SYNTH:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_SYNTH:\n"));
break;
case SOUND_MIXER_RECSRC:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_RECSRC:\n"));
break;
case SOUND_MIXER_DEVMASK:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_DEVMASK:\n"));
break;
case SOUND_MIXER_RECMASK:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_RECMASK:\n"));
break;
case SOUND_MIXER_STEREODEVS:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_STEREODEVS:\n"));
break;
case SOUND_MIXER_CAPS:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
break;
default:
i = _IOC_NR(x);
if (i >= SOUND_MIXER_NRDEVICES
|| !(vidx = mixtable1[i])) {
CS_DBGOUT(CS_IOCTL, 4, printk
("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
x, i));
} else {
CS_DBGOUT(CS_IOCTL, 4, printk
("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
x, i));
}
break;
}
}
}
#endif
static int ser_init(struct cs4297a_state *s)
{
int i;
CS_DBGOUT(CS_INIT, 2,
printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
__raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
__raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
__raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
__raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
__raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
__raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
__raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
/* This looks good from experimentation */
__raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
SS_CSR(R_SER_LINE_MODE));
/* This looks good from experimentation */
__raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
SS_TXTBL(0));
__raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
SS_TXTBL(1));
__raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
SS_TXTBL(2));
__raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
__raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
SS_RXTBL(0));
__raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
SS_RXTBL(1));
__raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
SS_RXTBL(2));
__raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
for (i=4; i<16; i++) {
/* Just in case... */
__raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
__raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
}
return 0;
}
static int init_serdma(serdma_t *dma)
{
CS_DBGOUT(CS_INIT, 2,
printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
/* Descriptors */
dma->ringsz = DMA_DESCR;
dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
if (!dma->descrtab) {
printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n");
return -1;
}
dma->descrtab_end = dma->descrtab + dma->ringsz;
/* XXX bloddy mess, use proper DMA API here ... */
dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
dma->descr_add = dma->descr_rem = dma->descrtab;
/* Frame buffer area */
dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL);
if (!dma->dma_buf) {
printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n");
kfree(dma->descrtab);
return -1;
}
dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
/* Samples buffer area */
dma->sbufsz = SAMPLE_BUF_SIZE;
dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
if (!dma->sample_buf) {
printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
kfree(dma->descrtab);
kfree(dma->dma_buf);
return -1;
}
dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
dma->fragsize = dma->sbufsz >> 1;
CS_DBGOUT(CS_INIT, 4,
printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
(int)dma->descrtab, (int)dma->dma_buf,
(int)dma->sample_buf));
return 0;
}
static int dma_init(struct cs4297a_state *s)
{
int i;
CS_DBGOUT(CS_INIT, 2,
printk(KERN_INFO "cs4297a: Setting up DMA\n"));
if (init_serdma(&s->dma_adc) ||
init_serdma(&s->dma_dac))
return -1;
if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
panic("DMA state corrupted?!");
}
/* Initialize now - the descr/buffer pairings will never
change... */
for (i=0; i<DMA_DESCR; i++) {
s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
(s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
(s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
s->dma_adc.descrtab[i].descr_b = 0;
}
__raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
SS_CSR(R_SER_DMA_CONFIG0_RX));
__raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
__raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
__raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
__raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
__raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
/* Prep the receive DMA descriptor ring */
__raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
__raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
__raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
SS_CSR(R_SER_INT_MASK));
/* Enable the rx/tx; let the codec warm up to the sync and
start sending good frames before the receive FIFO is
enabled */
__raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
udelay(1000);
__raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
/* XXXKW is this magic? (the "1" part) */
while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
;
CS_DBGOUT(CS_INIT, 4,
printk(KERN_INFO "cs4297a: status: %08x\n",
(unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
return 0;
}
static int serdma_reg_access(struct cs4297a_state *s, u64 data)
{
serdma_t *d = &s->dma_dac;
u64 *data_p;
unsigned swptr;
unsigned long flags;
serdma_descr_t *descr;
if (s->reg_request) {
printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
return -1;
}
if (s->ena & FMODE_WRITE) {
/* Since a writer has the DSP open, we have to mux the
request in */
s->reg_request = data;
interruptible_sleep_on(&s->dma_dac.reg_wait);
/* XXXKW how can I deal with the starvation case where
the opener isn't writing? */
} else {
/* Be safe when changing ring pointers */
spin_lock_irqsave(&s->lock, flags);
if (d->hwptr != d->swptr) {
printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
d->hwptr, d->swptr);
spin_unlock_irqrestore(&s->lock, flags);
return -1;
}
swptr = d->swptr;
d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
spin_unlock_irqrestore(&s->lock, flags);
descr = &d->descrtab[swptr];
data_p = &d->dma_buf[swptr * 4];
*data_p = cpu_to_be64(data);
__raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
CS_DBGOUT(CS_DESCR, 4,
printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n",
data_p, swptr, d->hwptr));
}
CS_DBGOUT(CS_FUNCTION, 6,
printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
return 0;
}
//****************************************************************************
// "cs4297a_read_ac97" -- Reads an AC97 register
//****************************************************************************
static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
u32 * value)
{
CS_DBGOUT(CS_AC97, 1,
printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
return -1;
interruptible_sleep_on(&s->dma_adc.reg_wait);
*value = s->read_value;
CS_DBGOUT(CS_AC97, 2,
printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
return 0;
}
//****************************************************************************
// "cs4297a_write_ac97()"-- writes an AC97 register
//****************************************************************************
static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
u32 value)
{
CS_DBGOUT(CS_AC97, 1,
printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
}
static void stop_dac(struct cs4297a_state *s)
{
unsigned long flags;
CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
spin_lock_irqsave(&s->lock, flags);
s->ena &= ~FMODE_WRITE;
#if 0
/* XXXKW what do I really want here? My theory for now is
that I just flip the "ena" bit, and the interrupt handler
will stop processing the xmit channel */
__raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
SS_CSR(R_SER_DMA_ENABLE));
#endif
spin_unlock_irqrestore(&s->lock, flags);
}
static void start_dac(struct cs4297a_state *s)
{
unsigned long flags;
CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
spin_lock_irqsave(&s->lock, flags);
if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
(s->dma_dac.count > 0
&& s->dma_dac.ready))) {
s->ena |= FMODE_WRITE;
/* XXXKW what do I really want here? My theory for
now is that I just flip the "ena" bit, and the
interrupt handler will start processing the xmit
channel */
CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
"cs4297a: start_dac(): start dma\n"));
}
spin_unlock_irqrestore(&s->lock, flags);
CS_DBGOUT(CS_FUNCTION, 3,
printk(KERN_INFO "cs4297a: start_dac()-\n"));
}
static void stop_adc(struct cs4297a_state *s)
{
unsigned long flags;
CS_DBGOUT(CS_FUNCTION, 3,
printk(KERN_INFO "cs4297a: stop_adc()+\n"));
spin_lock_irqsave(&s->lock, flags);
s->ena &= ~FMODE_READ;
if (s->conversion == 1) {
s->conversion = 0;
s->prop_adc.fmt = s->prop_adc.fmt_original;
}
/* Nothing to do really, I need to keep the DMA going
XXXKW when do I get here, and is there more I should do? */
spin_unlock_irqrestore(&s->lock, flags);
CS_DBGOUT(CS_FUNCTION, 3,
printk(KERN_INFO "cs4297a: stop_adc()-\n"));
}
static void start_adc(struct cs4297a_state *s)
{
unsigned long flags;
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4297a: start_adc()+\n"));
if (!(s->ena & FMODE_READ) &&
(s->dma_adc.mapped || s->dma_adc.count <=
(signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
&& s->dma_adc.ready) {
if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
//
// now only use 16 bit capture, due to truncation issue
// in the chip, noticable distortion occurs.
// allocate buffer and then convert from 16 bit to
// 8 bit for the user buffer.
//
s->prop_adc.fmt_original = s->prop_adc.fmt;
if (s->prop_adc.fmt & AFMT_S8) {
s->prop_adc.fmt &= ~AFMT_S8;
s->prop_adc.fmt |= AFMT_S16_LE;
}
if (s->prop_adc.fmt & AFMT_U8) {
s->prop_adc.fmt &= ~AFMT_U8;
s->prop_adc.fmt |= AFMT_U16_LE;
}
//
// prog_dmabuf_adc performs a stop_adc() but that is
// ok since we really haven't started the DMA yet.
//
prog_codec(s, CS_TYPE_ADC);
prog_dmabuf_adc(s);
s->conversion = 1;
}
spin_lock_irqsave(&s->lock, flags);
s->ena |= FMODE_READ;
/* Nothing to do really, I am probably already
DMAing... XXXKW when do I get here, and is there
more I should do? */
spin_unlock_irqrestore(&s->lock, flags);
CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
"cs4297a: start_adc(): start adc\n"));
}
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4297a: start_adc()-\n"));
}
// call with spinlock held!
static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
{
int good_diff, diff, diff2;
u64 *data_p, data;
u32 *s_ptr;
unsigned hwptr;
u32 status;
serdma_t *d;
serdma_descr_t *descr;
// update ADC pointer
status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
d = &s->dma_adc;
hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
d->descrtab_phys) / sizeof(serdma_descr_t));
if (s->ena & FMODE_READ) {
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
d->swptr, d->hwptr, hwptr, intflag));
/* Number of DMA buffers available for software: */
diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
d->hwptr = hwptr;
good_diff = 0;
s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
descr = &d->descrtab[d->swptr];
while (diff2--) {
u64 data = be64_to_cpu(*(u64 *)s_ptr);
u64 descr_a;
u16 left, right;
descr_a = descr->descr_a;
descr->descr_a &= ~M_DMA_SERRX_SOP;
if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
}
if (((data & 0x9800000000000000) != 0x9800000000000000) ||
(!(descr_a & M_DMA_SERRX_SOP)) ||
(G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
s->stats.rx_bad++;
printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
continue;
}
s->stats.rx_good++;
if ((data >> 61) == 7) {
s->read_value = (data >> 12) & 0xffff;
s->read_reg = (data >> 40) & 0x7f;
wake_up(&d->reg_wait);
}
if (d->count && (d->sb_hwptr == d->sb_swptr)) {
s->stats.rx_overflow++;
printk(KERN_DEBUG "cs4297a: RX overflow\n");
continue;
}
good_diff++;
left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
*d->sb_hwptr++ = cpu_to_be16(left);
*d->sb_hwptr++ = cpu_to_be16(right);
if (d->sb_hwptr == d->sb_end)
d->sb_hwptr = d->sample_buf;
descr++;
if (descr == d->descrtab_end) {
descr = d->descrtab;
s_ptr = (u32 *)s->dma_adc.dma_buf;
} else {
s_ptr += 8;
}
}
d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
d->count += good_diff * FRAME_SAMPLE_BYTES;
if (d->count > d->sbufsz) {
printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
}
d->swptr = (d->swptr + diff) % d->ringsz;
__raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
if (d->mapped) {
if (d->count >= (signed) d->fragsize)
wake_up(&d->wait);
} else {