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AArch64Mapping.c
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/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2019 */
#ifdef CAPSTONE_HAS_AARCH64
#include <stdio.h> // debug
#include <string.h>
#include "capstone/aarch64.h"
#include "../../cs_simple_types.h"
#include "../../Mapping.h"
#include "../../MathExtras.h"
#include "../../utils.h"
#include "AArch64AddressingModes.h"
#include "AArch64BaseInfo.h"
#include "AArch64DisassemblerExtension.h"
#include "AArch64Linkage.h"
#include "AArch64Mapping.h"
#ifndef CAPSTONE_DIET
static aarch64_reg aarch64_flag_regs[] = {
AArch64_REG_NZCV,
};
static aarch64_sysreg aarch64_flag_sys_regs[] = {
AArch64_SYSREG_NZCV,
AArch64_SYSREG_PMOVSCLR_EL0,
AArch64_SYSREG_PMOVSSET_EL0,
AArch64_SYSREG_SPMOVSCLR_EL0,
AArch64_SYSREG_SPMOVSSET_EL0
};
#endif // CAPSTONE_DIET
static AArch64Layout_VectorLayout sme_reg_to_vas(aarch64_reg reg) {
switch (reg) {
default:
return AArch64Layout_Invalid;
case AArch64_REG_ZAB0:
return AArch64Layout_VL_B;
case AArch64_REG_ZAH0:
case AArch64_REG_ZAH1:
return AArch64Layout_VL_H;
case AArch64_REG_ZAS0:
case AArch64_REG_ZAS1:
case AArch64_REG_ZAS2:
case AArch64_REG_ZAS3:
return AArch64Layout_VL_S;
case AArch64_REG_ZAD0:
case AArch64_REG_ZAD1:
case AArch64_REG_ZAD2:
case AArch64_REG_ZAD3:
case AArch64_REG_ZAD4:
case AArch64_REG_ZAD5:
case AArch64_REG_ZAD6:
case AArch64_REG_ZAD7:
return AArch64Layout_VL_D;
case AArch64_REG_ZAQ0:
case AArch64_REG_ZAQ1:
case AArch64_REG_ZAQ2:
case AArch64_REG_ZAQ3:
case AArch64_REG_ZAQ4:
case AArch64_REG_ZAQ5:
case AArch64_REG_ZAQ6:
case AArch64_REG_ZAQ7:
case AArch64_REG_ZAQ8:
case AArch64_REG_ZAQ9:
case AArch64_REG_ZAQ10:
case AArch64_REG_ZAQ11:
case AArch64_REG_ZAQ12:
case AArch64_REG_ZAQ13:
case AArch64_REG_ZAQ14:
case AArch64_REG_ZAQ15:
return AArch64Layout_VL_Q;
case AArch64_REG_ZA:
return AArch64Layout_VL_Complete;
}
}
void AArch64_init_mri(MCRegisterInfo *MRI)
{
MCRegisterInfo_InitMCRegisterInfo(
MRI, AArch64RegDesc, AArch64_REG_ENDING, 0, 0, AArch64MCRegisterClasses,
ARR_SIZE(AArch64MCRegisterClasses), 0, 0,
AArch64RegDiffLists, 0, AArch64SubRegIdxLists, ARR_SIZE(AArch64SubRegIdxLists), 0);
}
const insn_map aarch64_insns[] = {
#include "AArch64GenCSMappingInsn.inc"
};
static const name_map insn_alias_mnem_map[] = {
#include "AArch64GenCSAliasMnemMap.inc"
{ AArch64_INS_ALIAS_CFP, "cfp" },
{ AArch64_INS_ALIAS_DVP, "dvp" },
{ AArch64_INS_ALIAS_COSP, "cosp" },
{ AArch64_INS_ALIAS_CPP, "cpp" },
{ AArch64_INS_ALIAS_IC, "ic" },
{ AArch64_INS_ALIAS_DC, "dc" },
{ AArch64_INS_ALIAS_AT, "at" },
{ AArch64_INS_ALIAS_TLBI, "tlbi" },
{ AArch64_INS_ALIAS_TLBIP, "tlbip" },
{ AArch64_INS_ALIAS_RPRFM, "rprfm" },
{ AArch64_INS_ALIAS_LSL, "lsl" },
{ AArch64_INS_ALIAS_SBFX, "sbfx" },
{ AArch64_INS_ALIAS_UBFX, "ubfx" },
{ AArch64_INS_ALIAS_SBFIZ, "sbfiz" },
{ AArch64_INS_ALIAS_UBFIZ, "ubfiz" },
{ AArch64_INS_ALIAS_BFC, "bfc" },
{ AArch64_INS_ALIAS_BFI, "bfi" },
{ AArch64_INS_ALIAS_BFXIL, "bfxil" },
{ AArch64_INS_ALIAS_END, NULL },
};
static const char *get_custom_reg_alias(unsigned reg)
{
switch (reg) {
case AArch64_REG_X29:
return "fp";
case AArch64_REG_X30:
return "lr";
}
return NULL;
}
/// Very annoyingly LLVM hard codes the vector layout post-fixes into the asm string.
/// In this function we check for these cases and add the vectorlayout/arrangement
/// specifier.
void AArch64_add_vas(MCInst *MI, const SStream *OS) {
if (!detail_is_set(MI)) {
return;
}
if (AArch64_get_detail(MI)->op_count == 0) {
return;
}
// Search for r".[0-9]{1,2}[bhsdq]\W"
// with poor mans regex
const char *vl_ptr = strchr(OS->buffer, '.');
while (vl_ptr) {
// Number after dot?
unsigned num = 0;
if (strchr("1248", vl_ptr[1])) {
num = atoi(vl_ptr + 1);
vl_ptr = num > 9 ? vl_ptr + 3 : vl_ptr + 2;
} else {
vl_ptr++;
}
// Layout letter
char letter = '\0';
if (strchr("bhsdq", vl_ptr[0])) {
letter = vl_ptr[0];
}
if (!letter) {
goto next_dot_continue;
}
AArch64Layout_VectorLayout vl = AArch64Layout_Invalid;
switch (letter) {
default:
assert(0 && "Unhandled vector layout letter.");
return;
case 'b':
vl = AArch64Layout_VL_B;
break;
case 'h':
vl = AArch64Layout_VL_H;
break;
case 's':
vl = AArch64Layout_VL_S;
break;
case 'd':
vl = AArch64Layout_VL_D;
break;
case 'q':
vl = AArch64Layout_VL_Q;
break;
}
vl |= (num << 8);
// Determine op index by searching for trainling commata after op string
uint32_t op_idx = 0;
const char *comma_ptr = strchr(OS->buffer, ',');;
while (comma_ptr && comma_ptr < vl_ptr) {
++op_idx;
comma_ptr = strchr(comma_ptr + 1, ',');
}
if (!comma_ptr) {
// Last op doesn't have a trailing commata.
op_idx = AArch64_get_detail(MI)->op_count - 1;
}
if (op_idx >= AArch64_get_detail(MI)->op_count) {
// A memory operand with a commata in [base, dist]
op_idx = AArch64_get_detail(MI)->op_count - 1;
}
// Search for the operand this one belongs to.
cs_aarch64_op *op = &AArch64_get_detail(MI)->operands[op_idx];
if ((op->type != AArch64_OP_REG && op->type != AArch64_OP_SME_MATRIX) || op->vas != AArch64Layout_Invalid) {
goto next_dot_continue;
}
op->vas = vl;
next_dot_continue:
vl_ptr = strchr(vl_ptr + 1, '.');
}
}
const char *AArch64_reg_name(csh handle, unsigned int reg)
{
int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
const char *alias = get_custom_reg_alias(reg);
if ((syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS) && alias)
return alias;
if (((cs_struct *)(uintptr_t)handle)->syntax & CS_OPT_SYNTAX_NOREGNAME) {
return AArch64_LLVM_getRegisterName(reg, AArch64_NoRegAltName);
}
// TODO Add options for the other register names
return AArch64_LLVM_getRegisterName(reg, AArch64_NoRegAltName);
}
void AArch64_setup_op(cs_aarch64_op *op)
{
memset(op, 0, sizeof(cs_aarch64_op));
op->type = AArch64_OP_INVALID;
op->vector_index = -1;
}
void AArch64_init_cs_detail(MCInst *MI)
{
if (detail_is_set(MI)) {
memset(get_detail(MI), 0,
offsetof(cs_detail, aarch64) + sizeof(cs_aarch64));
for (int i = 0; i < ARR_SIZE(AArch64_get_detail(MI)->operands); i++)
AArch64_setup_op(&AArch64_get_detail(MI)->operands[i]);
AArch64_get_detail(MI)->cc = AArch64CC_Invalid;
}
}
/// Unfortunately, the AArch64 definitions do not indicate in any way
/// (exception are the instruction identifiers), if memory accesses
/// is post- or pre-indexed.
/// So the only generic way to determine, if the memory access is in
/// post-indexed addressing mode, is by search for "<membase>], #<memdisp>" in
/// @p OS.
/// Searching the asm string to determine such a property is enourmously ugly
/// and wastes resources.
/// Sorry, I know and do feel bad about it. But for now it works.
static bool AArch64_check_post_index_am(const MCInst *MI, const SStream *OS) {
if (AArch64_get_detail(MI)->post_index) {
return true;
}
cs_aarch64_op *memop = NULL;
for (int i = 0; i < AArch64_get_detail(MI)->op_count; ++i) {
if (AArch64_get_detail(MI)->operands[i].type & CS_OP_MEM) {
memop = &AArch64_get_detail(MI)->operands[i];
break;
}
}
if (!memop)
return false;
const char *membase = AArch64_LLVM_getRegisterName(memop->mem.base, AArch64_NoRegAltName);
int64_t memdisp = memop->mem.disp;
SStream pattern = { 0 };
SStream_concat(&pattern, membase);
SStream_concat(&pattern, "], ");
printInt32Bang(&pattern, memdisp);
return strstr(OS->buffer, pattern.buffer) != NULL;
}
static void AArch64_check_updates_flags(MCInst *MI)
{
#ifndef CAPSTONE_DIET
if (!detail_is_set(MI))
return;
cs_detail *detail = get_detail(MI);
// Implicity written registers
for (int i = 0; i < detail->regs_write_count; ++i) {
if (detail->regs_write[i] == 0)
break;
for (int j = 0; j < ARR_SIZE(aarch64_flag_regs); ++j) {
if (detail->regs_write[i] == aarch64_flag_regs[j]) {
detail->aarch64.update_flags = true;
return;
}
}
}
for (int i = 0; i < detail->aarch64.op_count; ++i) {
if (detail->aarch64.operands[i].type == AArch64_OP_SYSREG &&
detail->aarch64.operands[i].sysop.sub_type == AArch64_OP_REG_MSR) {
for (int j = 0; j < ARR_SIZE(aarch64_flag_sys_regs); ++j)
if (detail->aarch64.operands[i].sysop.reg.sysreg == aarch64_flag_sys_regs[j]) {
detail->aarch64.update_flags = true;
return;
}
} else if (detail->aarch64.operands[i].type == AArch64_OP_REG &&
detail->aarch64.operands[i].access & CS_AC_WRITE) {
for (int j = 0; j < ARR_SIZE(aarch64_flag_regs); ++j)
if (detail->aarch64.operands[i].reg == aarch64_flag_regs[j]) {
detail->aarch64.update_flags = true;
return;
}
}
}
#endif // CAPSTONE_DIET
}
static void add_non_alias_details(MCInst *MI) {
unsigned Opcode = MCInst_getOpcode(MI);
switch (Opcode) {
default:
break;
case AArch64_FCMPDri:
case AArch64_FCMPEDri:
case AArch64_FCMPEHri:
case AArch64_FCMPESri:
case AArch64_FCMPHri:
case AArch64_FCMPSri:
AArch64_insert_detail_op_reg_at(MI, -1, AArch64_REG_XZR, CS_AC_READ);
break;
case AArch64_CMEQv16i8rz:
case AArch64_CMEQv1i64rz:
case AArch64_CMEQv2i32rz:
case AArch64_CMEQv2i64rz:
case AArch64_CMEQv4i16rz:
case AArch64_CMEQv4i32rz:
case AArch64_CMEQv8i16rz:
case AArch64_CMEQv8i8rz:
case AArch64_CMGEv16i8rz:
case AArch64_CMGEv1i64rz:
case AArch64_CMGEv2i32rz:
case AArch64_CMGEv2i64rz:
case AArch64_CMGEv4i16rz:
case AArch64_CMGEv4i32rz:
case AArch64_CMGEv8i16rz:
case AArch64_CMGEv8i8rz:
case AArch64_CMGTv16i8rz:
case AArch64_CMGTv1i64rz:
case AArch64_CMGTv2i32rz:
case AArch64_CMGTv2i64rz:
case AArch64_CMGTv4i16rz:
case AArch64_CMGTv4i32rz:
case AArch64_CMGTv8i16rz:
case AArch64_CMGTv8i8rz:
case AArch64_CMLEv16i8rz:
case AArch64_CMLEv1i64rz:
case AArch64_CMLEv2i32rz:
case AArch64_CMLEv2i64rz:
case AArch64_CMLEv4i16rz:
case AArch64_CMLEv4i32rz:
case AArch64_CMLEv8i16rz:
case AArch64_CMLEv8i8rz:
case AArch64_CMLTv16i8rz:
case AArch64_CMLTv1i64rz:
case AArch64_CMLTv2i32rz:
case AArch64_CMLTv2i64rz:
case AArch64_CMLTv4i16rz:
case AArch64_CMLTv4i32rz:
case AArch64_CMLTv8i16rz:
case AArch64_CMLTv8i8rz:
AArch64_insert_detail_op_imm_at(MI, -1, 0);
break;
case AArch64_FCMEQv1i16rz:
case AArch64_FCMEQv1i32rz:
case AArch64_FCMEQv1i64rz:
case AArch64_FCMEQv2i32rz:
case AArch64_FCMEQv2i64rz:
case AArch64_FCMEQv4i16rz:
case AArch64_FCMEQv4i32rz:
case AArch64_FCMEQv8i16rz:
case AArch64_FCMGEv1i16rz:
case AArch64_FCMGEv1i32rz:
case AArch64_FCMGEv2i32rz:
case AArch64_FCMGEv2i64rz:
case AArch64_FCMGEv4i16rz:
case AArch64_FCMGEv4i32rz:
case AArch64_FCMGEv8i16rz:
case AArch64_FCMGTv2i32rz:
case AArch64_FCMGTv2i64rz:
case AArch64_FCMGTv4i16rz:
case AArch64_FCMGTv4i32rz:
case AArch64_FCMGTv8i16rz:
case AArch64_FCMLEv2i32rz:
case AArch64_FCMLEv2i64rz:
case AArch64_FCMLEv4i16rz:
case AArch64_FCMLEv4i32rz:
case AArch64_FCMLEv8i16rz:
case AArch64_FCMEQ_PPzZ0_D:
case AArch64_FCMEQ_PPzZ0_H:
case AArch64_FCMEQ_PPzZ0_S:
case AArch64_FCMGE_PPzZ0_D:
case AArch64_FCMGE_PPzZ0_H:
case AArch64_FCMGE_PPzZ0_S:
case AArch64_FCMGT_PPzZ0_D:
case AArch64_FCMGT_PPzZ0_H:
case AArch64_FCMGT_PPzZ0_S:
case AArch64_FCMLE_PPzZ0_D:
case AArch64_FCMLE_PPzZ0_H:
case AArch64_FCMLE_PPzZ0_S:
case AArch64_FCMLT_PPzZ0_D:
case AArch64_FCMLT_PPzZ0_H:
case AArch64_FCMLT_PPzZ0_S:
case AArch64_FCMNE_PPzZ0_D:
case AArch64_FCMNE_PPzZ0_H:
case AArch64_FCMNE_PPzZ0_S:
case AArch64_FCMLTv2i32rz:
case AArch64_FCMLTv2i64rz:
case AArch64_FCMLTv4i16rz:
case AArch64_FCMLTv4i32rz:
case AArch64_FCMLTv8i16rz:
AArch64_insert_detail_op_float_at(MI, -1, 0.0f, CS_AC_READ);
break;
}
}
static void AArch64_add_not_defined_ops(MCInst *MI, const SStream *OS)
{
if (!detail_is_set(MI))
return;
if (!MI->flat_insn->is_alias || !MI->flat_insn->usesAliasDetails) {
add_non_alias_details(MI);
return;
}
// Alias details
switch(MI->flat_insn->alias_id) {
default:
return;
case AArch64_INS_ALIAS_FMOV:
AArch64_insert_detail_op_float_at(MI, -1, 0.0f, CS_AC_READ);
break;
case AArch64_INS_ALIAS_LD1:
case AArch64_INS_ALIAS_LD1R:
case AArch64_INS_ALIAS_LD2:
case AArch64_INS_ALIAS_LD2R:
case AArch64_INS_ALIAS_LD3:
case AArch64_INS_ALIAS_LD3R:
case AArch64_INS_ALIAS_LD4:
case AArch64_INS_ALIAS_LD4R:
case AArch64_INS_ALIAS_ST1:
case AArch64_INS_ALIAS_ST2:
case AArch64_INS_ALIAS_ST3:
case AArch64_INS_ALIAS_ST4: {
// Add post-index disp
const char *disp_off = strrchr(OS->buffer, '#');
if (!disp_off)
return;
unsigned disp = atoi(disp_off + 1);
AArch64_get_detail_op(MI, -1)->type = AArch64_OP_MEM;
AArch64_get_detail_op(MI, -1)->mem.base = AArch64_get_detail_op(MI, -1)->reg;
AArch64_get_detail_op(MI, -1)->mem.disp = disp;
AArch64_get_detail(MI)->post_index = true;
break;
}
}
}
void AArch64_set_instr_map_data(MCInst *MI)
{
map_cs_id(MI, aarch64_insns, ARR_SIZE(aarch64_insns));
map_implicit_reads(MI, aarch64_insns);
map_implicit_writes(MI, aarch64_insns);
map_groups(MI, aarch64_insns);
}
bool AArch64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *MI, uint16_t *size, uint64_t address,
void *info) {
AArch64_init_cs_detail(MI);
bool Result = AArch64_LLVM_getInstruction(handle, code, code_len, MI, size, address,
info) != MCDisassembler_Fail;
AArch64_set_instr_map_data(MI);
return Result;
}
/// Patches the register names with Capstone specific alias.
/// Those are common alias for registers (e.g. r15 = pc)
/// which are not set in LLVM.
static void patch_cs_reg_alias(char *asm_str)
{
bool skip_sub = false;
char *x29 = strstr(asm_str, "x29");
if (x29 > asm_str && strstr(asm_str, "0x29") == (x29 - 1)) {
// Check for hex prefix
skip_sub = true;
}
while (x29 && !skip_sub) {
x29[0] = 'f';
x29[1] = 'p';
memmove(x29 + 2, x29 + 3, strlen(x29 + 3));
asm_str[strlen(asm_str) - 1] = '\0';
x29 = strstr(asm_str, "x29");
}
skip_sub = false;
char *x30 = strstr(asm_str, "x30");
if (x30 > asm_str && strstr(asm_str, "0x30") == (x30 - 1)) {
// Check for hex prefix
skip_sub = true;
}
while (x30 && !skip_sub) {
x30[0] = 'l';
x30[1] = 'r';
memmove(x30 + 2, x30 + 3, strlen(x30 + 3));
asm_str[strlen(asm_str) - 1] = '\0';
x30 = strstr(asm_str, "x30");
}
}
/// Adds group to the instruction which are not defined in LLVM.
static void AArch64_add_cs_groups(MCInst *MI)
{
unsigned Opcode = MI->flat_insn->id;
switch (Opcode) {
default:
return;
case AArch64_INS_SVC:
add_group(MI, AArch64_GRP_INT);
break;
case AArch64_INS_SMC:
case AArch64_INS_MSR:
case AArch64_INS_MRS:
add_group(MI, AArch64_GRP_PRIVILEGE);
break;
case AArch64_INS_RET:
case AArch64_INS_RETAA:
case AArch64_INS_RETAB:
add_group(MI, AArch64_GRP_RET);
break;
}
}
void AArch64_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) {
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
MI->MRI = MRI;
MI->fillDetailOps = detail_is_set(MI);
MI->flat_insn->usesAliasDetails = map_use_alias_details(MI);
AArch64_LLVM_printInstruction(MI, O, info);
if (detail_is_set(MI))
AArch64_get_detail(MI)->post_index = AArch64_check_post_index_am(MI, O);
AArch64_check_updates_flags(MI);
map_set_alias_id(MI, O, insn_alias_mnem_map, ARR_SIZE(insn_alias_mnem_map) - 1);
int syntax_opt = MI->csh->syntax;
if (syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS)
patch_cs_reg_alias(O->buffer);
AArch64_add_not_defined_ops(MI, O);
AArch64_add_cs_groups(MI);
AArch64_add_vas(MI, O);
}
// given internal insn id, return public instruction info
void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
// Done after disassembly
return;
}
static const char *const insn_name_maps[] = {
#include "AArch64GenCSMappingInsnName.inc"
};
const char *AArch64_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id < AArch64_INS_ALIAS_END && id > AArch64_INS_ALIAS_BEGIN) {
if (id - AArch64_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map))
return NULL;
return insn_alias_mnem_map[id - AArch64_INS_ALIAS_BEGIN - 1].name;
}
if (id >= AArch64_INS_ENDING)
return NULL;
if (id < ARR_SIZE(insn_name_maps))
return insn_name_maps[id];
// not found
return NULL;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
// generic groups
{ AArch64_GRP_INVALID, NULL },
{ AArch64_GRP_JUMP, "jump" },
{ AArch64_GRP_CALL, "call" },
{ AArch64_GRP_RET, "return" },
{ AArch64_GRP_PRIVILEGE, "privilege" },
{ AArch64_GRP_INT, "int" },
{ AArch64_GRP_BRANCH_RELATIVE, "branch_relative" },
// architecture-specific groups
#include "AArch64GenCSFeatureName.inc"
};
#endif
const char *AArch64_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
// map instruction name to public instruction ID
aarch64_insn AArch64_map_insn(const char *name)
{
unsigned int i;
for(i = 1; i < ARR_SIZE(insn_name_maps); i++) {
if (!strcmp(name, insn_name_maps[i]))
return i;
}
// not found
return AArch64_INS_INVALID;
}
#ifndef CAPSTONE_DIET
static const map_insn_ops insn_operands[] = {
#include "AArch64GenCSMappingInsnOp.inc"
};
void AArch64_reg_access(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count)
{
uint8_t i;
uint8_t read_count, write_count;
cs_aarch64 *aarch64 = &(insn->detail->aarch64);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
// explicit registers
for (i = 0; i < aarch64->op_count; i++) {
cs_aarch64_op *op = &(aarch64->operands[i]);
switch((int)op->type) {
case AArch64_OP_REG:
if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
case AArch64_OP_MEM:
// registers appeared in memory references always being read
if ((op->mem.base != AArch64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
regs_read[read_count] = (uint16_t)op->mem.base;
read_count++;
}
if ((op->mem.index != AArch64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
regs_read[read_count] = (uint16_t)op->mem.index;
read_count++;
}
if ((insn->detail->writeback) && (op->mem.base != AArch64_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
regs_write[write_count] = (uint16_t)op->mem.base;
write_count++;
}
default:
break;
}
}
*regs_read_count = read_count;
*regs_write_count = write_count;
}
#endif
static AArch64Layout_VectorLayout get_vl_by_suffix(const char suffix) {
switch (suffix) {
default:
return AArch64Layout_Invalid;
case 'b':
case 'B':
return AArch64Layout_VL_B;
case 'h':
case 'H':
return AArch64Layout_VL_H;
case 's':
case 'S':
return AArch64Layout_VL_S;
case 'd':
case 'D':
return AArch64Layout_VL_D;
case 'q':
case 'Q':
return AArch64Layout_VL_Q;
}
}
static unsigned get_vec_list_num_regs(MCInst *MI, unsigned Reg) {
// Work out how many registers there are in the list (if there is an actual
// list).
unsigned NumRegs = 1;
if (MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_DDRegClassID), Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_ZPR2RegClassID),
Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_QQRegClassID), Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_PPR2RegClassID),
Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_ZPR2StridedRegClassID),
Reg))
NumRegs = 2;
else if (MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_DDDRegClassID),
Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_ZPR3RegClassID),
Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_QQQRegClassID),
Reg))
NumRegs = 3;
else if (MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_DDDDRegClassID),
Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_ZPR4RegClassID),
Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_QQQQRegClassID),
Reg) ||
MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI,
AArch64_ZPR4StridedRegClassID),
Reg))
NumRegs = 4;
return NumRegs;
}
static unsigned get_vec_list_stride(MCInst *MI, unsigned Reg) {
unsigned Stride = 1;
if (MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_ZPR2StridedRegClassID),
Reg))
Stride = 8;
else if (MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI,
AArch64_ZPR4StridedRegClassID),
Reg))
Stride = 4;
return Stride;
}
static unsigned get_vec_list_first_reg(MCInst *MI, unsigned RegL) {
unsigned Reg = RegL;
// Now forget about the list and find out what the first register is.
if (MCRegisterInfo_getSubReg(MI->MRI, RegL, AArch64_dsub0))
Reg = MCRegisterInfo_getSubReg(MI->MRI, RegL, AArch64_dsub0);
else if (MCRegisterInfo_getSubReg(MI->MRI, RegL, AArch64_qsub0))
Reg = MCRegisterInfo_getSubReg(MI->MRI, RegL, AArch64_qsub0);
else if (MCRegisterInfo_getSubReg(MI->MRI, RegL, AArch64_zsub0))
Reg = MCRegisterInfo_getSubReg(MI->MRI, RegL, AArch64_zsub0);
else if (MCRegisterInfo_getSubReg(MI->MRI, RegL, AArch64_psub0))
Reg = MCRegisterInfo_getSubReg(MI->MRI, RegL, AArch64_psub0);
// If it's a D-reg, we need to promote it to the equivalent Q-reg before
// printing (otherwise getRegisterName fails).
if (MCRegisterClass_contains(
MCRegisterInfo_getRegClass(MI->MRI, AArch64_FPR64RegClassID),
Reg)) {
const MCRegisterClass *FPR128RC =
MCRegisterInfo_getRegClass(MI->MRI, AArch64_FPR128RegClassID);
Reg = MCRegisterInfo_getMatchingSuperReg(MI->MRI, Reg, AArch64_dsub,
FPR128RC);
}
return Reg;
}
static bool is_vector_reg(unsigned Reg) {
if ((Reg >= AArch64_Q0) && (Reg <= AArch64_Q31))
return true;
else if ((Reg >= AArch64_Z0) && (Reg <= AArch64_Z31))
return true;
else if ((Reg >= AArch64_P0) && (Reg <= AArch64_P15))
return true;
return false;
}
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride /* = 1 */)
{
while (Stride--) {
if (!is_vector_reg(Reg)) {
assert(0 && "Vector register expected!");
return 0;
}
// Vector lists can wrap around.
else if (Reg == AArch64_Q31)
Reg = AArch64_Q0;
// Vector lists can wrap around.
else if (Reg == AArch64_Z31)
Reg = AArch64_Z0;
// Vector lists can wrap around.
else if (Reg == AArch64_P15)
Reg = AArch64_P0;
else
// Assume ordered registers
++Reg;
}
return Reg;
}
static aarch64_extender llvm_to_cs_ext(AArch64_AM_ShiftExtendType ExtType) {
switch(ExtType) {
default:
return AArch64_EXT_INVALID;
case AArch64_AM_UXTB:
return AArch64_EXT_UXTB;
case AArch64_AM_UXTH:
return AArch64_EXT_UXTH;
case AArch64_AM_UXTW:
return AArch64_EXT_UXTW;
case AArch64_AM_UXTX:
return AArch64_EXT_UXTX;
case AArch64_AM_SXTB:
return AArch64_EXT_SXTB;
case AArch64_AM_SXTH:
return AArch64_EXT_SXTH;
case AArch64_AM_SXTW:
return AArch64_EXT_SXTW;
case AArch64_AM_SXTX:
return AArch64_EXT_SXTX;
}
}
static aarch64_shifter llvm_to_cs_shift(AArch64_AM_ShiftExtendType ShiftExtType) {
switch(ShiftExtType) {
default:
return AArch64_SFT_INVALID;
case AArch64_AM_LSL:
return AArch64_SFT_LSL;
case AArch64_AM_LSR:
return AArch64_SFT_LSR;
case AArch64_AM_ASR:
return AArch64_SFT_ASR;
case AArch64_AM_ROR:
return AArch64_SFT_ROR;
case AArch64_AM_MSL:
return AArch64_SFT_MSL;
}
}
/// Initializes or finishes a memory operand of Capstone (depending on \p
/// status). A memory operand in Capstone can be assembled by two LLVM operands.
/// E.g. the base register and the immediate disponent.
void AArch64_set_mem_access(MCInst *MI, bool status)
{
if (!detail_is_set(MI))
return;
set_doing_mem(MI, status);
if (status) {
if (AArch64_get_detail(MI)->op_count > 0 &&
AArch64_get_detail_op(MI, -1)->type == AArch64_OP_MEM &&
AArch64_get_detail_op(MI, -1)->mem.index == AArch64_REG_INVALID &&
AArch64_get_detail_op(MI, -1)->mem.disp == 0) {
// Previous memory operand not done yet. Select it.
AArch64_dec_op_count(MI);
return;
}
// Init a new one.
AArch64_get_detail_op(MI, 0)->type = AArch64_OP_MEM;
AArch64_get_detail_op(MI, 0)->mem.base = AArch64_REG_INVALID;
AArch64_get_detail_op(MI, 0)->mem.index = AArch64_REG_INVALID;
AArch64_get_detail_op(MI, 0)->mem.disp = 0;
#ifndef CAPSTONE_DIET
uint8_t access =
map_get_op_access(MI, AArch64_get_detail(MI)->op_count);
AArch64_get_detail_op(MI, 0)->access = access;
#endif
} else {
// done, select the next operand slot
AArch64_inc_op_count(MI);
}
}
/// Fills cs_detail with the data of the operand.
/// This function handles operands which's original printer function has no
/// specialities.
static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
unsigned OpNum) {
if (!detail_is_set(MI))
return;
// Fill cs_detail
switch (op_group) {
default:
printf("ERROR: Operand group %d not handled!\n", op_group);
assert(0);
case AArch64_OP_GROUP_Operand: {
cs_op_type primary_op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
switch (primary_op_type) {
default:
printf("Unhandled operand type 0x%x\n", primary_op_type);
assert(0);
case AArch64_OP_REG:
AArch64_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
break;
case AArch64_OP_IMM:
AArch64_set_detail_op_imm(MI, OpNum, AArch64_OP_IMM,
MCInst_getOpVal(MI, OpNum));
break;
case AArch64_OP_FP: {
// printOperand does not handle FP operands. But sometimes
// is is used to print FP operands as normal immediate.
AArch64_get_detail_op(MI, 0)->type = AArch64_OP_IMM;
AArch64_get_detail_op(MI, 0)->imm = MCInst_getOpVal(MI, OpNum);
AArch64_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
AArch64_inc_op_count(MI);
break;
}
}
break;
}
case AArch64_OP_GROUP_AddSubImm: {
unsigned Val = (MCInst_getOpVal(MI, OpNum) & 0xfff);
AArch64_set_detail_op_imm(MI, OpNum, AArch64_OP_IMM, Val);
// Shift is added in printShifter()
break;
}
case AArch64_OP_GROUP_AdrLabel: {
int64_t Offset = MCInst_getOpVal(MI, OpNum);
AArch64_set_detail_op_imm(MI, OpNum, AArch64_OP_IMM, (MI->address & -4096) + Offset);
break;
}
case AArch64_OP_GROUP_AdrpLabel: {
int64_t Offset = MCInst_getOpVal(MI, OpNum) * 4096;
AArch64_set_detail_op_imm(MI, OpNum, AArch64_OP_IMM, (MI->address & -4096) + Offset);
break;
}
case AArch64_OP_GROUP_AlignedLabel: {
int64_t Offset = MCInst_getOpVal(MI, OpNum) * 4;
AArch64_set_detail_op_imm(MI, OpNum, AArch64_OP_IMM, MI->address + Offset);
break;
}
case AArch64_OP_GROUP_AMNoIndex: {
AArch64_set_detail_op_mem(MI, OpNum, MCInst_getOpVal(MI, OpNum));
break;
}
case AArch64_OP_GROUP_ArithExtend: {
unsigned Val = MCInst_getOpVal(MI, OpNum);
AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val);
unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val);
AArch64_get_detail_op(MI, -1)->ext = llvm_to_cs_ext(ExtType);
AArch64_get_detail_op(MI, -1)->shift.value = ShiftVal;
AArch64_get_detail_op(MI, -1)->shift.type = AArch64_SFT_LSL;
break;
}
case AArch64_OP_GROUP_BarriernXSOption: {
unsigned Val = MCInst_getOpVal(MI, OpNum);
aarch64_sysop sysop;
const AArch64DBnXS_DBnXS *DB = AArch64DBnXS_lookupDBnXSByEncoding(Val);
if (DB)
sysop.imm = DB->SysImm;
else
sysop.imm.raw_val = Val;
sysop.sub_type = AArch64_OP_DBNXS;
AArch64_set_detail_op_sys(MI, OpNum, sysop, AArch64_OP_SYSIMM);
break;
}
case AArch64_OP_GROUP_BarrierOption: {
unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Opcode = MCInst_getOpcode(MI);
aarch64_sysop sysop;
if (Opcode == AArch64_ISB) {
const AArch64ISB_ISB *ISB = AArch64ISB_lookupISBByEncoding(Val);
if (ISB)
sysop.alias = ISB->SysAlias;
else
sysop.alias.raw_val = Val;
sysop.sub_type = AArch64_OP_ISB;
AArch64_set_detail_op_sys(MI, OpNum, sysop, AArch64_OP_SYSALIAS);
} else if (Opcode == AArch64_TSB) {
const AArch64TSB_TSB *TSB = AArch64TSB_lookupTSBByEncoding(Val);