chenzhiwo

Chengzhi Chen chenzhiwo

Achievements

7 stars written in Verilog

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,643 1,019 Updated Mar 24, 2021

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,160 291 Updated Dec 27, 2024

IC design and development should be faster，simpler and more reliable

Verilog 1,879 573 Updated Dec 31, 2021

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

Verilog 429 44 Updated Jul 24, 2024

FPGA-based Nintendo Entertainment System Emulator

Verilog 262 65 Updated Jan 16, 2024

A look ahead, round-robing parametrized arbiter written in Verilog.

Verilog 41 22 Updated May 22, 2020

Lichee Tang FPGA board examples

Verilog 32 6 Updated Dec 15, 2018