diff --git a/samples/audio/sof/prj.conf b/samples/audio/sof/prj.conf index 74c52d4a3e1e..2be9a027b56e 100644 --- a/samples/audio/sof/prj.conf +++ b/samples/audio/sof/prj.conf @@ -2,6 +2,7 @@ CONFIG_SOF=y CONFIG_SMP=n CONFIG_LOG=y CONFIG_MP_NUM_CPUS=1 +CONFIG_BUILD_OUTPUT_BIN=n # Requires heap_info() be implemented, but no Zephyr wrapper CONFIG_DEBUG_MEMORY_USAGE_SCAN=n diff --git a/soc/xtensa/intel_adsp/common/CMakeLists.txt b/soc/xtensa/intel_adsp/common/CMakeLists.txt index 8a323c21bc70..d49817183ead 100644 --- a/soc/xtensa/intel_adsp/common/CMakeLists.txt +++ b/soc/xtensa/intel_adsp/common/CMakeLists.txt @@ -27,7 +27,5 @@ if(CONFIG_SOC_SERIES_INTEL_CAVS_V15 OR CONFIG_SOC_SERIES_INTEL_CAVS_V18 OR CONFIG_SOC_SERIES_INTEL_CAVS_V20 OR CONFIG_SOC_SERIES_INTEL_CAVS_V25) - zephyr_library_sources(soc.c) - zephyr_library_sources(soc_mp.c) include(bootloader.cmake) endif() diff --git a/soc/xtensa/intel_adsp/common/adsp.c b/soc/xtensa/intel_adsp/common/adsp.c index f5bab48fa892..6ed4f93b5a49 100644 --- a/soc/xtensa/intel_adsp/common/adsp.c +++ b/soc/xtensa/intel_adsp/common/adsp.c @@ -17,8 +17,6 @@ LOG_MODULE_REGISTER(sof); #include #include -#include - /* * Sets up the host windows so that the host can see the memory * content on the DSP SRAM. diff --git a/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h b/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h deleted file mode 100644 index fe06ab660379..000000000000 --- a/soc/xtensa/intel_adsp/common/include/cavs/mailbox.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifndef __CAVS_MAILBOX_H__ -#define __CAVS_MAILBOX_H__ - -#include -#include - -/* - * The Window Region on HPSRAM for cAVS platforms is organised like this :- - * +--------------------------------------------------------------------------+ - * | Offset | Region | Size | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE | - * +---------------------+----------------+-----------------------------------+ - * - * Note: For suecreek SRAM_SW_REG window does not exist - MAILBOX_SW_REG_BASE - * and MAILBOX_SW_REG_BASE are equal to 0 - */ - - /* window 3 - trace */ -#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE -#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE - - /* window 2 debug, exception and stream */ -#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE -#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE - -#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE -#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE -#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE - -#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE -#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE -#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE) - - /* window 1 inbox/downlink and FW registers */ -#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE -#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE - - /* window 0 */ -#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE -#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE - -#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE -#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE - -#endif /* __CAVS_MAILBOX_H__ */