From 43ffcc571cfd300b6a84d0ce0ca42cb783d5c8d9 Mon Sep 17 00:00:00 2001
From: Hao Liu <Hao.Liu@arm.com>
Date: Mon, 30 Dec 2013 02:12:46 +0000
Subject: [PATCH] [AArch64]Can't select shift left 0 of type v1i64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198192 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AArch64/AArch64InstrNEON.td     | 14 ++++++++++----
 test/CodeGen/AArch64/neon-shl-ashr-lshr.ll | 14 ++++++++++++++
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td
index b1da41853d52..9849fe44b228 100644
--- a/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/lib/Target/AArch64/AArch64InstrNEON.td
@@ -4637,7 +4637,13 @@ multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
                 (INSTD FPR64:$Rn, imm:$Imm)>;
 }
 
-class Neon_ScalarShiftImm_V1_D_size_patterns<SDPatternOperator opnode,
+class Neon_ScalarShiftLImm_V1_D_size_patterns<SDPatternOperator opnode,
+                                             Instruction INSTD>
+  : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
+            (v1i64 (Neon_vdup (i32 shl_imm64:$Imm))))),
+        (INSTD FPR64:$Rn, imm:$Imm)>;
+
+class Neon_ScalarShiftRImm_V1_D_size_patterns<SDPatternOperator opnode,
                                              Instruction INSTD>
   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
             (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
@@ -4704,13 +4710,13 @@ multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
 // Pattern to match llvm.arm.* intrinsic.
-def : Neon_ScalarShiftImm_V1_D_size_patterns<sra, SSHRddi>;
+def : Neon_ScalarShiftRImm_V1_D_size_patterns<sra, SSHRddi>;
 
 // Scalar Unsigned Shift Right (Immediate)
 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
 // Pattern to match llvm.arm.* intrinsic.
-def : Neon_ScalarShiftImm_V1_D_size_patterns<srl, USHRddi>;
+def : Neon_ScalarShiftRImm_V1_D_size_patterns<srl, USHRddi>;
 
 // Scalar Signed Rounding Shift Right (Immediate)
 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
@@ -4744,7 +4750,7 @@ def : Neon_ScalarShiftRImm_accum_D_size_patterns
 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
 // Pattern to match llvm.arm.* intrinsic.
-def : Neon_ScalarShiftImm_V1_D_size_patterns<shl, SHLddi>;
+def : Neon_ScalarShiftLImm_V1_D_size_patterns<shl, SHLddi>;
 
 // Signed Saturating Shift Left (Immediate)
 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
diff --git a/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll b/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll
index 13912f417c48..af2ab4d4246c 100644
--- a/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll
+++ b/test/CodeGen/AArch64/neon-shl-ashr-lshr.ll
@@ -182,4 +182,18 @@ define <2 x i64> @ashr.v2i64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK: sshl v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
   %c = ashr <2 x i64> %a, %b
   ret <2 x i64> %c
+}
+
+define <1 x i64> @shl.v1i64.0(<1 x i64> %a) {
+; CHECK-LABEL: shl.v1i64.0:
+; CHECK: shl d{{[0-9]+}}, d{{[0-9]+}}, #0
+  %c = shl <1 x i64> %a, zeroinitializer
+  ret <1 x i64> %c
+}
+
+define <2 x i32> @shl.v2i32.0(<2 x i32> %a) {
+; CHECK-LABEL: shl.v2i32.0:
+; CHECK: shl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #0
+  %c = shl <2 x i32> %a, zeroinitializer
+  ret <2 x i32> %c
 }
\ No newline at end of file