From 15a812c07cfd7efb6d09fa7b42a82dfaec306a3f Mon Sep 17 00:00:00 2001 From: Eugene Zelenko Date: Fri, 6 Jan 2017 00:30:53 +0000 Subject: [PATCH] [AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291197 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelLowering.cpp | 110 +++++++++++++----- lib/Target/AArch64/AArch64InstrInfo.cpp | 71 +++++++---- .../AArch64/AArch64InstructionSelector.h | 8 +- .../AArch64/AArch64MachineFunctionInfo.h | 48 ++++---- lib/Target/AArch64/AArch64TargetMachine.cpp | 38 ++++-- .../AArch64/AsmParser/AArch64AsmParser.cpp | 89 +++++++++++--- .../Disassembler/AArch64Disassembler.h | 9 +- .../MCTargetDesc/AArch64ELFObjectWriter.cpp | 13 ++- .../MCTargetDesc/AArch64MCCodeEmitter.cpp | 27 +++-- .../MCTargetDesc/AArch64TargetStreamer.cpp | 3 +- lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp | 48 +++++--- .../Lanai/Disassembler/LanaiDisassembler.h | 7 +- .../Lanai/InstPrinter/LanaiInstPrinter.h | 13 ++- lib/Target/Lanai/LanaiISelLowering.cpp | 42 ++++--- lib/Target/Lanai/LanaiRegisterInfo.h | 9 +- .../MCTargetDesc/LanaiELFObjectWriter.cpp | 12 +- .../Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp | 23 ++-- .../Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp | 15 ++- 18 files changed, 386 insertions(+), 199 deletions(-) diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 4c98253878e4..74a01835171b 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -11,28 +11,79 @@ // //===----------------------------------------------------------------------===// -#include "AArch64ISelLowering.h" #include "AArch64CallingConvention.h" #include "AArch64MachineFunctionInfo.h" +#include "AArch64ISelLowering.h" #include "AArch64PerfectShuffle.h" +#include "AArch64RegisterInfo.h" #include "AArch64Subtarget.h" -#include "AArch64TargetMachine.h" -#include "AArch64TargetObjectFile.h" #include "MCTargetDesc/AArch64AddressingModes.h" +#include "Utils/AArch64BaseInfo.h" +#include "llvm/ADT/APFloat.h" +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/ADT/Triple.h" +#include "llvm/ADT/Twine.h" #include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/MachineValueType.h" +#include "llvm/CodeGen/RuntimeLibcalls.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" +#include "llvm/CodeGen/ValueTypes.h" +#include "llvm/IR/Attributes.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/DebugLoc.h" +#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" #include "llvm/IR/GetElementPtrTypeIterator.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/IR/Instruction.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/Intrinsics.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/OperandTraits.h" #include "llvm/IR/Type.h" +#include "llvm/IR/Use.h" +#include "llvm/IR/Value.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetCallingConv.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + using namespace llvm; #define DEBUG_TYPE "aarch64-lower" @@ -59,7 +110,6 @@ static const MVT MVT_CC = MVT::i32; AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI) : TargetLowering(TM), Subtarget(&STI) { - // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so // we have to make something up. Arbitrarily, choose ZeroOrOne. setBooleanContents(ZeroOrOneBooleanContent); @@ -218,7 +268,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); - setOperationAction(ISD::CTPOP, MVT::i32, Custom); setOperationAction(ISD::CTPOP, MVT::i64, Custom); @@ -3632,6 +3681,7 @@ SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op, llvm_unreachable("Unexpected platform trying to use TLS"); } + SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast(Op.getOperand(1))->get(); @@ -4549,7 +4599,6 @@ SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op, return DAG.getMergeValues(Ops, dl); } - /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two /// i64 values and take a 2 x i64 value to shift plus a shift amount. SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op, @@ -5074,10 +5123,11 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, int WindowBase; int WindowScale; - bool operator ==(SDValue OtherVec) { return Vec == OtherVec; } ShuffleSourceInfo(SDValue Vec) - : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0), - WindowScale(1) {} + : Vec(Vec), MinElt(std::numeric_limits::max()), MaxElt(0), + ShuffleVec(Vec), WindowBase(0), WindowScale(1) {} + + bool operator ==(SDValue OtherVec) { return Vec == OtherVec; } }; // First gather all vectors used as an immediate source for this BUILD_VECTOR @@ -7028,7 +7078,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, return true; } case Intrinsic::aarch64_ldaxp: - case Intrinsic::aarch64_ldxp: { + case Intrinsic::aarch64_ldxp: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i128; Info.ptrVal = I.getArgOperand(0); @@ -7038,9 +7088,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.readMem = true; Info.writeMem = false; return true; - } case Intrinsic::aarch64_stlxp: - case Intrinsic::aarch64_stxp: { + case Intrinsic::aarch64_stxp: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i128; Info.ptrVal = I.getArgOperand(2); @@ -7050,7 +7099,6 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.readMem = false; Info.writeMem = true; return true; - } default: break; } @@ -8044,13 +8092,13 @@ static SDValue tryCombineToEXTR(SDNode *N, SDValue LHS; uint32_t ShiftLHS = 0; - bool LHSFromHi = 0; + bool LHSFromHi = false; if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi)) return SDValue(); SDValue RHS; uint32_t ShiftRHS = 0; - bool RHSFromHi = 0; + bool RHSFromHi = false; if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) return SDValue(); @@ -9732,52 +9780,51 @@ static bool isEquivalentMaskless(unsigned CC, unsigned width, switch(CC) { case AArch64CC::LE: - case AArch64CC::GT: { + case AArch64CC::GT: if ((AddConstant == 0) || (CompConstant == MaxUInt - 1 && AddConstant < 0) || (AddConstant >= 0 && CompConstant < 0) || (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant)) return true; - } break; + break; case AArch64CC::LT: - case AArch64CC::GE: { + case AArch64CC::GE: if ((AddConstant == 0) || (AddConstant >= 0 && CompConstant <= 0) || (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant)) return true; - } break; + break; case AArch64CC::HI: - case AArch64CC::LS: { + case AArch64CC::LS: if ((AddConstant >= 0 && CompConstant < 0) || (AddConstant <= 0 && CompConstant >= -1 && CompConstant < AddConstant + MaxUInt)) return true; - } break; + break; case AArch64CC::PL: - case AArch64CC::MI: { + case AArch64CC::MI: if ((AddConstant == 0) || (AddConstant > 0 && CompConstant <= 0) || (AddConstant < 0 && CompConstant <= AddConstant)) return true; - } break; + break; case AArch64CC::LO: - case AArch64CC::HS: { + case AArch64CC::HS: if ((AddConstant >= 0 && CompConstant <= 0) || (AddConstant <= 0 && CompConstant >= 0 && CompConstant <= AddConstant + MaxUInt)) return true; - } break; + break; case AArch64CC::EQ: - case AArch64CC::NE: { + case AArch64CC::NE: if ((AddConstant > 0 && CompConstant < 0) || (AddConstant < 0 && CompConstant >= 0 && CompConstant < AddConstant + MaxUInt) || (AddConstant >= 0 && CompConstant >= 0 && CompConstant >= AddConstant) || (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant)) - return true; - } break; + break; case AArch64CC::VS: case AArch64CC::VC: case AArch64CC::AL: @@ -10501,7 +10548,7 @@ Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, if (ValTy->getPrimitiveSizeInBits() == 128) { Intrinsic::ID Int = IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp; - Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int); + Function *Ldxr = Intrinsic::getDeclaration(M, Int); Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext())); Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi"); @@ -10517,7 +10564,7 @@ Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, Type *Tys[] = { Addr->getType() }; Intrinsic::ID Int = IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr; - Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys); + Function *Ldxr = Intrinsic::getDeclaration(M, Int, Tys); return Builder.CreateTruncOrBitCast( Builder.CreateCall(Ldxr, Addr), @@ -10527,8 +10574,7 @@ Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance( IRBuilder<> &Builder) const { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); - Builder.CreateCall( - llvm::Intrinsic::getDeclaration(M, Intrinsic::aarch64_clrex)); + Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::aarch64_clrex)); } Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder, diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp index 56e585cdadec..5c8acba26aab 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -14,16 +14,37 @@ #include "AArch64InstrInfo.h" #include "AArch64Subtarget.h" #include "MCTargetDesc/AArch64AddressingModes.h" +#include "Utils/AArch64BaseInfo.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/StackMaps.h" +#include "llvm/IR/DebugLoc.h" +#include "llvm/IR/GlobalValue.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CodeGen.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/TargetRegistry.h" -#include +#include "llvm/Support/MathExtras.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Target/TargetSubtargetInfo.h" +#include +#include +#include +#include using namespace llvm; @@ -529,19 +550,19 @@ void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB, default: llvm_unreachable("Unknown branch opcode in Cond"); case AArch64::CBZW: - Is64Bit = 0; + Is64Bit = false; CC = AArch64CC::EQ; break; case AArch64::CBZX: - Is64Bit = 1; + Is64Bit = true; CC = AArch64CC::EQ; break; case AArch64::CBNZW: - Is64Bit = 0; + Is64Bit = false; CC = AArch64CC::NE; break; case AArch64::CBNZX: - Is64Bit = 1; + Is64Bit = true; CC = AArch64CC::NE; break; } @@ -1044,7 +1065,7 @@ static unsigned sForm(MachineInstr &Instr) { case AArch64::SUBSWri: case AArch64::SUBSXrr: case AArch64::SUBSXri: - return Instr.getOpcode();; + return Instr.getOpcode(); case AArch64::ADDWrr: return AArch64::ADDSWrr; case AArch64::ADDWri: return AArch64::ADDSWri; @@ -1072,12 +1093,15 @@ static bool areCFlagsAliveInSuccessors(MachineBasicBlock *MBB) { } namespace { + struct UsedNZCV { - bool N; - bool Z; - bool C; - bool V; - UsedNZCV(): N(false), Z(false), C(false), V(false) {} + bool N = false; + bool Z = false; + bool C = false; + bool V = false; + + UsedNZCV() = default; + UsedNZCV& operator |=(const UsedNZCV& UsedFlags) { this->N |= UsedFlags.N; this->Z |= UsedFlags.Z; @@ -1086,6 +1110,7 @@ struct UsedNZCV { return *this; } }; + } // end anonymous namespace /// Find a condition code used by the instruction. @@ -1561,7 +1586,7 @@ bool AArch64InstrInfo::isScaledAddr(const MachineInstr &MI) const { /// Check all MachineMemOperands for a hint to suppress pairing. bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) const { - return any_of(MI.memoperands(), [](MachineMemOperand *MMO) { + return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) { return MMO->getFlags() & MOSuppressPair; }); } @@ -1994,7 +2019,7 @@ static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, void AArch64InstrInfo::copyPhysRegTuple( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, - llvm::ArrayRef Indices) const { + ArrayRef Indices) const { assert(Subtarget.hasNEON() && "Unexpected register copy without NEON"); const TargetRegisterInfo *TRI = &getRegisterInfo(); @@ -3029,7 +3054,7 @@ bool AArch64InstrInfo::useMachineCombiner() const { return true; } -// + // True when Opc sets flag static bool isCombineInstrSettingFlag(unsigned Opc) { switch (Opc) { @@ -3048,7 +3073,7 @@ static bool isCombineInstrSettingFlag(unsigned Opc) { } return false; } -// + // 32b Opcodes that can be combined with a MUL static bool isCombineInstrCandidate32(unsigned Opc) { switch (Opc) { @@ -3067,7 +3092,7 @@ static bool isCombineInstrCandidate32(unsigned Opc) { } return false; } -// + // 64b Opcodes that can be combined with a MUL static bool isCombineInstrCandidate64(unsigned Opc) { switch (Opc) { @@ -3086,7 +3111,7 @@ static bool isCombineInstrCandidate64(unsigned Opc) { } return false; } -// + // FP Opcodes that can be combined with a FMUL static bool isCombineInstrCandidateFP(const MachineInstr &Inst) { switch (Inst.getOpcode()) { @@ -3108,7 +3133,7 @@ static bool isCombineInstrCandidateFP(const MachineInstr &Inst) { } return false; } -// + // Opcodes that can be combined with a MUL static bool isCombineInstrCandidate(unsigned Opc) { return (isCombineInstrCandidate32(Opc) || isCombineInstrCandidate64(Opc)); @@ -3298,7 +3323,7 @@ static bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl &Patterns) { if (!isCombineInstrCandidateFP(Root)) - return 0; + return false; MachineBasicBlock &MBB = *Root.getParent(); bool Found = false; @@ -4064,8 +4089,6 @@ void AArch64InstrInfo::genAlternativeCodeSequence( // Record MUL and ADD/SUB for deletion DelInstrs.push_back(MUL); DelInstrs.push_back(&Root); - - return; } /// \brief Replace csincr-branch sequence by simple conditional branch @@ -4241,6 +4264,7 @@ AArch64InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { ArrayRef> AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags() const { using namespace AArch64II; + static const std::pair TargetFlags[] = { {MO_PAGE, "aarch64-page"}, {MO_PAGEOFF, "aarch64-pageoff"}, @@ -4255,6 +4279,7 @@ AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags() const { ArrayRef> AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { using namespace AArch64II; + static const std::pair TargetFlags[] = { {MO_GOT, "aarch64-got"}, {MO_NC, "aarch64-nc"}, diff --git a/lib/Target/AArch64/AArch64InstructionSelector.h b/lib/Target/AArch64/AArch64InstructionSelector.h index 0d44e696ac20..2c6e5a912fb7 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.h +++ b/lib/Target/AArch64/AArch64InstructionSelector.h @@ -17,6 +17,7 @@ #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" namespace llvm { + class AArch64InstrInfo; class AArch64RegisterBankInfo; class AArch64RegisterInfo; @@ -29,7 +30,7 @@ class AArch64InstructionSelector : public InstructionSelector { const AArch64Subtarget &STI, const AArch64RegisterBankInfo &RBI); - virtual bool select(MachineInstr &I) const override; + bool select(MachineInstr &I) const override; private: /// tblgen-erated 'select' implementation, used as the initial selector for @@ -43,5 +44,6 @@ class AArch64InstructionSelector : public InstructionSelector { const AArch64RegisterBankInfo &RBI; }; -} // End llvm namespace. -#endif +} // end namespace llvm + +#endif // LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H diff --git a/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/lib/Target/AArch64/AArch64MachineFunctionInfo.h index ca2860afe13d..f0bffe544158 100644 --- a/lib/Target/AArch64/AArch64MachineFunctionInfo.h +++ b/lib/Target/AArch64/AArch64MachineFunctionInfo.h @@ -14,17 +14,18 @@ #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H #define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/MC/MCLinkerOptimizationHint.h" +#include namespace llvm { /// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and /// contains private AArch64-specific information for each MachineFunction. class AArch64FunctionInfo final : public MachineFunctionInfo { - /// Number of bytes of arguments this function has on the stack. If the callee /// is expected to restore the argument stack this should be a multiple of 16, /// all usable during a tail call. @@ -34,16 +35,16 @@ class AArch64FunctionInfo final : public MachineFunctionInfo { /// space to a function with 16-bytes then misalignment of this value would /// make a stack adjustment necessary, which could not be undone by the /// callee. - unsigned BytesInStackArgArea; + unsigned BytesInStackArgArea = 0; /// The number of bytes to restore to deallocate space for incoming /// arguments. Canonically 0 in the C calling convention, but non-zero when /// callee is expected to pop the args. - unsigned ArgumentStackToRestore; + unsigned ArgumentStackToRestore = 0; /// HasStackFrame - True if this function has a stack frame. Set by /// determineCalleeSaves(). - bool HasStackFrame; + bool HasStackFrame = false; /// \brief Amount of stack frame size, not including callee-saved registers. unsigned LocalStackSize; @@ -53,54 +54,44 @@ class AArch64FunctionInfo final : public MachineFunctionInfo { /// \brief Number of TLS accesses using the special (combinable) /// _TLS_MODULE_BASE_ symbol. - unsigned NumLocalDynamicTLSAccesses; + unsigned NumLocalDynamicTLSAccesses = 0; /// \brief FrameIndex for start of varargs area for arguments passed on the /// stack. - int VarArgsStackIndex; + int VarArgsStackIndex = 0; /// \brief FrameIndex for start of varargs area for arguments passed in /// general purpose registers. - int VarArgsGPRIndex; + int VarArgsGPRIndex = 0; /// \brief Size of the varargs area for arguments passed in general purpose /// registers. - unsigned VarArgsGPRSize; + unsigned VarArgsGPRSize = 0; /// \brief FrameIndex for start of varargs area for arguments passed in /// floating-point registers. - int VarArgsFPRIndex; + int VarArgsFPRIndex = 0; /// \brief Size of the varargs area for arguments passed in floating-point /// registers. - unsigned VarArgsFPRSize; + unsigned VarArgsFPRSize = 0; /// True if this function has a subset of CSRs that is handled explicitly via /// copies. - bool IsSplitCSR; + bool IsSplitCSR = false; /// True when the stack gets realigned dynamically because the size of stack /// frame is unknown at compile time. e.g., in case of VLAs. - bool StackRealigned; + bool StackRealigned = false; /// True when the callee-save stack area has unused gaps that may be used for /// other stack allocations. - bool CalleeSaveStackHasFreeSpace; + bool CalleeSaveStackHasFreeSpace = false; public: - AArch64FunctionInfo() - : BytesInStackArgArea(0), ArgumentStackToRestore(0), HasStackFrame(false), - NumLocalDynamicTLSAccesses(0), VarArgsStackIndex(0), VarArgsGPRIndex(0), - VarArgsGPRSize(0), VarArgsFPRIndex(0), VarArgsFPRSize(0), - IsSplitCSR(false), StackRealigned(false), - CalleeSaveStackHasFreeSpace(false) {} - - explicit AArch64FunctionInfo(MachineFunction &MF) - : BytesInStackArgArea(0), ArgumentStackToRestore(0), HasStackFrame(false), - NumLocalDynamicTLSAccesses(0), VarArgsStackIndex(0), VarArgsGPRIndex(0), - VarArgsGPRSize(0), VarArgsFPRIndex(0), VarArgsFPRSize(0), - IsSplitCSR(false), StackRealigned(false), - CalleeSaveStackHasFreeSpace(false) { + AArch64FunctionInfo() = default; + + explicit AArch64FunctionInfo(MachineFunction &MF) { (void)MF; } @@ -193,6 +184,7 @@ class AArch64FunctionInfo final : public MachineFunctionInfo { MILOHContainer LOHContainerSet; SetOfInstructions LOHRelated; }; -} // End llvm namespace -#endif +} // end namespace llvm + +#endif // LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index e4ef0d4bb8db..d2883941e2c4 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -15,24 +15,35 @@ #include "AArch64InstructionSelector.h" #include "AArch64LegalizerInfo.h" #include "AArch64RegisterBankInfo.h" +#include "AArch64Subtarget.h" #include "AArch64TargetMachine.h" #include "AArch64TargetObjectFile.h" #include "AArch64TargetTransformInfo.h" +#include "MCTargetDesc/AArch64MCTargetDesc.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/Triple.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/GlobalISel/GISelAccessor.h" #include "llvm/CodeGen/GlobalISel/IRTranslator.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/Attributes.h" #include "llvm/IR/Function.h" -#include "llvm/IR/LegacyPassManager.h" -#include "llvm/InitializePasses.h" +#include "llvm/MC/MCTargetOptions.h" +#include "llvm/Pass.h" +#include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/TargetRegistry.h" +#include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/Scalar.h" +#include +#include + using namespace llvm; static cl::opt EnableCCMP("aarch64-enable-ccmp", @@ -154,9 +165,9 @@ extern "C" void LLVMInitializeAArch64Target() { //===----------------------------------------------------------------------===// static std::unique_ptr createTLOF(const Triple &TT) { if (TT.isOSBinFormatMachO()) - return make_unique(); + return llvm::make_unique(); - return make_unique(); + return llvm::make_unique(); } // Helper function to build a DataLayout string @@ -202,29 +213,35 @@ AArch64TargetMachine::AArch64TargetMachine( initAsmInfo(); } -AArch64TargetMachine::~AArch64TargetMachine() {} +AArch64TargetMachine::~AArch64TargetMachine() = default; #ifdef LLVM_BUILD_GLOBAL_ISEL namespace { + struct AArch64GISelActualAccessor : public GISelAccessor { std::unique_ptr CallLoweringInfo; std::unique_ptr InstSelector; std::unique_ptr Legalizer; std::unique_ptr RegBankInfo; + const CallLowering *getCallLowering() const override { return CallLoweringInfo.get(); } + const InstructionSelector *getInstructionSelector() const override { return InstSelector.get(); } + const LegalizerInfo *getLegalizerInfo() const override { return Legalizer.get(); } + const RegisterBankInfo *getRegBankInfo() const override { return RegBankInfo.get(); } }; -} // End anonymous namespace. + +} // end anonymous namespace #endif const AArch64Subtarget * @@ -287,6 +304,7 @@ AArch64beTargetMachine::AArch64beTargetMachine( : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} namespace { + /// AArch64 Code Generator Pass Configuration Options. class AArch64PassConfig : public TargetPassConfig { public: @@ -324,7 +342,8 @@ class AArch64PassConfig : public TargetPassConfig { void addPreSched2() override; void addPreEmitPass() override; }; -} // namespace + +} // end anonymous namespace TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() { return TargetIRAnalysis([this](const Function &F) { @@ -414,14 +433,17 @@ bool AArch64PassConfig::addIRTranslator() { addPass(new IRTranslator()); return false; } + bool AArch64PassConfig::addLegalizeMachineIR() { addPass(new Legalizer()); return false; } + bool AArch64PassConfig::addRegBankSelect() { addPass(new RegBankSelect()); return false; } + bool AArch64PassConfig::addGlobalInstructionSelect() { addPass(new InstructionSelect()); return false; diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index db84afacf30e..b86a283b40d4 100644 --- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -9,45 +9,62 @@ #include "MCTargetDesc/AArch64AddressingModes.h" #include "MCTargetDesc/AArch64MCExpr.h" +#include "MCTargetDesc/AArch64MCTargetDesc.h" #include "MCTargetDesc/AArch64TargetStreamer.h" #include "Utils/AArch64BaseInfo.h" +#include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCLinkerOptimizationHint.h" #include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" +#include "llvm/MC/MCParser/MCAsmParserExtension.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/Support/Debug.h" +#include "llvm/MC/MCTargetOptions.h" +#include "llvm/MC/SubtargetFeature.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/SourceMgr.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Support/SMLoc.h" #include "llvm/Support/TargetParser.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" +#include +#include +#include #include +#include +#include +#include +#include + using namespace llvm; namespace { -class AArch64Operand; - class AArch64AsmParser : public MCTargetAsmParser { private: StringRef Mnemonic; ///< Instruction mnemonic. // Map of register aliases registers via the .req directive. - StringMap > RegisterReqs; + StringMap> RegisterReqs; AArch64TargetStreamer &getTargetStreamer() { MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); @@ -118,6 +135,7 @@ class AArch64AsmParser : public MCTargetAsmParser { #include "AArch64GenAsmMatcher.inc" }; bool IsILP32; + AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, STI) { @@ -143,9 +161,6 @@ class AArch64AsmParser : public MCTargetAsmParser { MCSymbolRefExpr::VariantKind &DarwinRefKind, int64_t &Addend); }; -} // end anonymous namespace - -namespace { /// AArch64Operand - Instances of this class represent a parsed AArch64 machine /// instruction. @@ -531,6 +546,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 0 && Val < 2); } + bool isImm0_7() const { if (!isImm()) return false; @@ -540,6 +556,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 0 && Val < 8); } + bool isImm1_8() const { if (!isImm()) return false; @@ -549,6 +566,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val > 0 && Val < 9); } + bool isImm0_15() const { if (!isImm()) return false; @@ -558,6 +576,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 0 && Val < 16); } + bool isImm1_16() const { if (!isImm()) return false; @@ -567,6 +586,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val > 0 && Val < 17); } + bool isImm0_31() const { if (!isImm()) return false; @@ -576,6 +596,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 0 && Val < 32); } + bool isImm1_31() const { if (!isImm()) return false; @@ -585,6 +606,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 1 && Val < 32); } + bool isImm1_32() const { if (!isImm()) return false; @@ -594,6 +616,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 1 && Val < 33); } + bool isImm0_63() const { if (!isImm()) return false; @@ -603,6 +626,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 0 && Val < 64); } + bool isImm1_63() const { if (!isImm()) return false; @@ -612,6 +636,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 1 && Val < 64); } + bool isImm1_64() const { if (!isImm()) return false; @@ -621,6 +646,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 1 && Val < 65); } + bool isImm0_127() const { if (!isImm()) return false; @@ -630,6 +656,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 0 && Val < 128); } + bool isImm0_255() const { if (!isImm()) return false; @@ -639,6 +666,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 0 && Val < 256); } + bool isImm0_65535() const { if (!isImm()) return false; @@ -648,6 +676,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 0 && Val < 65536); } + bool isImm32_63() const { if (!isImm()) return false; @@ -657,6 +686,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = MCE->getValue(); return (Val >= 32 && Val < 64); } + bool isLogicalImm32() const { if (!isImm()) return false; @@ -669,6 +699,7 @@ class AArch64Operand : public MCParsedAsmOperand { Val &= 0xFFFFFFFF; return AArch64_AM::isLogicalImmediate(Val, 32); } + bool isLogicalImm64() const { if (!isImm()) return false; @@ -677,6 +708,7 @@ class AArch64Operand : public MCParsedAsmOperand { return false; return AArch64_AM::isLogicalImmediate(MCE->getValue(), 64); } + bool isLogicalImm32Not() const { if (!isImm()) return false; @@ -686,6 +718,7 @@ class AArch64Operand : public MCParsedAsmOperand { int64_t Val = ~MCE->getValue() & 0xFFFFFFFF; return AArch64_AM::isLogicalImmediate(Val, 32); } + bool isLogicalImm64Not() const { if (!isImm()) return false; @@ -694,7 +727,9 @@ class AArch64Operand : public MCParsedAsmOperand { return false; return AArch64_AM::isLogicalImmediate(~MCE->getValue(), 64); } + bool isShiftedImm() const { return Kind == k_ShiftedImm; } + bool isAddSubImm() const { if (!isShiftedImm() && !isImm()) return false; @@ -737,6 +772,7 @@ class AArch64Operand : public MCParsedAsmOperand { // code deal with it. return true; } + bool isAddSubImmNeg() const { if (!isShiftedImm() && !isImm()) return false; @@ -756,7 +792,9 @@ class AArch64Operand : public MCParsedAsmOperand { const MCConstantExpr *CE = dyn_cast(Expr); return CE != nullptr && CE->getValue() < 0 && -CE->getValue() <= 0xfff; } + bool isCondCode() const { return Kind == k_CondCode; } + bool isSIMDImmType10() const { if (!isImm()) return false; @@ -765,6 +803,7 @@ class AArch64Operand : public MCParsedAsmOperand { return false; return AArch64_AM::isAdvSIMDModImmType10(MCE->getValue()); } + bool isBranchTarget26() const { if (!isImm()) return false; @@ -776,6 +815,7 @@ class AArch64Operand : public MCParsedAsmOperand { return false; return (Val >= -(0x2000000 << 2) && Val <= (0x1ffffff << 2)); } + bool isPCRelLabel19() const { if (!isImm()) return false; @@ -787,6 +827,7 @@ class AArch64Operand : public MCParsedAsmOperand { return false; return (Val >= -(0x40000 << 2) && Val <= (0x3ffff << 2)); } + bool isBranchTarget14() const { if (!isImm()) return false; @@ -891,40 +932,49 @@ class AArch64Operand : public MCParsedAsmOperand { bool isFPImm() const { return Kind == k_FPImm; } bool isBarrier() const { return Kind == k_Barrier; } bool isSysReg() const { return Kind == k_SysReg; } + bool isMRSSystemRegister() const { if (!isSysReg()) return false; return SysReg.MRSReg != -1U; } + bool isMSRSystemRegister() const { if (!isSysReg()) return false; return SysReg.MSRReg != -1U; } + bool isSystemPStateFieldWithImm0_1() const { if (!isSysReg()) return false; return (SysReg.PStateField == AArch64PState::PAN || SysReg.PStateField == AArch64PState::UAO); } + bool isSystemPStateFieldWithImm0_15() const { if (!isSysReg() || isSystemPStateFieldWithImm0_1()) return false; return SysReg.PStateField != -1U; } + bool isReg() const override { return Kind == k_Register && !Reg.isVector; } bool isVectorReg() const { return Kind == k_Register && Reg.isVector; } + bool isVectorRegLo() const { return Kind == k_Register && Reg.isVector && AArch64MCRegisterClasses[AArch64::FPR128_loRegClassID].contains( Reg.RegNum); } + bool isGPR32as64() const { return Kind == k_Register && !Reg.isVector && AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); } + bool isWSeqPair() const { return Kind == k_Register && !Reg.isVector && AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains( Reg.RegNum); } + bool isXSeqPair() const { return Kind == k_Register && !Reg.isVector && AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains( @@ -957,19 +1007,25 @@ class AArch64Operand : public MCParsedAsmOperand { bool isVectorIndex1() const { return Kind == k_VectorIndex && VectorIndex.Val == 1; } + bool isVectorIndexB() const { return Kind == k_VectorIndex && VectorIndex.Val < 16; } + bool isVectorIndexH() const { return Kind == k_VectorIndex && VectorIndex.Val < 8; } + bool isVectorIndexS() const { return Kind == k_VectorIndex && VectorIndex.Val < 4; } + bool isVectorIndexD() const { return Kind == k_VectorIndex && VectorIndex.Val < 2; } + bool isToken() const override { return Kind == k_Token; } + bool isTokenEqual(StringRef Str) const { return Kind == k_Token && getToken() == Str; } @@ -1006,6 +1062,7 @@ class AArch64Operand : public MCParsedAsmOperand { AArch64_AM::ShiftExtendType ET = getShiftExtendType(); return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX; } + bool isExtendLSL64() const { if (!isExtend()) return false; @@ -1836,11 +1893,10 @@ void AArch64Operand::print(raw_ostream &OS) const { OS << ""; break; } - case k_PSBHint: { + case k_PSBHint: OS << getPSBHintName(); break; - } - case k_ShiftExtend: { + case k_ShiftExtend: OS << "<" << AArch64_AM::getShiftExtendName(getShiftExtendType()) << " #" << getShiftExtendAmount(); if (!hasShiftExtendAmount()) @@ -1848,7 +1904,6 @@ void AArch64Operand::print(raw_ostream &OS) const { OS << '>'; break; } - } } /// @name Auto-generated Match Functions @@ -2469,7 +2524,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc, Expr = MCConstantExpr::create(op2, getContext()); \ Operands.push_back( \ AArch64Operand::CreateImm(Expr, S, getLoc(), getContext())); \ - } while (0) + } while (false) if (Mnemonic == "ic") { if (!Op.compare_lower("ialluis")) { @@ -3979,7 +4034,6 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } } - switch (MatchResult) { case Match_Success: { // Perform range checking and other semantic validations @@ -4550,7 +4604,6 @@ unsigned AArch64AsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, return Match_InvalidOperand; } - OperandMatchResultTy AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) { @@ -4601,7 +4654,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) { return MatchOperand_ParseFail; } - if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 || + if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 || (isXReg && !XRegClass.contains(SecondReg)) || (isWReg && !WRegClass.contains(SecondReg))) { Error(E,"expected second odd register of a " @@ -4610,7 +4663,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) { } unsigned Pair = 0; - if(isXReg) { + if (isXReg) { Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64, &AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID]); } else { diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.h b/lib/Target/AArch64/Disassembler/AArch64Disassembler.h index 24e353cf4b96..bc2f7f181699 100644 --- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.h +++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.h @@ -17,15 +17,12 @@ namespace llvm { -class MCInst; -class raw_ostream; - class AArch64Disassembler : public MCDisassembler { public: AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : MCDisassembler(STI, Ctx) {} - ~AArch64Disassembler() {} + ~AArch64Disassembler() override = default; MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef Bytes, @@ -33,6 +30,6 @@ class AArch64Disassembler : public MCDisassembler { raw_ostream &CStream) const override; }; -} // namespace llvm +} // end namespace llvm -#endif +#endif // LLVM_LIB_TARGET_AARCH64_DISASSEMBLER_AARCH64DISASSEMBLER_H diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp index a1edb3cef46a..c954c0eb2c6b 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp @@ -17,25 +17,30 @@ #include "MCTargetDesc/AArch64MCTargetDesc.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCFixup.h" #include "llvm/MC/MCValue.h" +#include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" +#include +#include using namespace llvm; namespace { + class AArch64ELFObjectWriter : public MCELFObjectTargetWriter { public: AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian, bool IsILP32); - ~AArch64ELFObjectWriter() override; + ~AArch64ELFObjectWriter() override = default; protected: unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const override; bool IsILP32; -private: }; -} + +} // end anonymous namespace AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian, @@ -44,8 +49,6 @@ AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, /*HasRelocationAddend*/ true), IsILP32(IsILP32) {} -AArch64ELFObjectWriter::~AArch64ELFObjectWriter() {} - #define R_CLS(rtype) \ IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype #define BAD_ILP32_MOV(lp64rtype) "ILP32 absolute MOV relocation not "\ diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp index f7058cdf2373..62dfa59483eb 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -15,15 +15,23 @@ #include "MCTargetDesc/AArch64FixupKinds.h" #include "MCTargetDesc/AArch64MCExpr.h" #include "Utils/AArch64BaseInfo.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include +#include + using namespace llvm; #define DEBUG_TYPE "mccodeemitter" @@ -37,13 +45,12 @@ class AArch64MCCodeEmitter : public MCCodeEmitter { MCContext &Ctx; const MCInstrInfo &MCII; - AArch64MCCodeEmitter(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT - void operator=(const AArch64MCCodeEmitter &); // DO NOT IMPLEMENT public: AArch64MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) : Ctx(ctx), MCII(mcii) {} - - ~AArch64MCCodeEmitter() override {} + AArch64MCCodeEmitter(const AArch64MCCodeEmitter &) = delete; + void operator=(const AArch64MCCodeEmitter &) = delete; + ~AArch64MCCodeEmitter() override = default; // getBinaryCodeForInstr - TableGen'erated function for getting the // binary encoding for an instruction. @@ -181,12 +188,6 @@ class AArch64MCCodeEmitter : public MCCodeEmitter { } // end anonymous namespace -MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII, - const MCRegisterInfo &MRI, - MCContext &Ctx) { - return new AArch64MCCodeEmitter(MCII, Ctx); -} - /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned @@ -601,3 +602,9 @@ unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison( #define ENABLE_INSTR_PREDICATE_VERIFIER #include "AArch64GenMCCodeEmitter.inc" + +MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, + MCContext &Ctx) { + return new AArch64MCCodeEmitter(MCII, Ctx); +} diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp index 3e86a42d5be6..1b949b54590c 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp @@ -13,6 +13,7 @@ #include "AArch64TargetStreamer.h" #include "llvm/MC/ConstantPools.h" + using namespace llvm; // @@ -21,7 +22,7 @@ using namespace llvm; AArch64TargetStreamer::AArch64TargetStreamer(MCStreamer &S) : MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()) {} -AArch64TargetStreamer::~AArch64TargetStreamer() {} +AArch64TargetStreamer::~AArch64TargetStreamer() = default; // The constant pool handling is shared by all AArch64TargetStreamer // implementations. diff --git a/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp index 903f92a04431..57ead973b56e 100644 --- a/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp +++ b/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp @@ -8,23 +8,41 @@ //===----------------------------------------------------------------------===// #include "Lanai.h" +#include "LanaiAluCode.h" +#include "LanaiCondCode.h" #include "MCTargetDesc/LanaiMCExpr.h" -#include "MCTargetDesc/LanaiMCTargetDesc.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/StringSwitch.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/SMLoc.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Support/TargetRegistry.h" +#include +#include +#include +#include +#include namespace llvm { + +// Auto-generated by TableGen +static unsigned MatchRegisterName(StringRef Name); + namespace { + struct LanaiOperand; class LanaiAsmParser : public MCTargetAsmParser { @@ -80,9 +98,6 @@ class LanaiAsmParser : public MCTargetAsmParser { const MCSubtargetInfo &SubtargetInfo; }; -// Auto-generated by TableGen -static unsigned MatchRegisterName(llvm::StringRef Name); - // LanaiOperand - Instances of this class represented a parsed machine // instruction struct LanaiOperand : public MCParsedAsmOperand { @@ -627,6 +642,8 @@ struct LanaiOperand : public MCParsedAsmOperand { } }; +} // end anonymous namespace + bool LanaiAsmParser::ParseDirective(AsmToken /*DirectiveId*/) { return true; } bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, @@ -680,11 +697,11 @@ std::unique_ptr LanaiAsmParser::parseRegister() { if (Lexer.getKind() == AsmToken::Identifier) { RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); if (RegNum == 0) - return 0; + return nullptr; Parser.Lex(); // Eat identifier token return LanaiOperand::createReg(RegNum, Start, End); } - return 0; + return nullptr; } bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, @@ -701,15 +718,15 @@ bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, std::unique_ptr LanaiAsmParser::parseIdentifier() { SMLoc Start = Parser.getTok().getLoc(); SMLoc End = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - const MCExpr *Res, *RHS = 0; + const MCExpr *Res, *RHS = nullptr; LanaiMCExpr::VariantKind Kind = LanaiMCExpr::VK_Lanai_None; if (Lexer.getKind() != AsmToken::Identifier) - return 0; + return nullptr; StringRef Identifier; if (Parser.parseIdentifier(Identifier)) - return 0; + return nullptr; // Check if identifier has a modifier if (Identifier.equals_lower("hi")) @@ -722,24 +739,24 @@ std::unique_ptr LanaiAsmParser::parseIdentifier() { if (Kind != LanaiMCExpr::VK_Lanai_None) { if (Lexer.getKind() != AsmToken::LParen) { Error(Lexer.getLoc(), "Expected '('"); - return 0; + return nullptr; } Lexer.Lex(); // lex '(' // Parse identifier if (Parser.parseIdentifier(Identifier)) - return 0; + return nullptr; } // If addition parse the RHS. if (Lexer.getKind() == AsmToken::Plus && Parser.parseExpression(RHS)) - return 0; + return nullptr; // For variants parse the final ')' if (Kind != LanaiMCExpr::VK_Lanai_None) { if (Lexer.getKind() != AsmToken::RParen) { Error(Lexer.getLoc(), "Expected ')'"); - return 0; + return nullptr; } Lexer.Lex(); // lex ')' } @@ -771,7 +788,7 @@ std::unique_ptr LanaiAsmParser::parseImmediate() { if (!Parser.parseExpression(ExprVal)) return LanaiOperand::createImm(ExprVal, Start, End); default: - return 0; + return nullptr; } } @@ -1204,10 +1221,9 @@ bool LanaiAsmParser::ParseInstruction(ParseInstructionInfo & /*Info*/, #define GET_REGISTER_MATCHER #define GET_MATCHER_IMPLEMENTATION #include "LanaiGenAsmMatcher.inc" -} // namespace extern "C" void LLVMInitializeLanaiAsmParser() { RegisterMCAsmParser x(getTheLanaiTarget()); } -} // namespace llvm +} // end namespace llvm diff --git a/lib/Target/Lanai/Disassembler/LanaiDisassembler.h b/lib/Target/Lanai/Disassembler/LanaiDisassembler.h index a317cd88ad63..e0c19e8ea644 100644 --- a/lib/Target/Lanai/Disassembler/LanaiDisassembler.h +++ b/lib/Target/Lanai/Disassembler/LanaiDisassembler.h @@ -20,14 +20,11 @@ namespace llvm { -class MCInst; -class raw_ostream; - class LanaiDisassembler : public MCDisassembler { public: LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx); - ~LanaiDisassembler() override {} + ~LanaiDisassembler() override = default; // getInstruction - See MCDisassembler. MCDisassembler::DecodeStatus @@ -36,6 +33,6 @@ class LanaiDisassembler : public MCDisassembler { raw_ostream &CStream) const override; }; -} // namespace llvm +} // end namespace llvm #endif // LLVM_LIB_TARGET_LANAI_DISASSEMBLER_LANAIDISASSEMBLER_H diff --git a/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.h b/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.h index 1c9d186ad819..59904fbaa318 100644 --- a/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.h +++ b/lib/Target/Lanai/InstPrinter/LanaiInstPrinter.h @@ -14,10 +14,10 @@ #ifndef LLVM_LIB_TARGET_LANAI_INSTPRINTER_LANAIINSTPRINTER_H #define LLVM_LIB_TARGET_LANAI_INSTPRINTER_LANAIINSTPRINTER_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCInstPrinter.h" namespace llvm { -class MCOperand; class LanaiInstPrinter : public MCInstPrinter { public: @@ -28,14 +28,14 @@ class LanaiInstPrinter : public MCInstPrinter { void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override; void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, - const char *Modifier = 0); + const char *Modifier = nullptr); void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printMemRiOperand(const MCInst *MI, int OpNo, raw_ostream &O, - const char *Modifier = 0); + const char *Modifier = nullptr); void printMemRrOperand(const MCInst *MI, int OpNo, raw_ostream &O, - const char *Modifier = 0); + const char *Modifier = nullptr); void printMemSplsOperand(const MCInst *MI, int OpNo, raw_ostream &O, - const char *Modifier = 0); + const char *Modifier = nullptr); void printCCOperand(const MCInst *MI, int OpNo, raw_ostream &O); void printAluOperand(const MCInst *MI, int OpNo, raw_ostream &O); void printHi16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); @@ -60,6 +60,7 @@ class LanaiInstPrinter : public MCInstPrinter { bool printMemoryStoreIncrement(const MCInst *MI, raw_ostream &Ostream, StringRef Opcode, int AddOffset); }; -} // namespace llvm + +} // end namespace llvm #endif // LLVM_LIB_TARGET_LANAI_INSTPRINTER_LANAIINSTPRINTER_H diff --git a/lib/Target/Lanai/LanaiISelLowering.cpp b/lib/Target/Lanai/LanaiISelLowering.cpp index ae7870e07d42..d156294a0b0c 100644 --- a/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/lib/Target/Lanai/LanaiISelLowering.cpp @@ -11,31 +11,46 @@ // //===----------------------------------------------------------------------===// -#include "LanaiISelLowering.h" - #include "Lanai.h" +#include "LanaiCondCode.h" +#include "LanaiISelLowering.h" #include "LanaiMachineFunctionInfo.h" #include "LanaiSubtarget.h" -#include "LanaiTargetMachine.h" #include "LanaiTargetObjectFile.h" +#include "MCTargetDesc/LanaiBaseInfo.h" +#include "llvm/ADT/APInt.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/StringSwitch.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/CodeGen/MachineValueType.h" +#include "llvm/CodeGen/RuntimeLibcalls.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" -#include "llvm/IR/GlobalAlias.h" -#include "llvm/IR/GlobalVariable.h" -#include "llvm/IR/Intrinsics.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/CodeGen.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetCallingConv.h" +#include "llvm/Target/TargetMachine.h" +#include +#include +#include +#include +#include #define DEBUG_TYPE "lanai-lower" @@ -195,6 +210,7 @@ SDValue LanaiTargetLowering::LowerOperation(SDValue Op, llvm_unreachable("unimplemented operand"); } } + //===----------------------------------------------------------------------===// // Lanai Inline Assembly Support //===----------------------------------------------------------------------===// @@ -244,7 +260,7 @@ LanaiTargetLowering::getSingleConstraintMatchWeight( Value *CallOperandVal = Info.CallOperandVal; // If we don't have a value, we can't do a match, // but allow it at the lowest weight. - if (CallOperandVal == NULL) + if (CallOperandVal == nullptr) return CW_Default; // Look at the constraint type. switch (*Constraint) { @@ -270,7 +286,7 @@ LanaiTargetLowering::getSingleConstraintMatchWeight( void LanaiTargetLowering::LowerAsmOperandForConstraint( SDValue Op, std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const { - SDValue Result(0, 0); + SDValue Result(nullptr, 0); // Only support length 1 constraints for now. if (Constraint.length() > 1) @@ -676,7 +692,7 @@ SDValue LanaiTargetLowering::LowerCCCCallTo( } else { assert(VA.isMemLoc()); - if (StackPtr.getNode() == 0) + if (StackPtr.getNode() == nullptr) StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP, getPointerTy(DAG.getDataLayout())); @@ -1120,7 +1136,7 @@ const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const { case LanaiISD::SMALL: return "LanaiISD::SMALL"; default: - return NULL; + return nullptr; } } diff --git a/lib/Target/Lanai/LanaiRegisterInfo.h b/lib/Target/Lanai/LanaiRegisterInfo.h index 8b84bbc460e8..c6e459076ebc 100644 --- a/lib/Target/Lanai/LanaiRegisterInfo.h +++ b/lib/Target/Lanai/LanaiRegisterInfo.h @@ -21,9 +21,6 @@ namespace llvm { -class TargetInstrInfo; -class Type; - struct LanaiRegisterInfo : public LanaiGenRegisterInfo { LanaiRegisterInfo(); @@ -32,7 +29,7 @@ struct LanaiRegisterInfo : public LanaiGenRegisterInfo { // Code Generation virtual methods. const uint16_t * - getCalleeSavedRegs(const MachineFunction *MF = 0) const override; + getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override; BitVector getReservedRegs(const MachineFunction &MF) const override; @@ -42,7 +39,7 @@ struct LanaiRegisterInfo : public LanaiGenRegisterInfo { void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, - RegScavenger *RS = NULL) const override; + RegScavenger *RS = nullptr) const override; bool canRealignStack(const MachineFunction &MF) const override; @@ -58,6 +55,6 @@ struct LanaiRegisterInfo : public LanaiGenRegisterInfo { int getDwarfRegNum(unsigned RegNum, bool IsEH) const; }; -} // namespace llvm +} // end namespace llvm #endif // LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H diff --git a/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp b/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp index e30d5e9a18eb..e02bba529bd5 100644 --- a/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp +++ b/lib/Target/Lanai/MCTargetDesc/LanaiELFObjectWriter.cpp @@ -9,20 +9,19 @@ #include "MCTargetDesc/LanaiBaseInfo.h" #include "MCTargetDesc/LanaiFixupKinds.h" -#include "MCTargetDesc/LanaiMCTargetDesc.h" #include "llvm/MC/MCELFObjectWriter.h" -#include "llvm/MC/MCSymbol.h" +#include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { + class LanaiELFObjectWriter : public MCELFObjectTargetWriter { public: explicit LanaiELFObjectWriter(uint8_t OSABI); - ~LanaiELFObjectWriter() override; + ~LanaiELFObjectWriter() override = default; protected: unsigned getRelocType(MCContext &Ctx, const MCValue &Target, @@ -30,14 +29,13 @@ class LanaiELFObjectWriter : public MCELFObjectTargetWriter { bool needsRelocateWithSymbol(const MCSymbol &SD, unsigned Type) const override; }; -} // namespace + +} // end anonymous namespace LanaiELFObjectWriter::LanaiELFObjectWriter(uint8_t OSABI) : MCELFObjectTargetWriter(/*Is64Bit_=*/false, OSABI, ELF::EM_LANAI, /*HasRelocationAddend=*/true) {} -LanaiELFObjectWriter::~LanaiELFObjectWriter() {} - unsigned LanaiELFObjectWriter::getRelocType(MCContext & /*Ctx*/, const MCValue & /*Target*/, const MCFixup &Fixup, diff --git a/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp b/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp index ce68b7e24dba..00cce92c2e28 100644 --- a/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp +++ b/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp @@ -12,37 +12,42 @@ //===----------------------------------------------------------------------===// #include "Lanai.h" +#include "LanaiAluCode.h" #include "MCTargetDesc/LanaiBaseInfo.h" #include "MCTargetDesc/LanaiFixupKinds.h" #include "MCTargetDesc/LanaiMCExpr.h" -#include "MCTargetDesc/LanaiMCTargetDesc.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCFixup.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/raw_ostream.h" +#include +#include #define DEBUG_TYPE "mccodeemitter" STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); namespace llvm { + namespace { + class LanaiMCCodeEmitter : public MCCodeEmitter { - LanaiMCCodeEmitter(const LanaiMCCodeEmitter &); // DO NOT IMPLEMENT - void operator=(const LanaiMCCodeEmitter &); // DO NOT IMPLEMENT const MCInstrInfo &InstrInfo; MCContext &Context; public: LanaiMCCodeEmitter(const MCInstrInfo &MCII, MCContext &C) : InstrInfo(MCII), Context(C) {} - - ~LanaiMCCodeEmitter() override {} + LanaiMCCodeEmitter(const LanaiMCCodeEmitter &) = delete; + void operator=(const LanaiMCCodeEmitter &) = delete; + ~LanaiMCCodeEmitter() override = default; // The functions below are called by TableGen generated functions for getting // the binary encoding of instructions/opereands. @@ -86,6 +91,8 @@ class LanaiMCCodeEmitter : public MCCodeEmitter { const MCSubtargetInfo &STI) const; }; +} // end anonymous namespace + Lanai::Fixups FixupKind(const MCExpr *Expr) { if (isa(Expr)) return Lanai::FIXUP_LANAI_21; @@ -298,8 +305,8 @@ unsigned LanaiMCCodeEmitter::getBranchTargetOpValue( } #include "LanaiGenMCCodeEmitter.inc" -} // namespace -} // namespace llvm + +} // end namespace llvm llvm::MCCodeEmitter * llvm::createLanaiMCCodeEmitter(const MCInstrInfo &InstrInfo, diff --git a/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp b/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp index c2f8c0f7ad50..a47ff9ff3d61 100644 --- a/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp +++ b/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp @@ -11,16 +11,21 @@ // //===----------------------------------------------------------------------===// +#include "LanaiMCAsmInfo.h" #include "LanaiMCTargetDesc.h" - #include "InstPrinter/LanaiInstPrinter.h" -#include "LanaiMCAsmInfo.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" +#include +#include #define GET_INSTRINFO_MC_DESC #include "LanaiGenInstrInfo.inc" @@ -70,7 +75,7 @@ static MCInstPrinter *createLanaiMCInstPrinter(const Triple & /*T*/, const MCRegisterInfo &MRI) { if (SyntaxVariant == 0) return new LanaiInstPrinter(MAI, MII, MRI); - return 0; + return nullptr; } static MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple, @@ -79,6 +84,7 @@ static MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple, } namespace { + class LanaiMCInstrAnalysis : public MCInstrAnalysis { public: explicit LanaiMCInstrAnalysis(const MCInstrInfo *Info) @@ -107,6 +113,7 @@ class LanaiMCInstrAnalysis : public MCInstrAnalysis { } } }; + } // end anonymous namespace static MCInstrAnalysis *createLanaiInstrAnalysis(const MCInstrInfo *Info) { @@ -131,7 +138,7 @@ extern "C" void LLVMInitializeLanaiTargetMC() { // Register the MC code emitter TargetRegistry::RegisterMCCodeEmitter(getTheLanaiTarget(), - llvm::createLanaiMCCodeEmitter); + createLanaiMCCodeEmitter); // Register the ASM Backend TargetRegistry::RegisterMCAsmBackend(getTheLanaiTarget(),