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Commits on Jan 16, 2017

• [XRay] Implement the llvm-xray graph subcommand

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  dwblaikie

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• Attempt to workaround MSVC build issue where I suspect an enum class constant 0 is considered a possible null pointer

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• [PowerPC] Expand ISEL instruction into if-then-else sequence.

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  Tony Jiang

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• [InstCombine] fix names in canEvaluateShiftedShift(); NFC

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• [InstCombine] use m_APInt to allow shift-shift folds for vectors with splat constants

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• [InstCombine] add tests to show missed vector folds; NFC

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• PR31650: Refer to enum constant when initializing llvm::None constant

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  dwblaikie

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• [NVPTX] Add blank line to NVPTXUsage.rst to appease the Sphinx.

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  Justin Lebar

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• [InstCombine] refactor shift-of-shift folds; NFCI

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• [InstCombine][SSE] Tests showing missed opportunities to pass demanded elts through a packss/packus truncation

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  RKSimon

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• [llvm-xray] Fix android build

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  labath

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• [AArch64] Falkor supports Rounding Double Multiply Add/Subtract instructions.

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  Chad Rosier

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• Revert r292132: [globalisel] Tablegen-erate current Register Bank Information'...

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  dsandersllvm

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• Fix use-after-free bug in AffectedValueCallbackVH::allUsesReplacedWith

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  Hal Finkel

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• [globalisel] Tablegen-erate current Register Bank Information

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• Revert "[PowerPC] Expand ISEL instruction into if-then-else sequence."

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  Tony Jiang

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• [SelectionDAG] Add knownbits support for BITREVERSE

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• [PowerPC] Expand ISEL instruction into if-then-else sequence.

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  Tony Jiang

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• DWARFDebugInfoTest.cpp: Don't use ArrayRef with initializer. It was allocated locally.

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• [X86][SSE] Test showing missing BITREVERSE knownbits support

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  RKSimon

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• [mips] Correct c.cond.fmt instruction definition.

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  Simon Dardis

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• [SelectionDAG] Add support for BITREVERSE constant folding

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  RKSimon

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• [X86][SSE] Tests showing missing BITREVERSE constant folding

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• [InstCombine][SSE] Add DemandedElts support for PSHUFB instructions

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• [X86] Merge the disassemblers handling of the different TYPE_RELs by getting the size information from the ENCODING field. NFCI

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• [X86] Reduce the number of operand 'types' the disassembler needs to deal with. NFCI

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• [AVX-512] Teach the disassembler about all of the EVEX gather and scatter instructions.

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• [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a different encoding than regular addressing modes.

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• Fix typos. NFC

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• [AVX-512] Add more gather/scatter encoding test cases.

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• [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQD

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• [AVX-512] Fix register class in one of the gather/scatter memory operands so that all 32 bit registers can be allowed.

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Commits on Jan 15, 2017

• [InstCombine] add tests to show missed vector folds; NFC

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• Empty line. NFC.

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• Use getLoopLatch in place of isLoopSimplifyForm

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