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wbuart.txt
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wbuart.txt
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################################################################################
##
## Filename: wbuart.txt
##
## Project: AutoFPGA, a utility for composing FPGA designs from peripherals
##
## Purpose: To describe a UART for autogen to work with.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2017-2020, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
# The prefix is used to create a series of bus data lines for interaction with
# the bus. In this case, these will be uart_sel, uart_stall, uart_ack, and
# uart_data.
@PREFIX=uart
# The number of addressable registers this peripheral has on the wishbone bus.
# Set this to zero to have no bus presence.
@NADDR= 4
# The type of peripheral. This can either:
# NOBUS Doesn't reply on the bus
# SINGLE, for a peripheral that only has one address, and whose result
# is available on every clock. In the future, these may be
# gathered together into a singleio.v file.
# DOUBLE, for a peripheral that takes one clock to access before its
# value is available on its output. This might be true for a
# peripheral that has several single-clocked registers within it,
# which then selects from among these registers in one clock
# cycle. In the future, these may be gathered together into a
# doubleio.v file.
# MEMORY
# OTHER (the default), for a peripheral that may take *many* clocks to
# respond to a bus transaction, ... one that uses its stall
# line of a necessity.
@SLAVE.TYPE= OTHER
@SLAVE.BUS=wb
@ACCESS= CONSOLE_ACCESS
@$BAUDRATE=1000000
@$UARTSETUP.EXPR=@$CLKFREQHZ/@$.BAUDRATE
@UARTSETUP.FORMAT=31'h%08x
@$SIM.UARTSETUP.EXPR=@$UARTSETUP
@SIM.UARTSETUP.FORMAT=0x%08x
@SIM.PORTOFFSET=1
@INT.INTLIST = @$(PREFIX)rx_int @$(PREFIX)tx_int @$(PREFIX)rxf_int
@INT.INTLIST += @$(PREFIX)txf_int
@INT.UARTRX.WIRE=uartrx_int
@INT.UARTTX.WIRE=uarttx_int
@INT.UARTRXF.WIRE=uartrxf_int
@INT.UARTTXF.WIRE=uarttxf_int
@INT.UARTRX.PIC=altpic
@INT.UARTTX.PIC=altpic
@INT.UARTRXF.PIC=syspic
@INT.UARTTXF.PIC=syspic
@CTS=i_@$(PREFIX)_cts_n
@RTS=o_@$(PREFIX)_rts_n
@MAIN.PORTLIST=
// The UART console
i_@$(PREFIX)_rx, o_@$(PREFIX)_tx, @$CTS, @$RTS
@MAIN.IODECL=
input wire i_@$(PREFIX)_rx, @$CTS;
output wire o_@$(PREFIX)_tx, @$RTS;
@MAIN.INSERT=
wbuart #(.INITIAL_SETUP(@$.UARTSETUP))
@$(PREFIX)_uart(i_clk, 1'b0,
@$(SLAVE.PORTLIST),
i_@$(PREFIX)_rx, o_@$(PREFIX)_tx, @$CTS, @$RTS,
@$(PREFIX)rx_int, @$(PREFIX)tx_int,
@$(PREFIX)rxf_int, @$(PREFIX)txf_int);
@MAIN.ALT=
assign o_@$(PREFIX)_tx = 1'b1;
assign @$RTS = 1'b0;
@REGS.NOTE = // WBUART registers
@REGS.N = 4
@REGS.0 = 0 R_UART_SETUP USETUP
@REGS.1 = 1 R_UART_FIFO UFIFO
@REGS.2 = 2 R_UART_UARTRX RX
@REGS.3 = 3 R_UART_UARTTX TX
@BDEF.DEFN =
#ifndef WBUART_H
#define WBUART_H
#define UART_PARITY_NONE 0
#define UART_HWFLOW_OFF 0x40000000
#define UART_PARITY_ODD 0x04000000
#define UART_PARITY_EVEN 0x05000000
#define UART_PARITY_SPACE 0x06000000
#define UART_PARITY_MARK 0x07000000
#define UART_STOP_ONEBIT 0
#define UART_STOP_TWOBITS 0x08000000
#define UART_DATA_8BITS 0
#define UART_DATA_7BITS 0x10000000
#define UART_DATA_6BITS 0x20000000
#define UART_DATA_5BITS 0x30000000
#define UART_RX_BREAK 0x0800
#define UART_RX_FRAMEERR 0x0400
#define UART_RX_PARITYERR 0x0200
#define UART_RX_NOTREADY 0x0100
#define UART_RX_ERR (-256)
#define UART_TX_BUSY 0x0100
#define UART_TX_BREAK 0x0200
typedef struct WBUART_S {
unsigned u_setup;
unsigned u_fifo;
unsigned u_rx, u_tx;
} WBUART;
#endif // WBUART_H
@BDEF.IONAME= _@$PREFIX
@BDEF.IOTYPE= WBUART
@BDEF.OSDEF= _BOARD_HAS_WBUART
@BDEF.OSVAL=static volatile WBUART *const @$BDEF.IONAME = ((WBUART *)@$[0x%08x](REGBASE));
@RTL.MAKE.GROUP=WBUART
@RTL.MAKE.FILES= wbuart.v ufifo.v rxuart.v txuart.v
@SIM.INCLUDE=
#include "uartsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
UARTSIM *m_@$(PREFIX);
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_@$(PREFIX) = new UARTSIM(FPGAPORT+@$(SIM.PORTOFFSET),@$(SIM.UARTSETUP));
m_core->@$CTS = 0; // The sim doesnt use flow control
#endif // @$(ACCESS)
@SIM.CLOCK=@$(SLAVE.BUS.CLOCK)
@SIM.TICK=
#ifdef @$(ACCESS)
m_core->i_@$(PREFIX)_rx = (*m_@$(PREFIX))(m_core->o_@$(PREFIX)_tx);
#else
m_core->i_@$(PREFIX)_rx = 1;
#endif // @$(ACCESS)