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Commits on Aug 14, 2020

• Fixes MacOS build err--std::string vs char * in gbl_msg.err()

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  5b57538

Commits on Aug 10, 2020

• Fixes broken fatal() error, referencing STRING rather than char *

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  8ec8302

Commits on Jul 9, 2020

• Added a mention to OpenZ7 to the README

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  d1f6532

• Prepared dev branch for merge w/ master

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  34b4d55

• Merge branch 'master' into devmerge

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  f893e98

Commits on Jul 8, 2020

• Fixed empty bus logic, or one master logic, for AXI and AXI-lite

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  2c43f20

Commits on Jul 2, 2020

• AXI4/AXI4-lite buses w/ no slaves now generate a warning and empty logic, no errs

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  e14ae66

Commits on May 22, 2020

• Adjusted ICD order to be closer to alphabetical

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  bd27ce6

• Same clock check now works for hashes (the normal case) as well as clock names

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  1bec83c

• Fixed logic for single address slaves--still generate bus portlists

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  2089b8c

• Null MAIN.PORTLISTs no longer produce extraneous comments

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  368481d

• Fixed WB SLIST case default generation

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  d296bb0

• Minor updates, commented unused variables, removed ERR: ERR: errors

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  0360c7c

Commits on Mar 27, 2020

• TESTB: Update time before updating clock for that new time

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  5e8b431

• Fixed a potential infinite loop in AXI bus expansion

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  4cd08f7

• Removed address bit-select from diow_axaddr assignments

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  0cbfa39

Commits on Mar 11, 2020

• Bus address width mismatch for AXI-lite DOUBLE

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  021d4f3

• AXI-Lite DOUBLE works, AXI adjusted accordingly

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  8096ca4

Commits on Mar 10, 2020

• AXI support builds a demo project

  Show description for b6f2e20
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  b6f2e20

Commits on Feb 25, 2020

• Fixd the number of address bits in SLAVE_ADDR comments

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  295b02e

• Fixed WB, now that bus generation supports either word or byte addressing

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  cf83fc4

• Adjusted subbus for mixed word/byte addressing

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  4d9b76c

• AXI-Lite handling builds w/o warning for SINGLE buses

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  7698026

Commits on Feb 24, 2020

• Added clock reset processing

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  f6f7e79

• Added more comments to testb

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  8ac4f53

Commits on Feb 6, 2020

• Better default: case determination (hopefully) for WB SLIST

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  3e0c0d8

• Fixed vanishing CLOCK.TOP tags

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  7947ef5

• Fixed processing of passthrough interconnects and return data for wb

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  cea7770

• Checked for CLOCK.TOP property when processing constraint files

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  241cce0

• Implemented read/only write/only slave processing

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  35a801d

• Copyright bump to 2020

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  58793a7

Commits on Jan 20, 2020

• Updated demo, w/ unused logic fixed

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  9538243

• Fixed incorrect bus names in the not ifdefd pass

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  0da6b3c

Commits on Jan 3, 2020

• Initial getting started drafts in doc/

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  d63e244

Commits on Jan 1, 2020

• Added SLAVE.PORTLIST and SLAVE.PREFIX keys, to provide partial nextgen support

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  95df250

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