Skip to content
View dpt's full-sized avatar

Block or report dpt

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
12 stars written in Verilog
Clear filter

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

Verilog 998 77 Updated Dec 15, 2022

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

Verilog 632 25 Updated Nov 8, 2024

Mega Drive/Genesis core written in Verilog

Verilog 302 9 Updated Oct 20, 2024

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

Verilog 169 14 Updated Feb 19, 2025

The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.

Verilog 97 11 Updated Nov 26, 2019

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your F…

Verilog 77 33 Updated Oct 14, 2020

The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.

Verilog 9 Updated Nov 26, 2019

A high-speed replacement 65C02 CPU for the Beeb; meets timing at 80MHz, seems stable at 100MHz!

Verilog 6 3 Updated Oct 20, 2023

Acorn ARM/RISC OS POST code reader

Verilog 6 3 Updated Sep 25, 2019

****DEPRECATED PROTOTYPE**** FPGA design and firmware for Acorn Archimedes DVI output adapter

Verilog 4 Updated Dec 4, 2021

A basic Verilog and VHDL tutorial

Verilog 3 Updated Jun 10, 2020

Verilog design for ArcDVI FPGA

Verilog 1 Updated Oct 21, 2023