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guest_mips_toIR.c
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guest_mips_toIR.c
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/*--------------------------------------------------------------------*/
/*--- begin guest_mips_toIR.c ---*/
/*--------------------------------------------------------------------*/
/*
This file is part of Valgrind, a dynamic binary instrumentation
framework.
Copyright (C) 2010-2015 RT-RK
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307, USA.
The GNU General Public License is contained in the file COPYING.
*/
/* Translates MIPS code to IR. */
#include "libvex_basictypes.h"
#include "libvex_ir.h"
#include "libvex.h"
#include "libvex_guest_mips32.h"
#include "libvex_guest_mips64.h"
#include "main_util.h"
#include "main_globals.h"
#include "guest_generic_bb_to_IR.h"
#include "guest_mips_defs.h"
/*------------------------------------------------------------*/
/*--- Globals ---*/
/*------------------------------------------------------------*/
/* These are set at the start of the translation of a instruction, so
that we don't have to pass them around endlessly. CONST means does
not change during translation of the instruction. */
/* CONST: what is the host's endianness? This has to do with float vs
double register accesses on VFP, but it's complex and not properly
thought out. */
static VexEndness host_endness;
/* Whether code we're analyzing comes from a big or little endian machine */
static IREndness guest_endness;
/* Pointer to the guest code area. */
static const UChar *guest_code;
/* CONST: The guest address for the instruction currently being
translated. */
static Addr64 guest_PC_curr_instr;
/* MOD: The IRSB* into which we're generating code. */
static IRSB *irsb;
/* Is our guest binary 32 or 64bit? Set at each call to
disInstr_MIPS below. */
static Bool mode64 = False;
/* CPU has FPU and 32 dbl. prec. FP registers. */
static Bool fp_mode64 = False;
#define OFFB_PC (mode64 ? offsetof(VexGuestMIPS64State, guest_PC) : offsetof(VexGuestMIPS32State, guest_PC))
/* Define 1.0 in single and double precision. */
#define ONE_SINGLE 0x3F800000
#define ONE_DOUBLE 0x3FF0000000000000ULL
/*------------------------------------------------------------*/
/*--- Debugging output ---*/
/*------------------------------------------------------------*/
#ifndef _MSC_VER
#define DIP(format, args...) \
if (vex_traceflags & VEX_TRACE_FE) \
vex_printf(format, ## args)
#else
#define DIP(format, ...) \
if (vex_traceflags & VEX_TRACE_FE) \
vex_printf(format, __VA_ARGS__)
#endif
/*------------------------------------------------------------*/
/*--- Helper bits and pieces for deconstructing the ---*/
/*--- mips insn stream. ---*/
/*------------------------------------------------------------*/
/* ---------------- Integer registers ---------------- */
static UInt integerGuestRegOffset(UInt iregNo)
{
/* Do we care about endianness here? We do if sub-parts of integer
registers are accessed, but I don't think that ever happens on
MIPS. */
UInt ret;
if (!mode64)
switch (iregNo) {
case 0:
ret = offsetof(VexGuestMIPS32State, guest_r0); break;
case 1:
ret = offsetof(VexGuestMIPS32State, guest_r1); break;
case 2:
ret = offsetof(VexGuestMIPS32State, guest_r2); break;
case 3:
ret = offsetof(VexGuestMIPS32State, guest_r3); break;
case 4:
ret = offsetof(VexGuestMIPS32State, guest_r4); break;
case 5:
ret = offsetof(VexGuestMIPS32State, guest_r5); break;
case 6:
ret = offsetof(VexGuestMIPS32State, guest_r6); break;
case 7:
ret = offsetof(VexGuestMIPS32State, guest_r7); break;
case 8:
ret = offsetof(VexGuestMIPS32State, guest_r8); break;
case 9:
ret = offsetof(VexGuestMIPS32State, guest_r9); break;
case 10:
ret = offsetof(VexGuestMIPS32State, guest_r10); break;
case 11:
ret = offsetof(VexGuestMIPS32State, guest_r11); break;
case 12:
ret = offsetof(VexGuestMIPS32State, guest_r12); break;
case 13:
ret = offsetof(VexGuestMIPS32State, guest_r13); break;
case 14:
ret = offsetof(VexGuestMIPS32State, guest_r14); break;
case 15:
ret = offsetof(VexGuestMIPS32State, guest_r15); break;
case 16:
ret = offsetof(VexGuestMIPS32State, guest_r16); break;
case 17:
ret = offsetof(VexGuestMIPS32State, guest_r17); break;
case 18:
ret = offsetof(VexGuestMIPS32State, guest_r18); break;
case 19:
ret = offsetof(VexGuestMIPS32State, guest_r19); break;
case 20:
ret = offsetof(VexGuestMIPS32State, guest_r20); break;
case 21:
ret = offsetof(VexGuestMIPS32State, guest_r21); break;
case 22:
ret = offsetof(VexGuestMIPS32State, guest_r22); break;
case 23:
ret = offsetof(VexGuestMIPS32State, guest_r23); break;
case 24:
ret = offsetof(VexGuestMIPS32State, guest_r24); break;
case 25:
ret = offsetof(VexGuestMIPS32State, guest_r25); break;
case 26:
ret = offsetof(VexGuestMIPS32State, guest_r26); break;
case 27:
ret = offsetof(VexGuestMIPS32State, guest_r27); break;
case 28:
ret = offsetof(VexGuestMIPS32State, guest_r28); break;
case 29:
ret = offsetof(VexGuestMIPS32State, guest_r29); break;
case 30:
ret = offsetof(VexGuestMIPS32State, guest_r30); break;
case 31:
ret = offsetof(VexGuestMIPS32State, guest_r31); break;
default:
vassert(0);
break;
}
else
switch (iregNo) {
case 0:
ret = offsetof(VexGuestMIPS64State, guest_r0); break;
case 1:
ret = offsetof(VexGuestMIPS64State, guest_r1); break;
case 2:
ret = offsetof(VexGuestMIPS64State, guest_r2); break;
case 3:
ret = offsetof(VexGuestMIPS64State, guest_r3); break;
case 4:
ret = offsetof(VexGuestMIPS64State, guest_r4); break;
case 5:
ret = offsetof(VexGuestMIPS64State, guest_r5); break;
case 6:
ret = offsetof(VexGuestMIPS64State, guest_r6); break;
case 7:
ret = offsetof(VexGuestMIPS64State, guest_r7); break;
case 8:
ret = offsetof(VexGuestMIPS64State, guest_r8); break;
case 9:
ret = offsetof(VexGuestMIPS64State, guest_r9); break;
case 10:
ret = offsetof(VexGuestMIPS64State, guest_r10); break;
case 11:
ret = offsetof(VexGuestMIPS64State, guest_r11); break;
case 12:
ret = offsetof(VexGuestMIPS64State, guest_r12); break;
case 13:
ret = offsetof(VexGuestMIPS64State, guest_r13); break;
case 14:
ret = offsetof(VexGuestMIPS64State, guest_r14); break;
case 15:
ret = offsetof(VexGuestMIPS64State, guest_r15); break;
case 16:
ret = offsetof(VexGuestMIPS64State, guest_r16); break;
case 17:
ret = offsetof(VexGuestMIPS64State, guest_r17); break;
case 18:
ret = offsetof(VexGuestMIPS64State, guest_r18); break;
case 19:
ret = offsetof(VexGuestMIPS64State, guest_r19); break;
case 20:
ret = offsetof(VexGuestMIPS64State, guest_r20); break;
case 21:
ret = offsetof(VexGuestMIPS64State, guest_r21); break;
case 22:
ret = offsetof(VexGuestMIPS64State, guest_r22); break;
case 23:
ret = offsetof(VexGuestMIPS64State, guest_r23); break;
case 24:
ret = offsetof(VexGuestMIPS64State, guest_r24); break;
case 25:
ret = offsetof(VexGuestMIPS64State, guest_r25); break;
case 26:
ret = offsetof(VexGuestMIPS64State, guest_r26); break;
case 27:
ret = offsetof(VexGuestMIPS64State, guest_r27); break;
case 28:
ret = offsetof(VexGuestMIPS64State, guest_r28); break;
case 29:
ret = offsetof(VexGuestMIPS64State, guest_r29); break;
case 30:
ret = offsetof(VexGuestMIPS64State, guest_r30); break;
case 31:
ret = offsetof(VexGuestMIPS64State, guest_r31); break;
default:
vassert(0);
break;
}
return ret;
}
/* ---------------- Floating point registers ---------------- */
static UInt floatGuestRegOffset(UInt fregNo)
{
vassert(fregNo < 32);
UInt ret;
if (!mode64)
switch (fregNo) {
case 0:
ret = offsetof(VexGuestMIPS32State, guest_f0); break;
case 1:
ret = offsetof(VexGuestMIPS32State, guest_f1); break;
case 2:
ret = offsetof(VexGuestMIPS32State, guest_f2); break;
case 3:
ret = offsetof(VexGuestMIPS32State, guest_f3); break;
case 4:
ret = offsetof(VexGuestMIPS32State, guest_f4); break;
case 5:
ret = offsetof(VexGuestMIPS32State, guest_f5); break;
case 6:
ret = offsetof(VexGuestMIPS32State, guest_f6); break;
case 7:
ret = offsetof(VexGuestMIPS32State, guest_f7); break;
case 8:
ret = offsetof(VexGuestMIPS32State, guest_f8); break;
case 9:
ret = offsetof(VexGuestMIPS32State, guest_f9); break;
case 10:
ret = offsetof(VexGuestMIPS32State, guest_f10); break;
case 11:
ret = offsetof(VexGuestMIPS32State, guest_f11); break;
case 12:
ret = offsetof(VexGuestMIPS32State, guest_f12); break;
case 13:
ret = offsetof(VexGuestMIPS32State, guest_f13); break;
case 14:
ret = offsetof(VexGuestMIPS32State, guest_f14); break;
case 15:
ret = offsetof(VexGuestMIPS32State, guest_f15); break;
case 16:
ret = offsetof(VexGuestMIPS32State, guest_f16); break;
case 17:
ret = offsetof(VexGuestMIPS32State, guest_f17); break;
case 18:
ret = offsetof(VexGuestMIPS32State, guest_f18); break;
case 19:
ret = offsetof(VexGuestMIPS32State, guest_f19); break;
case 20:
ret = offsetof(VexGuestMIPS32State, guest_f20); break;
case 21:
ret = offsetof(VexGuestMIPS32State, guest_f21); break;
case 22:
ret = offsetof(VexGuestMIPS32State, guest_f22); break;
case 23:
ret = offsetof(VexGuestMIPS32State, guest_f23); break;
case 24:
ret = offsetof(VexGuestMIPS32State, guest_f24); break;
case 25:
ret = offsetof(VexGuestMIPS32State, guest_f25); break;
case 26:
ret = offsetof(VexGuestMIPS32State, guest_f26); break;
case 27:
ret = offsetof(VexGuestMIPS32State, guest_f27); break;
case 28:
ret = offsetof(VexGuestMIPS32State, guest_f28); break;
case 29:
ret = offsetof(VexGuestMIPS32State, guest_f29); break;
case 30:
ret = offsetof(VexGuestMIPS32State, guest_f30); break;
case 31:
ret = offsetof(VexGuestMIPS32State, guest_f31); break;
default:
vassert(0);
break;
}
else
switch (fregNo) {
case 0:
ret = offsetof(VexGuestMIPS64State, guest_f0); break;
case 1:
ret = offsetof(VexGuestMIPS64State, guest_f1); break;
case 2:
ret = offsetof(VexGuestMIPS64State, guest_f2); break;
case 3:
ret = offsetof(VexGuestMIPS64State, guest_f3); break;
case 4:
ret = offsetof(VexGuestMIPS64State, guest_f4); break;
case 5:
ret = offsetof(VexGuestMIPS64State, guest_f5); break;
case 6:
ret = offsetof(VexGuestMIPS64State, guest_f6); break;
case 7:
ret = offsetof(VexGuestMIPS64State, guest_f7); break;
case 8:
ret = offsetof(VexGuestMIPS64State, guest_f8); break;
case 9:
ret = offsetof(VexGuestMIPS64State, guest_f9); break;
case 10:
ret = offsetof(VexGuestMIPS64State, guest_f10); break;
case 11:
ret = offsetof(VexGuestMIPS64State, guest_f11); break;
case 12:
ret = offsetof(VexGuestMIPS64State, guest_f12); break;
case 13:
ret = offsetof(VexGuestMIPS64State, guest_f13); break;
case 14:
ret = offsetof(VexGuestMIPS64State, guest_f14); break;
case 15:
ret = offsetof(VexGuestMIPS64State, guest_f15); break;
case 16:
ret = offsetof(VexGuestMIPS64State, guest_f16); break;
case 17:
ret = offsetof(VexGuestMIPS64State, guest_f17); break;
case 18:
ret = offsetof(VexGuestMIPS64State, guest_f18); break;
case 19:
ret = offsetof(VexGuestMIPS64State, guest_f19); break;
case 20:
ret = offsetof(VexGuestMIPS64State, guest_f20); break;
case 21:
ret = offsetof(VexGuestMIPS64State, guest_f21); break;
case 22:
ret = offsetof(VexGuestMIPS64State, guest_f22); break;
case 23:
ret = offsetof(VexGuestMIPS64State, guest_f23); break;
case 24:
ret = offsetof(VexGuestMIPS64State, guest_f24); break;
case 25:
ret = offsetof(VexGuestMIPS64State, guest_f25); break;
case 26:
ret = offsetof(VexGuestMIPS64State, guest_f26); break;
case 27:
ret = offsetof(VexGuestMIPS64State, guest_f27); break;
case 28:
ret = offsetof(VexGuestMIPS64State, guest_f28); break;
case 29:
ret = offsetof(VexGuestMIPS64State, guest_f29); break;
case 30:
ret = offsetof(VexGuestMIPS64State, guest_f30); break;
case 31:
ret = offsetof(VexGuestMIPS64State, guest_f31); break;
default:
vassert(0);
break;
}
return ret;
}
/* ---------------- MIPS32 DSP ASE(r2) accumulators ---------------- */
static UInt accumulatorGuestRegOffset(UInt acNo)
{
vassert(!mode64);
vassert(acNo <= 3);
UInt ret;
switch (acNo) {
case 0:
ret = offsetof(VexGuestMIPS32State, guest_ac0); break;
case 1:
ret = offsetof(VexGuestMIPS32State, guest_ac1); break;
case 2:
ret = offsetof(VexGuestMIPS32State, guest_ac2); break;
case 3:
ret = offsetof(VexGuestMIPS32State, guest_ac3); break;
default:
vassert(0);
break;
}
return ret;
}
/* Do a endian load of a 32-bit word, regardless of the endianness of the
underlying host. */
static inline UInt getUInt(const UChar * p)
{
UInt w = 0;
if (guest_endness == Iend_LE) {
w = (w << 8) | p[3];
w = (w << 8) | p[2];
w = (w << 8) | p[1];
w = (w << 8) | p[0];
} else {
w = (w << 8) | p[0];
w = (w << 8) | p[1];
w = (w << 8) | p[2];
w = (w << 8) | p[3];
}
return w;
}
#define BITS2(_b1,_b0) \
(((_b1) << 1) | (_b0))
#define BITS3(_b2,_b1,_b0) \
(((_b2) << 2) | ((_b1) << 1) | (_b0))
#define BITS4(_b3,_b2,_b1,_b0) \
(((_b3) << 3) | ((_b2) << 2) | ((_b1) << 1) | (_b0))
#define BITS5(_b4,_b3,_b2,_b1,_b0) \
(((_b4) << 4) | BITS4((_b3),(_b2),(_b1),(_b0)))
#define BITS6(_b5,_b4,_b3,_b2,_b1,_b0) \
((BITS2((_b5),(_b4)) << 4) \
| BITS4((_b3),(_b2),(_b1),(_b0)))
#define BITS8(_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \
((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \
| BITS4((_b3),(_b2),(_b1),(_b0)))
#define LOAD_STORE_PATTERN \
t1 = newTemp(mode64 ? Ity_I64 : Ity_I32); \
if(!mode64) \
assign(t1, binop(Iop_Add32, getIReg(rs), \
mkU32(extend_s_16to32(imm)))); \
else \
assign(t1, binop(Iop_Add64, getIReg(rs), \
mkU64(extend_s_16to64(imm)))); \
#define LOADX_STORE_PATTERN \
t1 = newTemp(mode64 ? Ity_I64 : Ity_I32); \
if(!mode64) \
assign(t1, binop(Iop_Add32, getIReg(regRs), getIReg(regRt))); \
else \
assign(t1, binop(Iop_Add64, getIReg(regRs), getIReg(regRt)));
#define LWX_SWX_PATTERN64 \
t2 = newTemp(Ity_I64); \
assign(t2, binop(Iop_And64, mkexpr(t1), mkU64(0xFFFFFFFFFFFFFFFCULL))); \
t4 = newTemp(Ity_I32); \
assign(t4, mkNarrowTo32( ty, binop(Iop_And64, \
mkexpr(t1), mkU64(0x3))));
#define LWX_SWX_PATTERN64_1 \
t2 = newTemp(Ity_I64); \
assign(t2, binop(Iop_And64, mkexpr(t1), mkU64(0xFFFFFFFFFFFFFFF8ULL))); \
t4 = newTemp(Ity_I64); \
assign(t4, binop(Iop_And64, mkexpr(t1), mkU64(0x7)));
#define LWX_SWX_PATTERN \
t2 = newTemp(Ity_I32); \
assign(t2, binop(Iop_And32, mkexpr(t1), mkU32(0xFFFFFFFC))); \
t4 = newTemp(Ity_I32); \
assign(t4, binop(Iop_And32, mkexpr(t1), mkU32(0x00000003)))
#define SXXV_PATTERN(op) \
putIReg(rd, binop(op, \
getIReg(rt), \
unop(Iop_32to8, \
binop(Iop_And32, \
getIReg(rs), \
mkU32(0x0000001F) \
) \
) \
) \
)
#define SXXV_PATTERN64(op) \
putIReg(rd, mkWidenFrom32(ty, binop(op, \
mkNarrowTo32(ty, getIReg(rt)), \
unop(Iop_32to8, \
binop(Iop_And32, \
mkNarrowTo32(ty, getIReg(rs)), \
mkU32(0x0000001F) \
) \
) \
), True \
))
#define SXX_PATTERN(op) \
putIReg(rd, binop(op, getIReg(rt), mkU8(sa)));
#define ALU_PATTERN(op) \
putIReg(rd, binop(op, getIReg(rs), getIReg(rt)));
#define ALUI_PATTERN(op) \
putIReg(rt, binop(op, getIReg(rs), mkU32(imm)));
#define ALUI_PATTERN64(op) \
putIReg(rt, binop(op, getIReg(rs), mkU64(imm)));
#define ALU_PATTERN64(op) \
putIReg(rd, mkWidenFrom32(ty, binop(op, \
mkNarrowTo32(ty, getIReg(rs)), \
mkNarrowTo32(ty, getIReg(rt))), True));
#define FP_CONDITIONAL_CODE \
t3 = newTemp(Ity_I32); \
assign(t3, binop(Iop_And32, \
IRExpr_ITE( binop(Iop_CmpEQ32, mkU32(cc), mkU32(0)), \
binop(Iop_Shr32, getFCSR(), mkU8(23)), \
binop(Iop_Shr32, getFCSR(), mkU8(24+cc))), \
mkU32(0x1)));
#define ILLEGAL_INSTRUCTON \
putPC(mkU32(guest_PC_curr_instr + 4)); \
dres.jk_StopHere = Ijk_SigILL; \
dres.whatNext = Dis_StopHere;
/*------------------------------------------------------------*/
/*--- Field helpers ---*/
/*------------------------------------------------------------*/
static UInt get_opcode(UInt mipsins)
{
return (0xFC000000 & mipsins) >> 26;
}
static UInt get_rs(UInt mipsins)
{
return (0x03E00000 & mipsins) >> 21;
}
static UInt get_rt(UInt mipsins)
{
return (0x001F0000 & mipsins) >> 16;
}
static UInt get_imm(UInt mipsins)
{
return (0x0000FFFF & mipsins);
}
static UInt get_instr_index(UInt mipsins)
{
return (0x03FFFFFF & mipsins);
}
static UInt get_rd(UInt mipsins)
{
return (0x0000F800 & mipsins) >> 11;
}
static UInt get_sa(UInt mipsins)
{
return (0x000007C0 & mipsins) >> 6;
}
static UInt get_function(UInt mipsins)
{
return (0x0000003F & mipsins);
}
static UInt get_ft(UInt mipsins)
{
return (0x001F0000 & mipsins) >> 16;
}
static UInt get_fs(UInt mipsins)
{
return (0x0000F800 & mipsins) >> 11;
}
static UInt get_fd(UInt mipsins)
{
return (0x000007C0 & mipsins) >> 6;
}
static UInt get_mov_cc(UInt mipsins)
{
return (0x001C0000 & mipsins) >> 18;
}
static UInt get_bc1_cc(UInt mipsins)
{
return (0x001C0000 & mipsins) >> 18;
}
static UInt get_fpc_cc(UInt mipsins)
{
return (0x00000700 & mipsins) >> 8;
}
static UInt get_tf(UInt mipsins)
{
return (0x00010000 & mipsins) >> 16;
}
static UInt get_nd(UInt mipsins)
{
return (0x00020000 & mipsins) >> 17;
}
static UInt get_fmt(UInt mipsins)
{
return (0x03E00000 & mipsins) >> 21;
}
static UInt get_FC(UInt mipsins)
{
return (0x000000F0 & mipsins) >> 4;
}
static UInt get_cond(UInt mipsins)
{
return (0x0000000F & mipsins);
}
/* for break & syscall */
static UInt get_code(UInt mipsins)
{
return (0xFFC0 & mipsins) >> 6;
}
static UInt get_lsb(UInt mipsins)
{
return (0x7C0 & mipsins) >> 6;
}
static UInt get_msb(UInt mipsins)
{
return (0x0000F800 & mipsins) >> 11;
}
static UInt get_rot(UInt mipsins)
{
return (0x00200000 & mipsins) >> 21;
}
static UInt get_rotv(UInt mipsins)
{
return (0x00000040 & mipsins) >> 6;
}
static UInt get_sel(UInt mipsins)
{
return (0x00000007 & mipsins);
}
/* Get acc number for all MIPS32 DSP ASE(r2) instructions that use them,
except for MFHI and MFLO. */
static UInt get_acNo(UInt mipsins)
{
return (0x00001800 & mipsins) >> 11;
}
/* Get accumulator number for MIPS32 DSP ASEr2 MFHI and MFLO instructions. */
static UInt get_acNo_mfhilo(UInt mipsins)
{
return (0x00600000 & mipsins) >> 21;
}
/* Get mask field (helper function for wrdsp instruction). */
static UInt get_wrdspMask(UInt mipsins)
{
return (0x001ff800 & mipsins) >> 11;
}
/* Get mask field (helper function for rddsp instruction). */
static UInt get_rddspMask(UInt mipsins)
{
return (0x03ff0000 & mipsins) >> 16;
}
/* Get shift field (helper function for DSP ASE instructions). */
static UInt get_shift(UInt mipsins)
{
return (0x03f00000 & mipsins) >> 20;
}
/* Get immediate field for DSP ASE instructions. */
static UInt get_dspImm(UInt mipsins)
{
return (0x03ff0000 & mipsins) >> 16;
}
static Bool branch_or_jump(const UChar * addr)
{
UInt fmt;
UInt cins = getUInt(addr);
UInt opcode = get_opcode(cins);
UInt rt = get_rt(cins);
UInt function = get_function(cins);
/* bgtz, blez, bne, beq, jal */
if (opcode == 0x07 || opcode == 0x06 || opcode == 0x05 || opcode == 0x04
|| opcode == 0x03 || opcode == 0x02) {
return True;
}
/* bgez */
if (opcode == 0x01 && rt == 0x01) {
return True;
}
/* bgezal */
if (opcode == 0x01 && rt == 0x11) {
return True;
}
/* bltzal */
if (opcode == 0x01 && rt == 0x10) {
return True;
}
/* bltz */
if (opcode == 0x01 && rt == 0x00) {
return True;
}
/* jalr */
if (opcode == 0x00 && function == 0x09) {
return True;
}
/* jr */
if (opcode == 0x00 && function == 0x08) {
return True;
}
if (opcode == 0x11) {
/*bc1f & bc1t */
fmt = get_fmt(cins);
if (fmt == 0x08) {
return True;
}
}
/* bposge32 */
if (opcode == 0x01 && rt == 0x1c) {
return True;
}
/* Cavium Specific instructions. */
if (opcode == 0x32 || opcode == 0x3A || opcode == 0x36 || opcode == 0x3E) {
/* BBIT0, BBIT1, BBIT032, BBIT132 */
return True;
}
return False;
}
static Bool is_Branch_or_Jump_and_Link(const UChar * addr)
{
UInt cins = getUInt(addr);
UInt opcode = get_opcode(cins);
UInt rt = get_rt(cins);
UInt function = get_function(cins);
/* jal */
if (opcode == 0x03) {
return True;
}
/* bgezal */
if (opcode == 0x01 && rt == 0x11) {
return True;
}
/* bltzal */
if (opcode == 0x01 && rt == 0x10) {
return True;
}
/* jalr */
if (opcode == 0x00 && function == 0x09) {
return True;
}
return False;
}
static Bool is_Ret(const UChar * addr)
{
UInt cins = getUInt(addr);
UInt opcode = get_opcode(cins);
UInt rs = get_rs(cins);
UInt function = get_function(cins);
/* jr $ra */
if(opcode == 0x00 && function == 0x08 && rs == 31) {
return True;
}
return False;
}
static Bool branch_or_link_likely(const UChar * addr)
{
UInt cins = getUInt(addr);
UInt opcode = get_opcode(cins);
UInt rt = get_rt(cins);
/* bgtzl, blezl, bnel, beql */
if (opcode == 0x17 || opcode == 0x16 || opcode == 0x15 || opcode == 0x14)
return True;
/* bgezl */
if (opcode == 0x01 && rt == 0x03)
return True;
/* bgezall */
if (opcode == 0x01 && rt == 0x13)
return True;
/* bltzall */
if (opcode == 0x01 && rt == 0x12)
return True;
/* bltzl */
if (opcode == 0x01 && rt == 0x02)
return True;
return False;
}
/*------------------------------------------------------------*/
/*--- Helper bits and pieces for creating IR fragments. ---*/
/*------------------------------------------------------------*/
static IRExpr *mkU8(UInt i)
{
vassert(i < 256);
return IRExpr_Const(IRConst_U8((UChar) i));
}
/* Create an expression node for a 16-bit integer constant. */
static IRExpr *mkU16(UInt i)
{
return IRExpr_Const(IRConst_U16(i));
}
/* Create an expression node for a 32-bit integer constant. */
static IRExpr *mkU32(UInt i)
{
return IRExpr_Const(IRConst_U32(i));
}
/* Create an expression node for a 64-bit integer constant. */
static IRExpr *mkU64(ULong i)
{
return IRExpr_Const(IRConst_U64(i));
}
static IRExpr *mkexpr(IRTemp tmp)
{
return IRExpr_RdTmp(tmp);
}
static IRExpr *unop(IROp op, IRExpr * a)
{
return IRExpr_Unop(op, a);
}
static IRExpr *binop(IROp op, IRExpr * a1, IRExpr * a2)
{
return IRExpr_Binop(op, a1, a2);
}
static IRExpr *triop(IROp op, IRExpr * a1, IRExpr * a2, IRExpr * a3)
{
return IRExpr_Triop(op, a1, a2, a3);
}
static IRExpr *qop ( IROp op, IRExpr * a1, IRExpr * a2, IRExpr * a3,
IRExpr * a4 )
{
return IRExpr_Qop(op, a1, a2, a3, a4);
}
static IRExpr *load(IRType ty, IRExpr * addr)
{
return IRExpr_Load(guest_endness, ty, addr);
}
/* Add a statement to the list held by "irsb". */
static void stmt(IRStmt * st)
{
addStmtToIRSB(irsb, st);
}
static void assign(IRTemp dst, IRExpr * e)
{
stmt(IRStmt_WrTmp(dst, e));
}
static void store(IRExpr * addr, IRExpr * data)
{
stmt(IRStmt_Store(guest_endness, addr, data));
}
/* Generate a new temporary of the given type. */
static IRTemp newTemp(IRType ty)
{
vassert(isPlausibleIRType(ty));
return newIRTemp(irsb->tyenv, ty);
}
/* Generate an expression for SRC rotated right by ROT. */
static IRExpr *genROR32(IRExpr * src, Int rot)
{
vassert(rot >= 0 && rot < 32);
if (rot == 0)
return src;
return binop(Iop_Or32, binop(Iop_Shl32, src, mkU8(32 - rot)),
binop(Iop_Shr32, src, mkU8(rot)));
}
static IRExpr *genRORV32(IRExpr * src, IRExpr * rs)
{
IRTemp t0 = newTemp(Ity_I8);
IRTemp t1 = newTemp(Ity_I8);
assign(t0, unop(Iop_32to8, binop(Iop_And32, rs, mkU32(0x0000001F))));
assign(t1, binop(Iop_Sub8, mkU8(32), mkexpr(t0)));
return binop(Iop_Or32, binop(Iop_Shl32, src, mkexpr(t1)),
binop(Iop_Shr32, src, mkexpr(t0)));
}
static UShort extend_s_10to16(UInt x)
{
return (UShort) ((((Int) x) << 22) >> 22);
}
static ULong extend_s_10to32(UInt x)
{
return (ULong)((((Long) x) << 22) >> 22);
}
static ULong extend_s_10to64(UInt x)
{
return (ULong)((((Long) x) << 54) >> 54);
}
static UInt extend_s_16to32(UInt x)
{
return (UInt) ((((Int) x) << 16) >> 16);
}
static UInt extend_s_18to32(UInt x)
{
return (UInt) ((((Int) x) << 14) >> 14);
}
static ULong extend_s_16to64 ( UInt x )
{
return (ULong) ((((Long) x) << 48) >> 48);
}
static ULong extend_s_18to64 ( UInt x )
{
return (ULong) ((((Long) x) << 46) >> 46);
}