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host_amd64_defs.c
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host_amd64_defs.c
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/*---------------------------------------------------------------*/
/*--- begin host_amd64_defs.c ---*/
/*---------------------------------------------------------------*/
/*
This file is part of Valgrind, a dynamic binary instrumentation
framework.
Copyright (C) 2004-2015 OpenWorks LLP
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA.
The GNU General Public License is contained in the file COPYING.
Neither the names of the U.S. Department of Energy nor the
University of California nor the names of its contributors may be
used to endorse or promote products derived from this software
without prior written permission.
*/
#include "libvex_basictypes.h"
#include "libvex.h"
#include "libvex_trc_values.h"
#include "main_util.h"
#include "host_generic_regs.h"
#include "host_amd64_defs.h"
/* --------- Registers. --------- */
const RRegUniverse* getRRegUniverse_AMD64 ( void )
{
/* The real-register universe is a big constant, so we just want to
initialise it once. */
static RRegUniverse rRegUniverse_AMD64;
static Bool rRegUniverse_AMD64_initted = False;
/* Handy shorthand, nothing more */
RRegUniverse* ru = &rRegUniverse_AMD64;
/* This isn't thread-safe. Sigh. */
if (LIKELY(rRegUniverse_AMD64_initted))
return ru;
RRegUniverse__init(ru);
/* Add the registers. The initial segment of this array must be
those available for allocation by reg-alloc, and those that
follow are not available for allocation. */
ru->allocable_start[HRcInt64] = ru->size;
ru->regs[ru->size++] = hregAMD64_RSI();
ru->regs[ru->size++] = hregAMD64_RDI();
ru->regs[ru->size++] = hregAMD64_R8();
ru->regs[ru->size++] = hregAMD64_R9();
ru->regs[ru->size++] = hregAMD64_R12();
ru->regs[ru->size++] = hregAMD64_R13();
ru->regs[ru->size++] = hregAMD64_R14();
ru->regs[ru->size++] = hregAMD64_R15();
ru->regs[ru->size++] = hregAMD64_RBX();
ru->regs[ru->size++] = hregAMD64_R10();
ru->allocable_end[HRcInt64] = ru->size - 1;
ru->allocable_start[HRcVec128] = ru->size;
ru->regs[ru->size++] = hregAMD64_XMM3();
ru->regs[ru->size++] = hregAMD64_XMM4();
ru->regs[ru->size++] = hregAMD64_XMM5();
ru->regs[ru->size++] = hregAMD64_XMM6();
ru->regs[ru->size++] = hregAMD64_XMM7();
ru->regs[ru->size++] = hregAMD64_XMM8();
ru->regs[ru->size++] = hregAMD64_XMM9();
ru->regs[ru->size++] = hregAMD64_XMM10();
ru->regs[ru->size++] = hregAMD64_XMM11();
ru->regs[ru->size++] = hregAMD64_XMM12();
ru->allocable_end[HRcVec128] = ru->size - 1;
ru->allocable = ru->size;
/* And other regs, not available to the allocator. */
ru->regs[ru->size++] = hregAMD64_RAX();
ru->regs[ru->size++] = hregAMD64_RCX();
ru->regs[ru->size++] = hregAMD64_RDX();
ru->regs[ru->size++] = hregAMD64_RSP();
ru->regs[ru->size++] = hregAMD64_RBP();
ru->regs[ru->size++] = hregAMD64_R11();
ru->regs[ru->size++] = hregAMD64_XMM0();
ru->regs[ru->size++] = hregAMD64_XMM1();
rRegUniverse_AMD64_initted = True;
RRegUniverse__check_is_sane(ru);
return ru;
}
UInt ppHRegAMD64 ( HReg reg )
{
Int r;
static const HChar* ireg64_names[16]
= { "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" };
/* Be generic for all virtual regs. */
if (hregIsVirtual(reg)) {
return ppHReg(reg);
}
/* But specific for real regs. */
switch (hregClass(reg)) {
case HRcInt64:
r = hregEncoding(reg);
vassert(r >= 0 && r < 16);
return vex_printf("%s", ireg64_names[r]);
case HRcVec128:
r = hregEncoding(reg);
vassert(r >= 0 && r < 16);
return vex_printf("%%xmm%d", r);
default:
vpanic("ppHRegAMD64");
}
}
static UInt ppHRegAMD64_lo32 ( HReg reg )
{
Int r;
static const HChar* ireg32_names[16]
= { "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
"%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" };
/* Be generic for all virtual regs. */
if (hregIsVirtual(reg)) {
UInt written = ppHReg(reg);
written += vex_printf("d");
return written;
}
/* But specific for real regs. */
switch (hregClass(reg)) {
case HRcInt64:
r = hregEncoding(reg);
vassert(r >= 0 && r < 16);
return vex_printf("%s", ireg32_names[r]);
default:
vpanic("ppHRegAMD64_lo32: invalid regclass");
}
}
/* --------- Condition codes, Intel encoding. --------- */
const HChar* showAMD64CondCode ( AMD64CondCode cond )
{
switch (cond) {
case Acc_O: return "o";
case Acc_NO: return "no";
case Acc_B: return "b";
case Acc_NB: return "nb";
case Acc_Z: return "z";
case Acc_NZ: return "nz";
case Acc_BE: return "be";
case Acc_NBE: return "nbe";
case Acc_S: return "s";
case Acc_NS: return "ns";
case Acc_P: return "p";
case Acc_NP: return "np";
case Acc_L: return "l";
case Acc_NL: return "nl";
case Acc_LE: return "le";
case Acc_NLE: return "nle";
case Acc_ALWAYS: return "ALWAYS";
default: vpanic("ppAMD64CondCode");
}
}
/* --------- AMD64AMode: memory address expressions. --------- */
AMD64AMode* AMD64AMode_IR ( UInt imm32, HReg reg ) {
AMD64AMode* am = LibVEX_Alloc_inline(sizeof(AMD64AMode));
am->tag = Aam_IR;
am->Aam.IR.imm = imm32;
am->Aam.IR.reg = reg;
return am;
}
AMD64AMode* AMD64AMode_IRRS ( UInt imm32, HReg base, HReg indEx, Int shift ) {
AMD64AMode* am = LibVEX_Alloc_inline(sizeof(AMD64AMode));
am->tag = Aam_IRRS;
am->Aam.IRRS.imm = imm32;
am->Aam.IRRS.base = base;
am->Aam.IRRS.index = indEx;
am->Aam.IRRS.shift = shift;
vassert(shift >= 0 && shift <= 3);
return am;
}
void ppAMD64AMode ( AMD64AMode* am ) {
switch (am->tag) {
case Aam_IR:
if (am->Aam.IR.imm == 0)
vex_printf("(");
else
vex_printf("0x%x(", am->Aam.IR.imm);
ppHRegAMD64(am->Aam.IR.reg);
vex_printf(")");
return;
case Aam_IRRS:
vex_printf("0x%x(", am->Aam.IRRS.imm);
ppHRegAMD64(am->Aam.IRRS.base);
vex_printf(",");
ppHRegAMD64(am->Aam.IRRS.index);
vex_printf(",%d)", 1 << am->Aam.IRRS.shift);
return;
default:
vpanic("ppAMD64AMode");
}
}
static void addRegUsage_AMD64AMode ( HRegUsage* u, AMD64AMode* am ) {
switch (am->tag) {
case Aam_IR:
addHRegUse(u, HRmRead, am->Aam.IR.reg);
return;
case Aam_IRRS:
addHRegUse(u, HRmRead, am->Aam.IRRS.base);
addHRegUse(u, HRmRead, am->Aam.IRRS.index);
return;
default:
vpanic("addRegUsage_AMD64AMode");
}
}
static void mapRegs_AMD64AMode ( HRegRemap* m, AMD64AMode* am ) {
switch (am->tag) {
case Aam_IR:
am->Aam.IR.reg = lookupHRegRemap(m, am->Aam.IR.reg);
return;
case Aam_IRRS:
am->Aam.IRRS.base = lookupHRegRemap(m, am->Aam.IRRS.base);
am->Aam.IRRS.index = lookupHRegRemap(m, am->Aam.IRRS.index);
return;
default:
vpanic("mapRegs_AMD64AMode");
}
}
/* --------- Operand, which can be reg, immediate or memory. --------- */
AMD64RMI* AMD64RMI_Imm ( UInt imm32 ) {
AMD64RMI* op = LibVEX_Alloc_inline(sizeof(AMD64RMI));
op->tag = Armi_Imm;
op->Armi.Imm.imm32 = imm32;
return op;
}
AMD64RMI* AMD64RMI_Reg ( HReg reg ) {
AMD64RMI* op = LibVEX_Alloc_inline(sizeof(AMD64RMI));
op->tag = Armi_Reg;
op->Armi.Reg.reg = reg;
return op;
}
AMD64RMI* AMD64RMI_Mem ( AMD64AMode* am ) {
AMD64RMI* op = LibVEX_Alloc_inline(sizeof(AMD64RMI));
op->tag = Armi_Mem;
op->Armi.Mem.am = am;
return op;
}
static void ppAMD64RMI_wrk ( AMD64RMI* op, Bool lo32 ) {
switch (op->tag) {
case Armi_Imm:
vex_printf("$0x%x", op->Armi.Imm.imm32);
return;
case Armi_Reg:
if (lo32)
ppHRegAMD64_lo32(op->Armi.Reg.reg);
else
ppHRegAMD64(op->Armi.Reg.reg);
return;
case Armi_Mem:
ppAMD64AMode(op->Armi.Mem.am);
return;
default:
vpanic("ppAMD64RMI");
}
}
void ppAMD64RMI ( AMD64RMI* op ) {
ppAMD64RMI_wrk(op, False/*!lo32*/);
}
void ppAMD64RMI_lo32 ( AMD64RMI* op ) {
ppAMD64RMI_wrk(op, True/*lo32*/);
}
/* An AMD64RMI can only be used in a "read" context (what would it mean
to write or modify a literal?) and so we enumerate its registers
accordingly. */
static void addRegUsage_AMD64RMI ( HRegUsage* u, AMD64RMI* op ) {
switch (op->tag) {
case Armi_Imm:
return;
case Armi_Reg:
addHRegUse(u, HRmRead, op->Armi.Reg.reg);
return;
case Armi_Mem:
addRegUsage_AMD64AMode(u, op->Armi.Mem.am);
return;
default:
vpanic("addRegUsage_AMD64RMI");
}
}
static void mapRegs_AMD64RMI ( HRegRemap* m, AMD64RMI* op ) {
switch (op->tag) {
case Armi_Imm:
return;
case Armi_Reg:
op->Armi.Reg.reg = lookupHRegRemap(m, op->Armi.Reg.reg);
return;
case Armi_Mem:
mapRegs_AMD64AMode(m, op->Armi.Mem.am);
return;
default:
vpanic("mapRegs_AMD64RMI");
}
}
/* --------- Operand, which can be reg or immediate only. --------- */
AMD64RI* AMD64RI_Imm ( UInt imm32 ) {
AMD64RI* op = LibVEX_Alloc_inline(sizeof(AMD64RI));
op->tag = Ari_Imm;
op->Ari.Imm.imm32 = imm32;
return op;
}
AMD64RI* AMD64RI_Reg ( HReg reg ) {
AMD64RI* op = LibVEX_Alloc_inline(sizeof(AMD64RI));
op->tag = Ari_Reg;
op->Ari.Reg.reg = reg;
return op;
}
void ppAMD64RI ( AMD64RI* op ) {
switch (op->tag) {
case Ari_Imm:
vex_printf("$0x%x", op->Ari.Imm.imm32);
return;
case Ari_Reg:
ppHRegAMD64(op->Ari.Reg.reg);
return;
default:
vpanic("ppAMD64RI");
}
}
/* An AMD64RI can only be used in a "read" context (what would it mean
to write or modify a literal?) and so we enumerate its registers
accordingly. */
static void addRegUsage_AMD64RI ( HRegUsage* u, AMD64RI* op ) {
switch (op->tag) {
case Ari_Imm:
return;
case Ari_Reg:
addHRegUse(u, HRmRead, op->Ari.Reg.reg);
return;
default:
vpanic("addRegUsage_AMD64RI");
}
}
static void mapRegs_AMD64RI ( HRegRemap* m, AMD64RI* op ) {
switch (op->tag) {
case Ari_Imm:
return;
case Ari_Reg:
op->Ari.Reg.reg = lookupHRegRemap(m, op->Ari.Reg.reg);
return;
default:
vpanic("mapRegs_AMD64RI");
}
}
/* --------- Operand, which can be reg or memory only. --------- */
AMD64RM* AMD64RM_Reg ( HReg reg ) {
AMD64RM* op = LibVEX_Alloc_inline(sizeof(AMD64RM));
op->tag = Arm_Reg;
op->Arm.Reg.reg = reg;
return op;
}
AMD64RM* AMD64RM_Mem ( AMD64AMode* am ) {
AMD64RM* op = LibVEX_Alloc_inline(sizeof(AMD64RM));
op->tag = Arm_Mem;
op->Arm.Mem.am = am;
return op;
}
void ppAMD64RM ( AMD64RM* op ) {
switch (op->tag) {
case Arm_Mem:
ppAMD64AMode(op->Arm.Mem.am);
return;
case Arm_Reg:
ppHRegAMD64(op->Arm.Reg.reg);
return;
default:
vpanic("ppAMD64RM");
}
}
/* Because an AMD64RM can be both a source or destination operand, we
have to supply a mode -- pertaining to the operand as a whole --
indicating how it's being used. */
static void addRegUsage_AMD64RM ( HRegUsage* u, AMD64RM* op, HRegMode mode ) {
switch (op->tag) {
case Arm_Mem:
/* Memory is read, written or modified. So we just want to
know the regs read by the amode. */
addRegUsage_AMD64AMode(u, op->Arm.Mem.am);
return;
case Arm_Reg:
/* reg is read, written or modified. Add it in the
appropriate way. */
addHRegUse(u, mode, op->Arm.Reg.reg);
return;
default:
vpanic("addRegUsage_AMD64RM");
}
}
static void mapRegs_AMD64RM ( HRegRemap* m, AMD64RM* op )
{
switch (op->tag) {
case Arm_Mem:
mapRegs_AMD64AMode(m, op->Arm.Mem.am);
return;
case Arm_Reg:
op->Arm.Reg.reg = lookupHRegRemap(m, op->Arm.Reg.reg);
return;
default:
vpanic("mapRegs_AMD64RM");
}
}
/* --------- Instructions. --------- */
static const HChar* showAMD64ScalarSz ( Int sz ) {
switch (sz) {
case 2: return "w";
case 4: return "l";
case 8: return "q";
default: vpanic("showAMD64ScalarSz");
}
}
const HChar* showAMD64UnaryOp ( AMD64UnaryOp op ) {
switch (op) {
case Aun_NOT: return "not";
case Aun_NEG: return "neg";
default: vpanic("showAMD64UnaryOp");
}
}
const HChar* showAMD64AluOp ( AMD64AluOp op ) {
switch (op) {
case Aalu_MOV: return "mov";
case Aalu_CMP: return "cmp";
case Aalu_ADD: return "add";
case Aalu_SUB: return "sub";
case Aalu_ADC: return "adc";
case Aalu_SBB: return "sbb";
case Aalu_AND: return "and";
case Aalu_OR: return "or";
case Aalu_XOR: return "xor";
case Aalu_MUL: return "imul";
default: vpanic("showAMD64AluOp");
}
}
const HChar* showAMD64ShiftOp ( AMD64ShiftOp op ) {
switch (op) {
case Ash_SHL: return "shl";
case Ash_SHR: return "shr";
case Ash_SAR: return "sar";
default: vpanic("showAMD64ShiftOp");
}
}
const HChar* showA87FpOp ( A87FpOp op ) {
switch (op) {
case Afp_SCALE: return "scale";
case Afp_ATAN: return "atan";
case Afp_YL2X: return "yl2x";
case Afp_YL2XP1: return "yl2xp1";
case Afp_PREM: return "prem";
case Afp_PREM1: return "prem1";
case Afp_SQRT: return "sqrt";
case Afp_SIN: return "sin";
case Afp_COS: return "cos";
case Afp_TAN: return "tan";
case Afp_ROUND: return "round";
case Afp_2XM1: return "2xm1";
default: vpanic("showA87FpOp");
}
}
const HChar* showAMD64SseOp ( AMD64SseOp op ) {
switch (op) {
case Asse_MOV: return "movups";
case Asse_ADDF: return "add";
case Asse_SUBF: return "sub";
case Asse_MULF: return "mul";
case Asse_DIVF: return "div";
case Asse_MAXF: return "max";
case Asse_MINF: return "min";
case Asse_CMPEQF: return "cmpFeq";
case Asse_CMPLTF: return "cmpFlt";
case Asse_CMPLEF: return "cmpFle";
case Asse_CMPUNF: return "cmpFun";
case Asse_RCPF: return "rcp";
case Asse_RSQRTF: return "rsqrt";
case Asse_SQRTF: return "sqrt";
case Asse_AND: return "and";
case Asse_OR: return "or";
case Asse_XOR: return "xor";
case Asse_ANDN: return "andn";
case Asse_ADD8: return "paddb";
case Asse_ADD16: return "paddw";
case Asse_ADD32: return "paddd";
case Asse_ADD64: return "paddq";
case Asse_QADD8U: return "paddusb";
case Asse_QADD16U: return "paddusw";
case Asse_QADD8S: return "paddsb";
case Asse_QADD16S: return "paddsw";
case Asse_SUB8: return "psubb";
case Asse_SUB16: return "psubw";
case Asse_SUB32: return "psubd";
case Asse_SUB64: return "psubq";
case Asse_QSUB8U: return "psubusb";
case Asse_QSUB16U: return "psubusw";
case Asse_QSUB8S: return "psubsb";
case Asse_QSUB16S: return "psubsw";
case Asse_MUL16: return "pmullw";
case Asse_MULHI16U: return "pmulhuw";
case Asse_MULHI16S: return "pmulhw";
case Asse_AVG8U: return "pavgb";
case Asse_AVG16U: return "pavgw";
case Asse_MAX16S: return "pmaxw";
case Asse_MAX8U: return "pmaxub";
case Asse_MIN16S: return "pminw";
case Asse_MIN8U: return "pminub";
case Asse_CMPEQ8: return "pcmpeqb";
case Asse_CMPEQ16: return "pcmpeqw";
case Asse_CMPEQ32: return "pcmpeqd";
case Asse_CMPGT8S: return "pcmpgtb";
case Asse_CMPGT16S: return "pcmpgtw";
case Asse_CMPGT32S: return "pcmpgtd";
case Asse_SHL16: return "psllw";
case Asse_SHL32: return "pslld";
case Asse_SHL64: return "psllq";
case Asse_SHR16: return "psrlw";
case Asse_SHR32: return "psrld";
case Asse_SHR64: return "psrlq";
case Asse_SAR16: return "psraw";
case Asse_SAR32: return "psrad";
case Asse_PACKSSD: return "packssdw";
case Asse_PACKSSW: return "packsswb";
case Asse_PACKUSW: return "packuswb";
case Asse_UNPCKHB: return "punpckhb";
case Asse_UNPCKHW: return "punpckhw";
case Asse_UNPCKHD: return "punpckhd";
case Asse_UNPCKHQ: return "punpckhq";
case Asse_UNPCKLB: return "punpcklb";
case Asse_UNPCKLW: return "punpcklw";
case Asse_UNPCKLD: return "punpckld";
case Asse_UNPCKLQ: return "punpcklq";
default: vpanic("showAMD64SseOp");
}
}
AMD64Instr* AMD64Instr_Imm64 ( ULong imm64, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Imm64;
i->Ain.Imm64.imm64 = imm64;
i->Ain.Imm64.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_Alu64R ( AMD64AluOp op, AMD64RMI* src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Alu64R;
i->Ain.Alu64R.op = op;
i->Ain.Alu64R.src = src;
i->Ain.Alu64R.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_Alu64M ( AMD64AluOp op, AMD64RI* src, AMD64AMode* dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Alu64M;
i->Ain.Alu64M.op = op;
i->Ain.Alu64M.src = src;
i->Ain.Alu64M.dst = dst;
vassert(op != Aalu_MUL);
return i;
}
AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp op, UInt src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Sh64;
i->Ain.Sh64.op = op;
i->Ain.Sh64.src = src;
i->Ain.Sh64.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_Test64 ( UInt imm32, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Test64;
i->Ain.Test64.imm32 = imm32;
i->Ain.Test64.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Unary64;
i->Ain.Unary64.op = op;
i->Ain.Unary64.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_Lea64 ( AMD64AMode* am, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Lea64;
i->Ain.Lea64.am = am;
i->Ain.Lea64.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_Alu32R ( AMD64AluOp op, AMD64RMI* src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Alu32R;
i->Ain.Alu32R.op = op;
i->Ain.Alu32R.src = src;
i->Ain.Alu32R.dst = dst;
switch (op) {
case Aalu_ADD: case Aalu_SUB: case Aalu_CMP:
case Aalu_AND: case Aalu_OR: case Aalu_XOR: break;
default: vassert(0);
}
return i;
}
AMD64Instr* AMD64Instr_MulL ( Bool syned, AMD64RM* src ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_MulL;
i->Ain.MulL.syned = syned;
i->Ain.MulL.src = src;
return i;
}
AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* src ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Div;
i->Ain.Div.syned = syned;
i->Ain.Div.sz = sz;
i->Ain.Div.src = src;
vassert(sz == 4 || sz == 8);
return i;
}
AMD64Instr* AMD64Instr_Push( AMD64RMI* src ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Push;
i->Ain.Push.src = src;
return i;
}
AMD64Instr* AMD64Instr_Call ( AMD64CondCode cond, Addr64 target, Int regparms,
RetLoc rloc ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Call;
i->Ain.Call.cond = cond;
i->Ain.Call.target = target;
i->Ain.Call.regparms = regparms;
i->Ain.Call.rloc = rloc;
vassert(regparms >= 0 && regparms <= 6);
vassert(is_sane_RetLoc(rloc));
return i;
}
AMD64Instr* AMD64Instr_XDirect ( Addr64 dstGA, AMD64AMode* amRIP,
AMD64CondCode cond, Bool toFastEP ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_XDirect;
i->Ain.XDirect.dstGA = dstGA;
i->Ain.XDirect.amRIP = amRIP;
i->Ain.XDirect.cond = cond;
i->Ain.XDirect.toFastEP = toFastEP;
return i;
}
AMD64Instr* AMD64Instr_XIndir ( HReg dstGA, AMD64AMode* amRIP,
AMD64CondCode cond ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_XIndir;
i->Ain.XIndir.dstGA = dstGA;
i->Ain.XIndir.amRIP = amRIP;
i->Ain.XIndir.cond = cond;
return i;
}
AMD64Instr* AMD64Instr_XAssisted ( HReg dstGA, AMD64AMode* amRIP,
AMD64CondCode cond, IRJumpKind jk ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_XAssisted;
i->Ain.XAssisted.dstGA = dstGA;
i->Ain.XAssisted.amRIP = amRIP;
i->Ain.XAssisted.cond = cond;
i->Ain.XAssisted.jk = jk;
return i;
}
AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode cond, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_CMov64;
i->Ain.CMov64.cond = cond;
i->Ain.CMov64.src = src;
i->Ain.CMov64.dst = dst;
vassert(cond != Acc_ALWAYS);
return i;
}
AMD64Instr* AMD64Instr_CLoad ( AMD64CondCode cond, UChar szB,
AMD64AMode* addr, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_CLoad;
i->Ain.CLoad.cond = cond;
i->Ain.CLoad.szB = szB;
i->Ain.CLoad.addr = addr;
i->Ain.CLoad.dst = dst;
vassert(cond != Acc_ALWAYS && (szB == 4 || szB == 8));
return i;
}
AMD64Instr* AMD64Instr_CStore ( AMD64CondCode cond, UChar szB,
HReg src, AMD64AMode* addr ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_CStore;
i->Ain.CStore.cond = cond;
i->Ain.CStore.szB = szB;
i->Ain.CStore.src = src;
i->Ain.CStore.addr = addr;
vassert(cond != Acc_ALWAYS && (szB == 4 || szB == 8));
return i;
}
AMD64Instr* AMD64Instr_MovxLQ ( Bool syned, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_MovxLQ;
i->Ain.MovxLQ.syned = syned;
i->Ain.MovxLQ.src = src;
i->Ain.MovxLQ.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned,
AMD64AMode* src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_LoadEX;
i->Ain.LoadEX.szSmall = szSmall;
i->Ain.LoadEX.syned = syned;
i->Ain.LoadEX.src = src;
i->Ain.LoadEX.dst = dst;
vassert(szSmall == 1 || szSmall == 2 || szSmall == 4);
return i;
}
AMD64Instr* AMD64Instr_Store ( UChar sz, HReg src, AMD64AMode* dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Store;
i->Ain.Store.sz = sz;
i->Ain.Store.src = src;
i->Ain.Store.dst = dst;
vassert(sz == 1 || sz == 2 || sz == 4);
return i;
}
AMD64Instr* AMD64Instr_Set64 ( AMD64CondCode cond, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Set64;
i->Ain.Set64.cond = cond;
i->Ain.Set64.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_Bsfr64 ( Bool isFwds, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Bsfr64;
i->Ain.Bsfr64.isFwds = isFwds;
i->Ain.Bsfr64.src = src;
i->Ain.Bsfr64.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_MFence ( void ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_MFence;
return i;
}
AMD64Instr* AMD64Instr_ACAS ( AMD64AMode* addr, UChar sz ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_ACAS;
i->Ain.ACAS.addr = addr;
i->Ain.ACAS.sz = sz;
vassert(sz == 8 || sz == 4 || sz == 2 || sz == 1);
return i;
}
AMD64Instr* AMD64Instr_DACAS ( AMD64AMode* addr, UChar sz ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_DACAS;
i->Ain.DACAS.addr = addr;
i->Ain.DACAS.sz = sz;
vassert(sz == 8 || sz == 4);
return i;
}
AMD64Instr* AMD64Instr_A87Free ( Int nregs )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_A87Free;
i->Ain.A87Free.nregs = nregs;
vassert(nregs >= 1 && nregs <= 7);
return i;
}
AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_A87PushPop;
i->Ain.A87PushPop.addr = addr;
i->Ain.A87PushPop.isPush = isPush;
i->Ain.A87PushPop.szB = szB;
vassert(szB == 8 || szB == 4);
return i;
}
AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_A87FpOp;
i->Ain.A87FpOp.op = op;
return i;
}
AMD64Instr* AMD64Instr_A87LdCW ( AMD64AMode* addr )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_A87LdCW;
i->Ain.A87LdCW.addr = addr;
return i;
}
AMD64Instr* AMD64Instr_A87StSW ( AMD64AMode* addr )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_A87StSW;
i->Ain.A87StSW.addr = addr;
return i;
}
AMD64Instr* AMD64Instr_LdMXCSR ( AMD64AMode* addr ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_LdMXCSR;
i->Ain.LdMXCSR.addr = addr;
return i;
}
AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseUComIS;
i->Ain.SseUComIS.sz = toUChar(sz);
i->Ain.SseUComIS.srcL = srcL;
i->Ain.SseUComIS.srcR = srcR;
i->Ain.SseUComIS.dst = dst;
vassert(sz == 4 || sz == 8);
return i;
}
AMD64Instr* AMD64Instr_SseSI2SF ( Int szS, Int szD, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseSI2SF;
i->Ain.SseSI2SF.szS = toUChar(szS);
i->Ain.SseSI2SF.szD = toUChar(szD);
i->Ain.SseSI2SF.src = src;
i->Ain.SseSI2SF.dst = dst;
vassert(szS == 4 || szS == 8);
vassert(szD == 4 || szD == 8);
return i;
}
AMD64Instr* AMD64Instr_SseSF2SI ( Int szS, Int szD, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseSF2SI;
i->Ain.SseSF2SI.szS = toUChar(szS);
i->Ain.SseSF2SI.szD = toUChar(szD);
i->Ain.SseSF2SI.src = src;
i->Ain.SseSF2SI.dst = dst;
vassert(szS == 4 || szS == 8);
vassert(szD == 4 || szD == 8);
return i;
}
AMD64Instr* AMD64Instr_SseSDSS ( Bool from64, HReg src, HReg dst )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseSDSS;
i->Ain.SseSDSS.from64 = from64;
i->Ain.SseSDSS.src = src;
i->Ain.SseSDSS.dst = dst;
return i;
}
AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz,
HReg reg, AMD64AMode* addr ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseLdSt;
i->Ain.SseLdSt.isLoad = isLoad;
i->Ain.SseLdSt.sz = toUChar(sz);
i->Ain.SseLdSt.reg = reg;
i->Ain.SseLdSt.addr = addr;
vassert(sz == 4 || sz == 8 || sz == 16);
return i;
}
AMD64Instr* AMD64Instr_SseCStore ( AMD64CondCode cond,
HReg src, AMD64AMode* addr )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseCStore;
i->Ain.SseCStore.cond = cond;
i->Ain.SseCStore.src = src;
i->Ain.SseCStore.addr = addr;
vassert(cond != Acc_ALWAYS);
return i;
}
AMD64Instr* AMD64Instr_SseCLoad ( AMD64CondCode cond,
AMD64AMode* addr, HReg dst )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseCLoad;
i->Ain.SseCLoad.cond = cond;
i->Ain.SseCLoad.addr = addr;
i->Ain.SseCLoad.dst = dst;
vassert(cond != Acc_ALWAYS);
return i;
}
AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg reg, AMD64AMode* addr )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseLdzLO;
i->Ain.SseLdzLO.sz = sz;
i->Ain.SseLdzLO.reg = reg;
i->Ain.SseLdzLO.addr = addr;
vassert(sz == 4 || sz == 8);
return i;
}
AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp op, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Sse32Fx4;
i->Ain.Sse32Fx4.op = op;
i->Ain.Sse32Fx4.src = src;
i->Ain.Sse32Fx4.dst = dst;
vassert(op != Asse_MOV);
return i;
}
AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp op, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Sse32FLo;
i->Ain.Sse32FLo.op = op;
i->Ain.Sse32FLo.src = src;
i->Ain.Sse32FLo.dst = dst;
vassert(op != Asse_MOV);
return i;
}
AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp op, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Sse64Fx2;
i->Ain.Sse64Fx2.op = op;
i->Ain.Sse64Fx2.src = src;
i->Ain.Sse64Fx2.dst = dst;
vassert(op != Asse_MOV);
return i;
}
AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp op, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_Sse64FLo;
i->Ain.Sse64FLo.op = op;
i->Ain.Sse64FLo.src = src;
i->Ain.Sse64FLo.dst = dst;
vassert(op != Asse_MOV);
return i;
}
AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp op, HReg re, HReg rg ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseReRg;
i->Ain.SseReRg.op = op;
i->Ain.SseReRg.src = re;
i->Ain.SseReRg.dst = rg;
return i;
}
AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode cond, HReg src, HReg dst ) {
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
i->tag = Ain_SseCMov;
i->Ain.SseCMov.cond = cond;
i->Ain.SseCMov.src = src;
i->Ain.SseCMov.dst = dst;
vassert(cond != Acc_ALWAYS);
return i;
}
AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ) {