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omap2.c
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/*
* TI OMAP processors emulation.
*
* Copyright (C) 2007-2008 Nokia Corporation
* Written by Andrzej Zaborowski <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "hw/boards.h"
#include "hw/hw.h"
#include "hw/arm/arm.h"
#include "hw/arm/omap.h"
#include "sysemu/sysemu.h"
#include "qemu/timer.h"
#include "chardev/char-fe.h"
#include "hw/block/flash.h"
#include "hw/arm/soc_dma.h"
#include "hw/sysbus.h"
#include "audio/audio.h"
/* Enhanced Audio Controller (CODEC only) */
struct omap_eac_s {
qemu_irq irq;
MemoryRegion iomem;
uint16_t sysconfig;
uint8_t config[4];
uint8_t control;
uint8_t address;
uint16_t data;
uint8_t vtol;
uint8_t vtsl;
uint16_t mixer;
uint16_t gain[4];
uint8_t att;
uint16_t max[7];
struct {
qemu_irq txdrq;
qemu_irq rxdrq;
uint32_t (*txrx)(void *opaque, uint32_t, int);
void *opaque;
#define EAC_BUF_LEN 1024
uint32_t rxbuf[EAC_BUF_LEN];
int rxoff;
int rxlen;
int rxavail;
uint32_t txbuf[EAC_BUF_LEN];
int txlen;
int txavail;
int enable;
int rate;
uint16_t config[4];
/* These need to be moved to the actual codec */
QEMUSoundCard card;
SWVoiceIn *in_voice;
SWVoiceOut *out_voice;
int hw_enable;
} codec;
struct {
uint8_t control;
uint16_t config;
} modem, bt;
};
static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
{
qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
}
static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
{
qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
((s->codec.config[1] >> 12) & 1)); /* DMAREN */
}
static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
{
qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
}
static inline void omap_eac_in_refill(struct omap_eac_s *s)
{
int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
int recv = 1;
uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
left -= leftwrap;
start = 0;
while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
leftwrap)) > 0) { /* Be defensive */
start += recv;
leftwrap -= recv;
}
if (recv <= 0)
s->codec.rxavail = 0;
else
s->codec.rxavail -= start >> 2;
s->codec.rxlen += start >> 2;
if (recv > 0 && left > 0) {
start = 0;
while (left && (recv = AUD_read(s->codec.in_voice,
(uint8_t *) s->codec.rxbuf + start,
left)) > 0) { /* Be defensive */
start += recv;
left -= recv;
}
if (recv <= 0)
s->codec.rxavail = 0;
else
s->codec.rxavail -= start >> 2;
s->codec.rxlen += start >> 2;
}
}
static inline void omap_eac_out_empty(struct omap_eac_s *s)
{
int left = s->codec.txlen << 2;
int start = 0;
int sent = 1;
while (left && (sent = AUD_write(s->codec.out_voice,
(uint8_t *) s->codec.txbuf + start,
left)) > 0) { /* Be defensive */
start += sent;
left -= sent;
}
if (!sent) {
s->codec.txavail = 0;
omap_eac_out_dmarequest_update(s);
}
if (start)
s->codec.txlen = 0;
}
static void omap_eac_in_cb(void *opaque, int avail_b)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
s->codec.rxavail = avail_b >> 2;
omap_eac_in_refill(s);
/* TODO: possibly discard current buffer if overrun */
omap_eac_in_dmarequest_update(s);
}
static void omap_eac_out_cb(void *opaque, int free_b)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
s->codec.txavail = free_b >> 2;
if (s->codec.txlen)
omap_eac_out_empty(s);
else
omap_eac_out_dmarequest_update(s);
}
static void omap_eac_enable_update(struct omap_eac_s *s)
{
s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
(s->codec.config[1] & 2) && /* AUDEN */
s->codec.hw_enable;
}
static const int omap_eac_fsint[4] = {
8000,
11025,
22050,
44100,
};
static const int omap_eac_fsint2[8] = {
8000,
11025,
22050,
44100,
48000,
0, 0, 0,
};
static const int omap_eac_fsint3[16] = {
8000,
11025,
16000,
22050,
24000,
32000,
44100,
48000,
0, 0, 0, 0, 0, 0, 0, 0,
};
static void omap_eac_rate_update(struct omap_eac_s *s)
{
int fsint[3];
fsint[2] = (s->codec.config[3] >> 9) & 0xf;
fsint[1] = (s->codec.config[2] >> 0) & 0x7;
fsint[0] = (s->codec.config[0] >> 6) & 0x3;
if (fsint[2] < 0xf)
s->codec.rate = omap_eac_fsint3[fsint[2]];
else if (fsint[1] < 0x7)
s->codec.rate = omap_eac_fsint2[fsint[1]];
else
s->codec.rate = omap_eac_fsint[fsint[0]];
}
static void omap_eac_volume_update(struct omap_eac_s *s)
{
/* TODO */
}
static void omap_eac_format_update(struct omap_eac_s *s)
{
struct audsettings fmt;
/* The hardware buffers at most one sample */
if (s->codec.rxlen)
s->codec.rxlen = 1;
if (s->codec.in_voice) {
AUD_set_active_in(s->codec.in_voice, 0);
AUD_close_in(&s->codec.card, s->codec.in_voice);
s->codec.in_voice = NULL;
}
if (s->codec.out_voice) {
omap_eac_out_empty(s);
AUD_set_active_out(s->codec.out_voice, 0);
AUD_close_out(&s->codec.card, s->codec.out_voice);
s->codec.out_voice = NULL;
s->codec.txavail = 0;
}
/* Discard what couldn't be written */
s->codec.txlen = 0;
omap_eac_enable_update(s);
if (!s->codec.enable)
return;
omap_eac_rate_update(s);
fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
fmt.freq = s->codec.rate;
/* TODO: signedness possibly depends on the CODEC hardware - or
* does I2S specify it? */
/* All register writes are 16 bits so we we store 16-bit samples
* in the buffers regardless of AGCFR[B8_16] value. */
fmt.fmt = AUD_FMT_U16;
s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
"eac.codec.in", s, omap_eac_in_cb, &fmt);
s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
"eac.codec.out", s, omap_eac_out_cb, &fmt);
omap_eac_volume_update(s);
AUD_set_active_in(s->codec.in_voice, 1);
AUD_set_active_out(s->codec.out_voice, 1);
}
static void omap_eac_reset(struct omap_eac_s *s)
{
s->sysconfig = 0;
s->config[0] = 0x0c;
s->config[1] = 0x09;
s->config[2] = 0xab;
s->config[3] = 0x03;
s->control = 0x00;
s->address = 0x00;
s->data = 0x0000;
s->vtol = 0x00;
s->vtsl = 0x00;
s->mixer = 0x0000;
s->gain[0] = 0xe7e7;
s->gain[1] = 0x6767;
s->gain[2] = 0x6767;
s->gain[3] = 0x6767;
s->att = 0xce;
s->max[0] = 0;
s->max[1] = 0;
s->max[2] = 0;
s->max[3] = 0;
s->max[4] = 0;
s->max[5] = 0;
s->max[6] = 0;
s->modem.control = 0x00;
s->modem.config = 0x0000;
s->bt.control = 0x00;
s->bt.config = 0x0000;
s->codec.config[0] = 0x0649;
s->codec.config[1] = 0x0000;
s->codec.config[2] = 0x0007;
s->codec.config[3] = 0x1ffc;
s->codec.rxoff = 0;
s->codec.rxlen = 0;
s->codec.txlen = 0;
s->codec.rxavail = 0;
s->codec.txavail = 0;
omap_eac_format_update(s);
omap_eac_interrupt_update(s);
}
static uint64_t omap_eac_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
uint32_t ret;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
}
switch (addr) {
case 0x000: /* CPCFR1 */
return s->config[0];
case 0x004: /* CPCFR2 */
return s->config[1];
case 0x008: /* CPCFR3 */
return s->config[2];
case 0x00c: /* CPCFR4 */
return s->config[3];
case 0x010: /* CPTCTL */
return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
((s->codec.txlen < s->codec.txavail) << 5);
case 0x014: /* CPTTADR */
return s->address;
case 0x018: /* CPTDATL */
return s->data & 0xff;
case 0x01c: /* CPTDATH */
return s->data >> 8;
case 0x020: /* CPTVSLL */
return s->vtol;
case 0x024: /* CPTVSLH */
return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
case 0x040: /* MPCTR */
return s->modem.control;
case 0x044: /* MPMCCFR */
return s->modem.config;
case 0x060: /* BPCTR */
return s->bt.control;
case 0x064: /* BPMCCFR */
return s->bt.config;
case 0x080: /* AMSCFR */
return s->mixer;
case 0x084: /* AMVCTR */
return s->gain[0];
case 0x088: /* AM1VCTR */
return s->gain[1];
case 0x08c: /* AM2VCTR */
return s->gain[2];
case 0x090: /* AM3VCTR */
return s->gain[3];
case 0x094: /* ASTCTR */
return s->att;
case 0x098: /* APD1LCR */
return s->max[0];
case 0x09c: /* APD1RCR */
return s->max[1];
case 0x0a0: /* APD2LCR */
return s->max[2];
case 0x0a4: /* APD2RCR */
return s->max[3];
case 0x0a8: /* APD3LCR */
return s->max[4];
case 0x0ac: /* APD3RCR */
return s->max[5];
case 0x0b0: /* APD4R */
return s->max[6];
case 0x0b4: /* ADWR */
/* This should be write-only? Docs list it as read-only. */
return 0x0000;
case 0x0b8: /* ADRDR */
if (likely(s->codec.rxlen > 1)) {
ret = s->codec.rxbuf[s->codec.rxoff ++];
s->codec.rxlen --;
s->codec.rxoff &= EAC_BUF_LEN - 1;
return ret;
} else if (s->codec.rxlen) {
ret = s->codec.rxbuf[s->codec.rxoff ++];
s->codec.rxlen --;
s->codec.rxoff &= EAC_BUF_LEN - 1;
if (s->codec.rxavail)
omap_eac_in_refill(s);
omap_eac_in_dmarequest_update(s);
return ret;
}
return 0x0000;
case 0x0bc: /* AGCFR */
return s->codec.config[0];
case 0x0c0: /* AGCTR */
return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
case 0x0c4: /* AGCFR2 */
return s->codec.config[2];
case 0x0c8: /* AGCFR3 */
return s->codec.config[3];
case 0x0cc: /* MBPDMACTR */
case 0x0d0: /* MPDDMARR */
case 0x0d8: /* MPUDMARR */
case 0x0e4: /* BPDDMARR */
case 0x0ec: /* BPUDMARR */
return 0x0000;
case 0x100: /* VERSION_NUMBER */
return 0x0010;
case 0x104: /* SYSCONFIG */
return s->sysconfig;
case 0x108: /* SYSSTATUS */
return 1 | 0xe; /* RESETDONE | stuff */
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_eac_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
case 0x098: /* APD1LCR */
case 0x09c: /* APD1RCR */
case 0x0a0: /* APD2LCR */
case 0x0a4: /* APD2RCR */
case 0x0a8: /* APD3LCR */
case 0x0ac: /* APD3RCR */
case 0x0b0: /* APD4R */
case 0x0b8: /* ADRDR */
case 0x0d0: /* MPDDMARR */
case 0x0d8: /* MPUDMARR */
case 0x0e4: /* BPDDMARR */
case 0x0ec: /* BPUDMARR */
case 0x100: /* VERSION_NUMBER */
case 0x108: /* SYSSTATUS */
OMAP_RO_REG(addr);
return;
case 0x000: /* CPCFR1 */
s->config[0] = value & 0xff;
omap_eac_format_update(s);
break;
case 0x004: /* CPCFR2 */
s->config[1] = value & 0xff;
omap_eac_format_update(s);
break;
case 0x008: /* CPCFR3 */
s->config[2] = value & 0xff;
omap_eac_format_update(s);
break;
case 0x00c: /* CPCFR4 */
s->config[3] = value & 0xff;
omap_eac_format_update(s);
break;
case 0x010: /* CPTCTL */
/* Assuming TXF and TXE bits are read-only... */
s->control = value & 0x5f;
omap_eac_interrupt_update(s);
break;
case 0x014: /* CPTTADR */
s->address = value & 0xff;
break;
case 0x018: /* CPTDATL */
s->data &= 0xff00;
s->data |= value & 0xff;
break;
case 0x01c: /* CPTDATH */
s->data &= 0x00ff;
s->data |= value << 8;
break;
case 0x020: /* CPTVSLL */
s->vtol = value & 0xf8;
break;
case 0x024: /* CPTVSLH */
s->vtsl = value & 0x9f;
break;
case 0x040: /* MPCTR */
s->modem.control = value & 0x8f;
break;
case 0x044: /* MPMCCFR */
s->modem.config = value & 0x7fff;
break;
case 0x060: /* BPCTR */
s->bt.control = value & 0x8f;
break;
case 0x064: /* BPMCCFR */
s->bt.config = value & 0x7fff;
break;
case 0x080: /* AMSCFR */
s->mixer = value & 0x0fff;
break;
case 0x084: /* AMVCTR */
s->gain[0] = value & 0xffff;
break;
case 0x088: /* AM1VCTR */
s->gain[1] = value & 0xff7f;
break;
case 0x08c: /* AM2VCTR */
s->gain[2] = value & 0xff7f;
break;
case 0x090: /* AM3VCTR */
s->gain[3] = value & 0xff7f;
break;
case 0x094: /* ASTCTR */
s->att = value & 0xff;
break;
case 0x0b4: /* ADWR */
s->codec.txbuf[s->codec.txlen ++] = value;
if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
s->codec.txlen == s->codec.txavail)) {
if (s->codec.txavail)
omap_eac_out_empty(s);
/* Discard what couldn't be written */
s->codec.txlen = 0;
}
break;
case 0x0bc: /* AGCFR */
s->codec.config[0] = value & 0x07ff;
omap_eac_format_update(s);
break;
case 0x0c0: /* AGCTR */
s->codec.config[1] = value & 0x780f;
omap_eac_format_update(s);
break;
case 0x0c4: /* AGCFR2 */
s->codec.config[2] = value & 0x003f;
omap_eac_format_update(s);
break;
case 0x0c8: /* AGCFR3 */
s->codec.config[3] = value & 0xffff;
omap_eac_format_update(s);
break;
case 0x0cc: /* MBPDMACTR */
case 0x0d4: /* MPDDMAWR */
case 0x0e0: /* MPUDMAWR */
case 0x0e8: /* BPDDMAWR */
case 0x0f0: /* BPUDMAWR */
break;
case 0x104: /* SYSCONFIG */
if (value & (1 << 1)) /* SOFTRESET */
omap_eac_reset(s);
s->sysconfig = value & 0x31d;
break;
default:
OMAP_BAD_REG(addr);
return;
}
}
static const MemoryRegionOps omap_eac_ops = {
.read = omap_eac_read,
.write = omap_eac_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
struct omap_eac_s *s = g_new0(struct omap_eac_s, 1);
s->irq = irq;
s->codec.rxdrq = *drq ++;
s->codec.txdrq = *drq;
omap_eac_reset(s);
AUD_register_card("OMAP EAC", &s->codec.card);
memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
return s;
}
/* STI/XTI (emulation interface) console - reverse engineered only */
struct omap_sti_s {
qemu_irq irq;
MemoryRegion iomem;
MemoryRegion iomem_fifo;
CharBackend chr;
uint32_t sysconfig;
uint32_t systest;
uint32_t irqst;
uint32_t irqen;
uint32_t clkcontrol;
uint32_t serial_config;
};
#define STI_TRACE_CONSOLE_CHANNEL 239
#define STI_TRACE_CONTROL_CHANNEL 253
static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
{
qemu_set_irq(s->irq, s->irqst & s->irqen);
}
static void omap_sti_reset(struct omap_sti_s *s)
{
s->sysconfig = 0;
s->irqst = 0;
s->irqen = 0;
s->clkcontrol = 0;
s->serial_config = 0;
omap_sti_interrupt_update(s);
}
static uint64_t omap_sti_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
}
switch (addr) {
case 0x00: /* STI_REVISION */
return 0x10;
case 0x10: /* STI_SYSCONFIG */
return s->sysconfig;
case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
return 0x00;
case 0x18: /* STI_IRQSTATUS */
return s->irqst;
case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
return s->irqen;
case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
case 0x28: /* STI_RX_DR / XTI_RXDATA */
/* TODO */
return 0;
case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
return s->clkcontrol;
case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
return s->serial_config;
}
OMAP_BAD_REG(addr);
return 0;
}
static void omap_sti_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
case 0x00: /* STI_REVISION */
case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
OMAP_RO_REG(addr);
return;
case 0x10: /* STI_SYSCONFIG */
if (value & (1 << 1)) /* SOFTRESET */
omap_sti_reset(s);
s->sysconfig = value & 0xfe;
break;
case 0x18: /* STI_IRQSTATUS */
s->irqst &= ~value;
omap_sti_interrupt_update(s);
break;
case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
s->irqen = value & 0xffff;
omap_sti_interrupt_update(s);
break;
case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
s->clkcontrol = value & 0xff;
break;
case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
s->serial_config = value & 0xff;
break;
case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
case 0x28: /* STI_RX_DR / XTI_RXDATA */
/* TODO */
return;
default:
OMAP_BAD_REG(addr);
return;
}
}
static const MemoryRegionOps omap_sti_ops = {
.read = omap_sti_read,
.write = omap_sti_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
unsigned size)
{
OMAP_BAD_REG(addr);
return 0;
}
static void omap_sti_fifo_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
int ch = addr >> 6;
uint8_t byte = value;
if (size != 1) {
omap_badwidth_write8(opaque, addr, size);
return;
}
if (ch == STI_TRACE_CONTROL_CHANNEL) {
/* Flush channel <i>value</i>. */
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\r", 1);
} else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
if (value == 0xc0 || value == 0xc3) {
/* Open channel <i>ch</i>. */
} else if (value == 0x00) {
qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\n", 1);
} else {
qemu_chr_fe_write_all(&s->chr, &byte, 1);
}
}
}
static const MemoryRegionOps omap_sti_fifo_ops = {
.read = omap_sti_fifo_read,
.write = omap_sti_fifo_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
hwaddr channel_base, qemu_irq irq, omap_clk clk,
Chardev *chr)
{
struct omap_sti_s *s = g_new0(struct omap_sti_s, 1);
s->irq = irq;
omap_sti_reset(s);
qemu_chr_fe_init(&s->chr, chr ?: qemu_chr_new("null", "null"),
&error_abort);
memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
"omap.sti.fifo", 0x10000);
memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
return s;
}
/* L4 Interconnect */
#define L4TA(n) (n)
#define L4TAO(n) ((n) + 39)
static const struct omap_l4_region_s omap_l4_region[125] = {
[ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
[ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
[ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
[ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
[ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
[ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
[ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
[ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
[ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
[ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
[ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
[ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
[ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
[ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
[ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
[ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
[ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
[ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
[ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
[ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
[ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
[ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
[ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
[ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
[ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
[ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
[ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
[ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
[ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
[ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
[ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
[ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
[ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
[ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
[ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
[ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
[ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
[ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
[ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
[ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
[ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
[ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
[ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
[ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
[ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
[ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
[ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
[ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
[ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
[ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
[ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
[ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
[ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
[ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
[ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
[ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
[ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
[ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
[ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
[ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
[ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
[ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
[ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
[ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
[ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
[ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
[ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
[ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
[ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
[ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
[ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
[ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
[ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
[ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
[ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
[ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
[ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
[ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
[ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
[ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
[ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
[ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
[ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
[ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
[ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
[ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
[ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
[ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
[ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
[ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
[ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
[ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
[ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
[ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
[ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
[ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
[ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
[ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
[ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
[ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
[100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
[101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
[102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
[103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
[104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
[105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
[106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
[107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
[108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
[109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
[110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
[111] = { 0xa0000, 0x1000, 32 }, /* RNG */
[112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
[113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
[114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
[115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
[116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
[117] = { 0xa6000, 0x1000, 32 }, /* AES */
[118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
[119] = { 0xa8000, 0x2000, 32 }, /* PKA */
[120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
[121] = { 0xb0000, 0x1000, 32 }, /* MG */
[122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
[123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
[124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
};
static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
{ 0, 0, 3, 2 }, /* L4IA initiatior agent */
{ L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
{ L4TAO(2), 5, 2, 1 }, /* 32K timer */
{ L4TAO(3), 7, 3, 2 }, /* PRCM */
{ L4TA(1), 10, 2, 1 }, /* BCM */
{ L4TA(2), 12, 2, 1 }, /* Test JTAG */
{ L4TA(3), 14, 6, 3 }, /* Quad GPIO */
{ L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
{ L4TA(7), 24, 2, 1 }, /* GP timer 1 */
{ L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
{ L4TA(10), 28, 5, 4 }, /* Display subsystem */
{ L4TA(11), 33, 5, 4 }, /* Camera subsystem */
{ L4TA(12), 38, 2, 1 }, /* sDMA */
{ L4TA(13), 40, 5, 4 }, /* SSI */
{ L4TAO(4), 45, 2, 1 }, /* USB */
{ L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
{ L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
{ L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
{ L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
{ L4TA(18), 55, 2, 1 }, /* XTI */
{ L4TA(19), 57, 2, 1 }, /* UART1 */
{ L4TA(20), 59, 2, 1 }, /* UART2 */
{ L4TA(21), 61, 2, 1 }, /* UART3 */
{ L4TAO(5), 63, 2, 1 }, /* I2C1 */
{ L4TAO(6), 65, 2, 1 }, /* I2C2 */
{ L4TAO(7), 67, 2, 1 }, /* McBSP1 */
{ L4TAO(8), 69, 2, 1 }, /* McBSP2 */
{ L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
{ L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
{ L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
{ L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
{ L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
{ L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
{ L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
{ L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
{ L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
{ L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
{ L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
{ L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
{ L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
{ L4TA(32), 97, 2, 1 }, /* EAC */
{ L4TA(33), 99, 2, 1 }, /* FAC */
{ L4TA(34), 101, 2, 1 }, /* IPC */
{ L4TA(35), 103, 2, 1 }, /* SPI1 */
{ L4TA(36), 105, 2, 1 }, /* SPI2 */
{ L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
{ L4TAO(10), 109, 2, 1 },
{ L4TAO(11), 111, 2, 1 }, /* RNG */
{ L4TAO(12), 113, 2, 1 }, /* DES3DES */
{ L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
{ L4TA(37), 117, 2, 1 }, /* AES */
{ L4TA(38), 119, 2, 1 }, /* PKA */