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test-i386.c
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/*
* x86 CPU test
*
* Copyright (c) 2003 Fabrice Bellard
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#define _GNU_SOURCE
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
#include <signal.h>
#include <setjmp.h>
#include <errno.h>
#include <sys/ucontext.h>
#include <sys/mman.h>
#if !defined(__x86_64__)
#define TEST_VM86
#define TEST_SEGS
#endif
//#define LINUX_VM86_IOPL_FIX
//#define TEST_P4_FLAGS
#if defined(__x86_64__)
#define TEST_SSE
#define TEST_CMOV 1
#define TEST_FCOMI 1
#else
//#define TEST_SSE
#define TEST_CMOV 0
#define TEST_FCOMI 0
#endif
#if defined(__x86_64__)
#define FMT64X "%016lx"
#define FMTLX "%016lx"
#define X86_64_ONLY(x) x
#else
#define FMT64X "%016" PRIx64
#define FMTLX "%08lx"
#define X86_64_ONLY(x)
#endif
#ifdef TEST_VM86
#include <asm/vm86.h>
#endif
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s) tostring(s)
#define tostring(s) #s
#define CC_C 0x0001
#define CC_P 0x0004
#define CC_A 0x0010
#define CC_Z 0x0040
#define CC_S 0x0080
#define CC_O 0x0800
#define __init_call __attribute__ ((unused,__section__ ("initcall")))
#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
#if defined(__x86_64__)
static inline long i2l(long v)
{
return v | ((v ^ 0xabcd) << 32);
}
#else
static inline long i2l(long v)
{
return v;
}
#endif
#define OP add
#include "test-i386.h"
#define OP sub
#include "test-i386.h"
#define OP xor
#include "test-i386.h"
#define OP and
#include "test-i386.h"
#define OP or
#include "test-i386.h"
#define OP cmp
#include "test-i386.h"
#define OP adc
#define OP_CC
#include "test-i386.h"
#define OP sbb
#define OP_CC
#include "test-i386.h"
#define OP inc
#define OP_CC
#define OP1
#include "test-i386.h"
#define OP dec
#define OP_CC
#define OP1
#include "test-i386.h"
#define OP neg
#define OP_CC
#define OP1
#include "test-i386.h"
#define OP not
#define OP_CC
#define OP1
#include "test-i386.h"
#undef CC_MASK
#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O)
#define OP shl
#include "test-i386-shift.h"
#define OP shr
#include "test-i386-shift.h"
#define OP sar
#include "test-i386-shift.h"
#define OP rol
#include "test-i386-shift.h"
#define OP ror
#include "test-i386-shift.h"
#define OP rcr
#define OP_CC
#include "test-i386-shift.h"
#define OP rcl
#define OP_CC
#include "test-i386-shift.h"
#define OP shld
#define OP_SHIFTD
#define OP_NOBYTE
#include "test-i386-shift.h"
#define OP shrd
#define OP_SHIFTD
#define OP_NOBYTE
#include "test-i386-shift.h"
/* XXX: should be more precise ? */
#undef CC_MASK
#define CC_MASK (CC_C)
#define OP bt
#define OP_NOBYTE
#include "test-i386-shift.h"
#define OP bts
#define OP_NOBYTE
#include "test-i386-shift.h"
#define OP btr
#define OP_NOBYTE
#include "test-i386-shift.h"
#define OP btc
#define OP_NOBYTE
#include "test-i386-shift.h"
/* lea test (modrm support) */
#define TEST_LEAQ(STR)\
{\
asm("lea " STR ", %0"\
: "=r" (res)\
: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
printf("lea %s = " FMTLX "\n", STR, res);\
}
#define TEST_LEA(STR)\
{\
asm("lea " STR ", %0"\
: "=r" (res)\
: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
printf("lea %s = " FMTLX "\n", STR, res);\
}
#define TEST_LEA16(STR)\
{\
asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
: "=wq" (res)\
: "a" (eax), "b" (ebx), "c" (ecx), "d" (edx), "S" (esi), "D" (edi));\
printf("lea %s = %08lx\n", STR, res);\
}
void test_lea(void)
{
long eax, ebx, ecx, edx, esi, edi, res;
eax = i2l(0x0001);
ebx = i2l(0x0002);
ecx = i2l(0x0004);
edx = i2l(0x0008);
esi = i2l(0x0010);
edi = i2l(0x0020);
TEST_LEA("0x4000");
TEST_LEA("(%%eax)");
TEST_LEA("(%%ebx)");
TEST_LEA("(%%ecx)");
TEST_LEA("(%%edx)");
TEST_LEA("(%%esi)");
TEST_LEA("(%%edi)");
TEST_LEA("0x40(%%eax)");
TEST_LEA("0x40(%%ebx)");
TEST_LEA("0x40(%%ecx)");
TEST_LEA("0x40(%%edx)");
TEST_LEA("0x40(%%esi)");
TEST_LEA("0x40(%%edi)");
TEST_LEA("0x4000(%%eax)");
TEST_LEA("0x4000(%%ebx)");
TEST_LEA("0x4000(%%ecx)");
TEST_LEA("0x4000(%%edx)");
TEST_LEA("0x4000(%%esi)");
TEST_LEA("0x4000(%%edi)");
TEST_LEA("(%%eax, %%ecx)");
TEST_LEA("(%%ebx, %%edx)");
TEST_LEA("(%%ecx, %%ecx)");
TEST_LEA("(%%edx, %%ecx)");
TEST_LEA("(%%esi, %%ecx)");
TEST_LEA("(%%edi, %%ecx)");
TEST_LEA("0x40(%%eax, %%ecx)");
TEST_LEA("0x4000(%%ebx, %%edx)");
TEST_LEA("(%%ecx, %%ecx, 2)");
TEST_LEA("(%%edx, %%ecx, 4)");
TEST_LEA("(%%esi, %%ecx, 8)");
TEST_LEA("(,%%eax, 2)");
TEST_LEA("(,%%ebx, 4)");
TEST_LEA("(,%%ecx, 8)");
TEST_LEA("0x40(,%%eax, 2)");
TEST_LEA("0x40(,%%ebx, 4)");
TEST_LEA("0x40(,%%ecx, 8)");
TEST_LEA("-10(%%ecx, %%ecx, 2)");
TEST_LEA("-10(%%edx, %%ecx, 4)");
TEST_LEA("-10(%%esi, %%ecx, 8)");
TEST_LEA("0x4000(%%ecx, %%ecx, 2)");
TEST_LEA("0x4000(%%edx, %%ecx, 4)");
TEST_LEA("0x4000(%%esi, %%ecx, 8)");
#if defined(__x86_64__)
TEST_LEAQ("0x4000");
TEST_LEAQ("0x4000(%%rip)");
TEST_LEAQ("(%%rax)");
TEST_LEAQ("(%%rbx)");
TEST_LEAQ("(%%rcx)");
TEST_LEAQ("(%%rdx)");
TEST_LEAQ("(%%rsi)");
TEST_LEAQ("(%%rdi)");
TEST_LEAQ("0x40(%%rax)");
TEST_LEAQ("0x40(%%rbx)");
TEST_LEAQ("0x40(%%rcx)");
TEST_LEAQ("0x40(%%rdx)");
TEST_LEAQ("0x40(%%rsi)");
TEST_LEAQ("0x40(%%rdi)");
TEST_LEAQ("0x4000(%%rax)");
TEST_LEAQ("0x4000(%%rbx)");
TEST_LEAQ("0x4000(%%rcx)");
TEST_LEAQ("0x4000(%%rdx)");
TEST_LEAQ("0x4000(%%rsi)");
TEST_LEAQ("0x4000(%%rdi)");
TEST_LEAQ("(%%rax, %%rcx)");
TEST_LEAQ("(%%rbx, %%rdx)");
TEST_LEAQ("(%%rcx, %%rcx)");
TEST_LEAQ("(%%rdx, %%rcx)");
TEST_LEAQ("(%%rsi, %%rcx)");
TEST_LEAQ("(%%rdi, %%rcx)");
TEST_LEAQ("0x40(%%rax, %%rcx)");
TEST_LEAQ("0x4000(%%rbx, %%rdx)");
TEST_LEAQ("(%%rcx, %%rcx, 2)");
TEST_LEAQ("(%%rdx, %%rcx, 4)");
TEST_LEAQ("(%%rsi, %%rcx, 8)");
TEST_LEAQ("(,%%rax, 2)");
TEST_LEAQ("(,%%rbx, 4)");
TEST_LEAQ("(,%%rcx, 8)");
TEST_LEAQ("0x40(,%%rax, 2)");
TEST_LEAQ("0x40(,%%rbx, 4)");
TEST_LEAQ("0x40(,%%rcx, 8)");
TEST_LEAQ("-10(%%rcx, %%rcx, 2)");
TEST_LEAQ("-10(%%rdx, %%rcx, 4)");
TEST_LEAQ("-10(%%rsi, %%rcx, 8)");
TEST_LEAQ("0x4000(%%rcx, %%rcx, 2)");
TEST_LEAQ("0x4000(%%rdx, %%rcx, 4)");
TEST_LEAQ("0x4000(%%rsi, %%rcx, 8)");
#else
/* limited 16 bit addressing test */
TEST_LEA16("0x4000");
TEST_LEA16("(%%bx)");
TEST_LEA16("(%%si)");
TEST_LEA16("(%%di)");
TEST_LEA16("0x40(%%bx)");
TEST_LEA16("0x40(%%si)");
TEST_LEA16("0x40(%%di)");
TEST_LEA16("0x4000(%%bx)");
TEST_LEA16("0x4000(%%si)");
TEST_LEA16("(%%bx,%%si)");
TEST_LEA16("(%%bx,%%di)");
TEST_LEA16("0x40(%%bx,%%si)");
TEST_LEA16("0x40(%%bx,%%di)");
TEST_LEA16("0x4000(%%bx,%%si)");
TEST_LEA16("0x4000(%%bx,%%di)");
#endif
}
#define TEST_JCC(JCC, v1, v2)\
{\
int res;\
asm("movl $1, %0\n\t"\
"cmpl %2, %1\n\t"\
"j" JCC " 1f\n\t"\
"movl $0, %0\n\t"\
"1:\n\t"\
: "=r" (res)\
: "r" (v1), "r" (v2));\
printf("%-10s %d\n", "j" JCC, res);\
\
asm("movl $0, %0\n\t"\
"cmpl %2, %1\n\t"\
"set" JCC " %b0\n\t"\
: "=r" (res)\
: "r" (v1), "r" (v2));\
printf("%-10s %d\n", "set" JCC, res);\
if (TEST_CMOV) {\
long val = i2l(1);\
long res = i2l(0x12345678);\
X86_64_ONLY(\
asm("cmpl %2, %1\n\t"\
"cmov" JCC "q %3, %0\n\t"\
: "=r" (res)\
: "r" (v1), "r" (v2), "m" (val), "0" (res));\
printf("%-10s R=" FMTLX "\n", "cmov" JCC "q", res);)\
asm("cmpl %2, %1\n\t"\
"cmov" JCC "l %k3, %k0\n\t"\
: "=r" (res)\
: "r" (v1), "r" (v2), "m" (val), "0" (res));\
printf("%-10s R=" FMTLX "\n", "cmov" JCC "l", res);\
asm("cmpl %2, %1\n\t"\
"cmov" JCC "w %w3, %w0\n\t"\
: "=r" (res)\
: "r" (v1), "r" (v2), "r" (1), "0" (res));\
printf("%-10s R=" FMTLX "\n", "cmov" JCC "w", res);\
} \
}
/* various jump tests */
void test_jcc(void)
{
TEST_JCC("ne", 1, 1);
TEST_JCC("ne", 1, 0);
TEST_JCC("e", 1, 1);
TEST_JCC("e", 1, 0);
TEST_JCC("l", 1, 1);
TEST_JCC("l", 1, 0);
TEST_JCC("l", 1, -1);
TEST_JCC("le", 1, 1);
TEST_JCC("le", 1, 0);
TEST_JCC("le", 1, -1);
TEST_JCC("ge", 1, 1);
TEST_JCC("ge", 1, 0);
TEST_JCC("ge", -1, 1);
TEST_JCC("g", 1, 1);
TEST_JCC("g", 1, 0);
TEST_JCC("g", 1, -1);
TEST_JCC("b", 1, 1);
TEST_JCC("b", 1, 0);
TEST_JCC("b", 1, -1);
TEST_JCC("be", 1, 1);
TEST_JCC("be", 1, 0);
TEST_JCC("be", 1, -1);
TEST_JCC("ae", 1, 1);
TEST_JCC("ae", 1, 0);
TEST_JCC("ae", 1, -1);
TEST_JCC("a", 1, 1);
TEST_JCC("a", 1, 0);
TEST_JCC("a", 1, -1);
TEST_JCC("p", 1, 1);
TEST_JCC("p", 1, 0);
TEST_JCC("np", 1, 1);
TEST_JCC("np", 1, 0);
TEST_JCC("o", 0x7fffffff, 0);
TEST_JCC("o", 0x7fffffff, -1);
TEST_JCC("no", 0x7fffffff, 0);
TEST_JCC("no", 0x7fffffff, -1);
TEST_JCC("s", 0, 1);
TEST_JCC("s", 0, -1);
TEST_JCC("s", 0, 0);
TEST_JCC("ns", 0, 1);
TEST_JCC("ns", 0, -1);
TEST_JCC("ns", 0, 0);
}
#undef CC_MASK
#ifdef TEST_P4_FLAGS
#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
#else
#define CC_MASK (CC_O | CC_C)
#endif
#define OP mul
#include "test-i386-muldiv.h"
#define OP imul
#include "test-i386-muldiv.h"
void test_imulw2(long op0, long op1)
{
long res, s1, s0, flags;
s0 = op0;
s1 = op1;
res = s0;
flags = 0;
asm volatile ("push %4\n\t"
"popf\n\t"
"imulw %w2, %w0\n\t"
"pushf\n\t"
"pop %1\n\t"
: "=q" (res), "=g" (flags)
: "q" (s1), "0" (res), "1" (flags));
printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
"imulw", s0, s1, res, flags & CC_MASK);
}
void test_imull2(long op0, long op1)
{
long res, s1, s0, flags;
s0 = op0;
s1 = op1;
res = s0;
flags = 0;
asm volatile ("push %4\n\t"
"popf\n\t"
"imull %k2, %k0\n\t"
"pushf\n\t"
"pop %1\n\t"
: "=q" (res), "=g" (flags)
: "q" (s1), "0" (res), "1" (flags));
printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
"imull", s0, s1, res, flags & CC_MASK);
}
#if defined(__x86_64__)
void test_imulq2(long op0, long op1)
{
long res, s1, s0, flags;
s0 = op0;
s1 = op1;
res = s0;
flags = 0;
asm volatile ("push %4\n\t"
"popf\n\t"
"imulq %2, %0\n\t"
"pushf\n\t"
"pop %1\n\t"
: "=q" (res), "=g" (flags)
: "q" (s1), "0" (res), "1" (flags));
printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",
"imulq", s0, s1, res, flags & CC_MASK);
}
#endif
#define TEST_IMUL_IM(size, rsize, op0, op1)\
{\
long res, flags, s1;\
flags = 0;\
res = 0;\
s1 = op1;\
asm volatile ("push %3\n\t"\
"popf\n\t"\
"imul" size " $" #op0 ", %" rsize "2, %" rsize "0\n\t" \
"pushf\n\t"\
"pop %1\n\t"\
: "=r" (res), "=g" (flags)\
: "r" (s1), "1" (flags), "0" (res));\
printf("%-10s A=" FMTLX " B=" FMTLX " R=" FMTLX " CC=%04lx\n",\
"imul" size " im", (long)op0, (long)op1, res, flags & CC_MASK);\
}
#undef CC_MASK
#define CC_MASK (0)
#define OP div
#include "test-i386-muldiv.h"
#define OP idiv
#include "test-i386-muldiv.h"
void test_mul(void)
{
test_imulb(0x1234561d, 4);
test_imulb(3, -4);
test_imulb(0x80, 0x80);
test_imulb(0x10, 0x10);
test_imulw(0, 0x1234001d, 45);
test_imulw(0, 23, -45);
test_imulw(0, 0x8000, 0x8000);
test_imulw(0, 0x100, 0x100);
test_imull(0, 0x1234001d, 45);
test_imull(0, 23, -45);
test_imull(0, 0x80000000, 0x80000000);
test_imull(0, 0x10000, 0x10000);
test_mulb(0x1234561d, 4);
test_mulb(3, -4);
test_mulb(0x80, 0x80);
test_mulb(0x10, 0x10);
test_mulw(0, 0x1234001d, 45);
test_mulw(0, 23, -45);
test_mulw(0, 0x8000, 0x8000);
test_mulw(0, 0x100, 0x100);
test_mull(0, 0x1234001d, 45);
test_mull(0, 23, -45);
test_mull(0, 0x80000000, 0x80000000);
test_mull(0, 0x10000, 0x10000);
test_imulw2(0x1234001d, 45);
test_imulw2(23, -45);
test_imulw2(0x8000, 0x8000);
test_imulw2(0x100, 0x100);
test_imull2(0x1234001d, 45);
test_imull2(23, -45);
test_imull2(0x80000000, 0x80000000);
test_imull2(0x10000, 0x10000);
TEST_IMUL_IM("w", "w", 45, 0x1234);
TEST_IMUL_IM("w", "w", -45, 23);
TEST_IMUL_IM("w", "w", 0x8000, 0x80000000);
TEST_IMUL_IM("w", "w", 0x7fff, 0x1000);
TEST_IMUL_IM("l", "k", 45, 0x1234);
TEST_IMUL_IM("l", "k", -45, 23);
TEST_IMUL_IM("l", "k", 0x8000, 0x80000000);
TEST_IMUL_IM("l", "k", 0x7fff, 0x1000);
test_idivb(0x12341678, 0x127e);
test_idivb(0x43210123, -5);
test_idivb(0x12340004, -1);
test_idivw(0, 0x12345678, 12347);
test_idivw(0, -23223, -45);
test_idivw(0, 0x12348000, -1);
test_idivw(0x12343, 0x12345678, 0x81238567);
test_idivl(0, 0x12345678, 12347);
test_idivl(0, -233223, -45);
test_idivl(0, 0x80000000, -1);
test_idivl(0x12343, 0x12345678, 0x81234567);
test_divb(0x12341678, 0x127e);
test_divb(0x43210123, -5);
test_divb(0x12340004, -1);
test_divw(0, 0x12345678, 12347);
test_divw(0, -23223, -45);
test_divw(0, 0x12348000, -1);
test_divw(0x12343, 0x12345678, 0x81238567);
test_divl(0, 0x12345678, 12347);
test_divl(0, -233223, -45);
test_divl(0, 0x80000000, -1);
test_divl(0x12343, 0x12345678, 0x81234567);
#if defined(__x86_64__)
test_imulq(0, 0x1234001d1234001d, 45);
test_imulq(0, 23, -45);
test_imulq(0, 0x8000000000000000, 0x8000000000000000);
test_imulq(0, 0x100000000, 0x100000000);
test_mulq(0, 0x1234001d1234001d, 45);
test_mulq(0, 23, -45);
test_mulq(0, 0x8000000000000000, 0x8000000000000000);
test_mulq(0, 0x100000000, 0x100000000);
test_imulq2(0x1234001d1234001d, 45);
test_imulq2(23, -45);
test_imulq2(0x8000000000000000, 0x8000000000000000);
test_imulq2(0x100000000, 0x100000000);
TEST_IMUL_IM("q", "", 45, 0x12341234);
TEST_IMUL_IM("q", "", -45, 23);
TEST_IMUL_IM("q", "", 0x8000, 0x8000000000000000);
TEST_IMUL_IM("q", "", 0x7fff, 0x10000000);
test_idivq(0, 0x12345678abcdef, 12347);
test_idivq(0, -233223, -45);
test_idivq(0, 0x8000000000000000, -1);
test_idivq(0x12343, 0x12345678, 0x81234567);
test_divq(0, 0x12345678abcdef, 12347);
test_divq(0, -233223, -45);
test_divq(0, 0x8000000000000000, -1);
test_divq(0x12343, 0x12345678, 0x81234567);
#endif
}
#define TEST_BSX(op, size, op0)\
{\
long res, val, resz;\
val = op0;\
asm("xor %1, %1\n"\
"mov $0x12345678, %0\n"\
#op " %" size "2, %" size "0 ; setz %b1" \
: "=r" (res), "=q" (resz)\
: "g" (val));\
printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
}
void test_bsx(void)
{
TEST_BSX(bsrw, "w", 0);
TEST_BSX(bsrw, "w", 0x12340128);
TEST_BSX(bsfw, "w", 0);
TEST_BSX(bsfw, "w", 0x12340128);
TEST_BSX(bsrl, "k", 0);
TEST_BSX(bsrl, "k", 0x00340128);
TEST_BSX(bsfl, "k", 0);
TEST_BSX(bsfl, "k", 0x00340128);
#if defined(__x86_64__)
TEST_BSX(bsrq, "", 0);
TEST_BSX(bsrq, "", 0x003401281234);
TEST_BSX(bsfq, "", 0);
TEST_BSX(bsfq, "", 0x003401281234);
#endif
}
/**********************************************/
union float64u {
double d;
uint64_t l;
};
union float64u q_nan = { .l = 0xFFF8000000000000 };
union float64u s_nan = { .l = 0xFFF0000000000000 };
void test_fops(double a, double b)
{
printf("a=%f b=%f a+b=%f\n", a, b, a + b);
printf("a=%f b=%f a-b=%f\n", a, b, a - b);
printf("a=%f b=%f a*b=%f\n", a, b, a * b);
printf("a=%f b=%f a/b=%f\n", a, b, a / b);
printf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
printf("a=%f sqrt(a)=%f\n", a, sqrt(a));
printf("a=%f sin(a)=%f\n", a, sin(a));
printf("a=%f cos(a)=%f\n", a, cos(a));
printf("a=%f tan(a)=%f\n", a, tan(a));
printf("a=%f log(a)=%f\n", a, log(a));
printf("a=%f exp(a)=%f\n", a, exp(a));
printf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
/* just to test some op combining */
printf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
printf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
printf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
}
void fpu_clear_exceptions(void)
{
struct __attribute__((packed)) {
uint16_t fpuc;
uint16_t dummy1;
uint16_t fpus;
uint16_t dummy2;
uint16_t fptag;
uint16_t dummy3;
uint32_t ignored[4];
long double fpregs[8];
} float_env32;
asm volatile ("fnstenv %0\n" : : "m" (float_env32));
float_env32.fpus &= ~0x7f;
asm volatile ("fldenv %0\n" : : "m" (float_env32));
}
/* XXX: display exception bits when supported */
#define FPUS_EMASK 0x0000
//#define FPUS_EMASK 0x007f
void test_fcmp(double a, double b)
{
long eflags, fpus;
fpu_clear_exceptions();
asm("fcom %2\n"
"fstsw %%ax\n"
: "=a" (fpus)
: "t" (a), "u" (b));
printf("fcom(%f %f)=%04lx \n",
a, b, fpus & (0x4500 | FPUS_EMASK));
fpu_clear_exceptions();
asm("fucom %2\n"
"fstsw %%ax\n"
: "=a" (fpus)
: "t" (a), "u" (b));
printf("fucom(%f %f)=%04lx\n",
a, b, fpus & (0x4500 | FPUS_EMASK));
if (TEST_FCOMI) {
/* test f(u)comi instruction */
fpu_clear_exceptions();
asm("fcomi %3, %2\n"
"fstsw %%ax\n"
"pushf\n"
"pop %0\n"
: "=r" (eflags), "=a" (fpus)
: "t" (a), "u" (b));
printf("fcomi(%f %f)=%04lx %02lx\n",
a, b, fpus & FPUS_EMASK, eflags & (CC_Z | CC_P | CC_C));
fpu_clear_exceptions();
asm("fucomi %3, %2\n"
"fstsw %%ax\n"
"pushf\n"
"pop %0\n"
: "=r" (eflags), "=a" (fpus)
: "t" (a), "u" (b));
printf("fucomi(%f %f)=%04lx %02lx\n",
a, b, fpus & FPUS_EMASK, eflags & (CC_Z | CC_P | CC_C));
}
fpu_clear_exceptions();
asm volatile("fxam\n"
"fstsw %%ax\n"
: "=a" (fpus)
: "t" (a));
printf("fxam(%f)=%04lx\n", a, fpus & 0x4700);
fpu_clear_exceptions();
}
void test_fcvt(double a)
{
float fa;
long double la;
int16_t fpuc;
int i;
int64_t lla;
int ia;
int16_t wa;
double ra;
fa = a;
la = a;
printf("(float)%f = %f\n", a, fa);
printf("(long double)%f = %Lf\n", a, la);
printf("a=" FMT64X "\n", *(uint64_t *)&a);
printf("la=" FMT64X " %04x\n", *(uint64_t *)&la,
*(unsigned short *)((char *)(&la) + 8));
/* test all roundings */
asm volatile ("fstcw %0" : "=m" (fpuc));
for(i=0;i<4;i++) {
asm volatile ("fldcw %0" : : "m" ((fpuc & ~0x0c00) | (i << 10)));
asm volatile ("fist %0" : "=m" (wa) : "t" (a));
asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
asm volatile ("fldcw %0" : : "m" (fpuc));
printf("(short)a = %d\n", wa);
printf("(int)a = %d\n", ia);
printf("(int64_t)a = " FMT64X "\n", lla);
printf("rint(a) = %f\n", ra);
}
}
#define TEST(N) \
asm("fld" #N : "=t" (a)); \
printf("fld" #N "= %f\n", a);
void test_fconst(void)
{
double a;
TEST(1);
TEST(l2t);
TEST(l2e);
TEST(pi);
TEST(lg2);
TEST(ln2);
TEST(z);
}
void test_fbcd(double a)
{
unsigned short bcd[5];
double b;
asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
printf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
}
#define TEST_ENV(env, save, restore)\
{\
memset((env), 0xaa, sizeof(*(env)));\
for(i=0;i<5;i++)\
asm volatile ("fldl %0" : : "m" (dtab[i]));\
asm volatile (save " %0\n" : : "m" (*(env)));\
asm volatile (restore " %0\n": : "m" (*(env)));\
for(i=0;i<5;i++)\
asm volatile ("fstpl %0" : "=m" (rtab[i]));\
for(i=0;i<5;i++)\
printf("res[%d]=%f\n", i, rtab[i]);\
printf("fpuc=%04x fpus=%04x fptag=%04x\n",\
(env)->fpuc,\
(env)->fpus & 0xff00,\
(env)->fptag);\
}
void test_fenv(void)
{
struct __attribute__((packed)) {
uint16_t fpuc;
uint16_t dummy1;
uint16_t fpus;
uint16_t dummy2;
uint16_t fptag;
uint16_t dummy3;
uint32_t ignored[4];
long double fpregs[8];
} float_env32;
struct __attribute__((packed)) {
uint16_t fpuc;
uint16_t fpus;
uint16_t fptag;
uint16_t ignored[4];
long double fpregs[8];
} float_env16;
double dtab[8];
double rtab[8];
int i;
for(i=0;i<8;i++)
dtab[i] = i + 1;
TEST_ENV(&float_env16, "data16 fnstenv", "data16 fldenv");
TEST_ENV(&float_env16, "data16 fnsave", "data16 frstor");
TEST_ENV(&float_env32, "fnstenv", "fldenv");
TEST_ENV(&float_env32, "fnsave", "frstor");
/* test for ffree */
for(i=0;i<5;i++)
asm volatile ("fldl %0" : : "m" (dtab[i]));
asm volatile("ffree %st(2)");
asm volatile ("fnstenv %0\n" : : "m" (float_env32));
asm volatile ("fninit");
printf("fptag=%04x\n", float_env32.fptag);
}
#define TEST_FCMOV(a, b, eflags, CC)\
{\
double res;\
asm("push %3\n"\
"popf\n"\
"fcmov" CC " %2, %0\n"\
: "=t" (res)\
: "0" (a), "u" (b), "g" (eflags));\
printf("fcmov%s eflags=0x%04lx-> %f\n", \
CC, (long)eflags, res);\
}
void test_fcmov(void)
{
double a, b;
long eflags, i;
a = 1.0;
b = 2.0;
for(i = 0; i < 4; i++) {
eflags = 0;
if (i & 1)
eflags |= CC_C;
if (i & 2)
eflags |= CC_Z;
TEST_FCMOV(a, b, eflags, "b");
TEST_FCMOV(a, b, eflags, "e");
TEST_FCMOV(a, b, eflags, "be");
TEST_FCMOV(a, b, eflags, "nb");
TEST_FCMOV(a, b, eflags, "ne");
TEST_FCMOV(a, b, eflags, "nbe");
}
TEST_FCMOV(a, b, 0, "u");
TEST_FCMOV(a, b, CC_P, "u");
TEST_FCMOV(a, b, 0, "nu");
TEST_FCMOV(a, b, CC_P, "nu");
}
void test_floats(void)
{
test_fops(2, 3);
test_fops(1.4, -5);
test_fcmp(2, -1);
test_fcmp(2, 2);
test_fcmp(2, 3);
test_fcmp(2, q_nan.d);
test_fcmp(q_nan.d, -1);
test_fcmp(-1.0/0.0, -1);
test_fcmp(1.0/0.0, -1);
test_fcvt(0.5);
test_fcvt(-0.5);
test_fcvt(1.0/7.0);
test_fcvt(-1.0/9.0);
test_fcvt(32768);
test_fcvt(-1e20);
test_fcvt(-1.0/0.0);
test_fcvt(1.0/0.0);
test_fcvt(q_nan.d);
test_fconst();
test_fbcd(1234567890123456);
test_fbcd(-123451234567890);
test_fenv();
if (TEST_CMOV) {
test_fcmov();
}
}
/**********************************************/
#if !defined(__x86_64__)
#define TEST_BCD(op, op0, cc_in, cc_mask)\
{\
int res, flags;\
res = op0;\
flags = cc_in;\
asm ("push %3\n\t"\
"popf\n\t"\
#op "\n\t"\
"pushf\n\t"\
"pop %1\n\t"\
: "=a" (res), "=g" (flags)\