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Commits

Commits on Nov 24, 2014

More long path name support on Windows, this time in program execution.
Paul Robinson
committed
[Hexagon] Adding asrh instruction, removing unused multiclasses.
Colin LeMahieu
committed
[Hexagon] Adding aslh instruction.
Colin LeMahieu
committed
[Hexagon] Adding zxth instruction.
Colin LeMahieu
committed
Adding const iterator to MCInst. http://reviews.llvm.org/D6359
Colin LeMahieu
committed
[Hexagon] Adding zxtb instruction.
Colin LeMahieu
committed
InstCombine: Don't create an unused instruction
majnemer
committed
[mips][microMIPS] Fix JRADDIUSP instruction
Jozef Kolek
committed
Added comment about llvm_execute_on_thread waiting for thread to complete.
yrnkrn
committed
[mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions
Jozef Kolek
committed
[mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0
Jozef Kolek
committed
[Mips] Update MIPS relocations list
atanasyan
committed
Replace a comment that says 'unreachable' with llvm_unreachable in TableGen AsmWriter output.
topperc
committed
Removing a variable that is initialized but never read. The original author has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime.
AaronBallman
committed
[mips][microMIPS] Implement disassembler support for 16-bit instructions
Jozef Kolek
committed
[X86] Improved target specific combine on VSELECT dag nodes.
adibiagio
committed
InstCombine: Don't assume DataLayout is always available
majnemer
committed
Support: Add *cast_or_null<> for pointer wrappers
dexonsmith
committed
Detect best type for some static index tables instead of just using uint32_t to reduce total data size.
topperc
committed

Commits on Nov 23, 2014

Converted back to Unix format (after my last commit 222632)
Elena Demikhovsky
committed
[X86] Fixes bug in build_vector v4x32 lowering
Michael Kuperstein
committed
Add missing override keywords.
topperc
committed
Tablegen output formatting fixes.
topperc
committed
Masked Vector Load and Store Intrinsics.
Elena Demikhovsky
committed
R600: Fix extloads of i1 on R600/Evergreen
arsenm
committed
R600: Fix assert on copy of an i1 on pre-SI
arsenm
committed
R600/SI: Add additional tests for i1 loads
arsenm
committed
R600/SI: Fix broken check lines and modernize prefixes
arsenm
committed
R600/SI: Fix missing -verify-machineinstrs on a test
arsenm
committed

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Commits on Nov 24, 2014

Commits on Nov 23, 2014

Commits on Nov 22, 2014

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