- Circuit: 8-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add8u_0FP | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add8u_5R3 | 0.039 | 0.20 | 25.00 | 0.14 | 0.2 | [Verilog] [VerilogPDK45] [C] |
| add8u_5QL | 0.16 | 0.59 | 43.75 | 0.40 | 1.5 | [Verilog] [VerilogPDK45] [C] |
| add8u_5LT | 0.33 | 1.37 | 71.88 | 0.91 | 6.0 | [Verilog] [VerilogPDK45] [C] |
| add8u_5HQ | 0.68 | 2.93 | 85.74 | 1.80 | 24 | [Verilog] [VerilogPDK45] [C] |
| add8u_5SY | 1.05 | 3.12 | 94.14 | 2.93 | 44 | [Verilog] [VerilogPDK45] [C] |
| add8u_8LL | 1.97 | 6.25 | 96.97 | 6.16 | 154 | [Verilog] [C] |
| add8u_006 | 4.92 | 17.97 | 98.77 | 14.58 | 960 | [Verilog] [C] |
| add8u_8ES | 8.28 | 25.59 | 99.24 | 25.01 | 2692 | [Verilog] [C] |
| add8u_88L | 19.67 | 50.39 | 99.77 | 49.16 | 14074 | [Verilog] [C] |
- V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188
- V. Mrazek, R. Hrbacek, Z. Vasicek and L. Sekanina, "EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 258-261. doi: 10.23919/DATE.2017.7926993
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020