From 1cc744a2e5297118aeed122a8dd5c4d57c091d0b Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Tue, 15 May 2018 16:05:04 +0000 Subject: [PATCH] [mips] Mark select instructions correctly Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46702 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332364 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsInstrFPU.td | 17 ++ lib/Target/Mips/MicroMipsInstrInfo.td | 37 ++- lib/Target/Mips/MipsCondMov.td | 289 +++++++++--------- test/CodeGen/Mips/llvm-ir/add.ll | 22 +- test/CodeGen/Mips/llvm-ir/lshr.ll | 133 ++++---- test/CodeGen/Mips/llvm-ir/select-dbl.ll | 73 ++--- test/CodeGen/Mips/llvm-ir/select-flt.ll | 68 ++--- test/CodeGen/Mips/llvm-ir/select-int.ll | 14 +- test/CodeGen/Mips/llvm-ir/shl.ll | 152 +++++---- test/MC/Mips/micromips-movcond-instructions.s | 12 +- 10 files changed, 429 insertions(+), 388 deletions(-) diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td index 413206d8b78d..12ef03f9ad93 100644 --- a/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/lib/Target/Mips/MicroMipsInstrFPU.td @@ -414,3 +414,20 @@ def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), (CVT_S_D32_MM AFGR64Opnd:$src)>, ISA_MICROMIPS, FGR_32; def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), (CVT_D32_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS, FGR_32; + +// Selects +defm : MovzPats0, + ISA_MICROMIPS32_NOT_MIPS32R6; +defm : MovzPats1, + ISA_MICROMIPS32_NOT_MIPS32R6; + +defm : MovnPats, + ISA_MICROMIPS32_NOT_MIPS32R6; + +defm : MovzPats0, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; +defm : MovzPats1, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; +defm : MovnPats, + ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 869014a215bd..a8c053b440dc 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -894,13 +894,15 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Move Conditional def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, - NoItinerary>, ADD_FM_MM<0, 0x58>; + II_MOVZ>, ADD_FM_MM<0, 0x58>, + ISA_MICROMIPS32_NOT_MIPS32R6; def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, - NoItinerary>, ADD_FM_MM<0, 0x18>; - def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>, - CMov_F_I_FM_MM<0x25>; - def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>, - CMov_F_I_FM_MM<0x5>; + II_MOVN>, ADD_FM_MM<0, 0x18>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>, + CMov_F_I_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6; + def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, + CMov_F_I_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6; /// Move to/from HI/LO def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, @@ -1228,6 +1230,29 @@ defm : SetgtPats; defm : SetgePats; defm : SetgeImmPats; +// Select patterns + +// Instantiation of conditional move patterns. +defm : MovzPats0, + ISA_MICROMIPS32_NOT_MIPS32R6; +defm : MovzPats1, + ISA_MICROMIPS32_NOT_MIPS32R6; +defm : MovzPats2, + ISA_MICROMIPS32_NOT_MIPS32R6; + + +defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6; + +// Instantiation of conditional move patterns. +defm : MovzPats0, + ISA_MICROMIPS32_NOT_MIPS32R6; +defm : MovzPats1, + ISA_MICROMIPS32_NOT_MIPS32R6; +defm : MovzPats2, + ISA_MICROMIPS32_NOT_MIPS32R6; + +defm : MovnPats, ISA_MICROMIPS32_NOT_MIPS32R6; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td index 75ebdeb2bb89..39dc2654aa6a 100644 --- a/lib/Target/Mips/MipsCondMov.td +++ b/lib/Target/Mips/MipsCondMov.td @@ -104,163 +104,162 @@ multiclass MovnPats, - ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; - -let isCodeGenOnly = 1 in { - def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>, - ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; - def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>, - ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; - def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>, - ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; -} - -def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>, - ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; - -let isCodeGenOnly = 1 in { - def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>, - ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; - def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>, - ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; - def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>, - ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; -} let AdditionalPredicates = [NotInMicroMips] in { -def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, - CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6; - -let isCodeGenOnly = 1 in -def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>, - CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>, + ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; -def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, - CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6; + let isCodeGenOnly = 1 in { + def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>, + ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; + def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>, + ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; + def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>, + ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; + } -let isCodeGenOnly = 1 in -def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, - CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>, + ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; -def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, - II_MOVZ_D>, CMov_I_F_FM<18, 17>, - INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; -def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, - II_MOVN_D>, CMov_I_F_FM<19, 17>, - INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; -} -let DecoderNamespace = "MipsFP64" in { - def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>, - CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; - def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>, - CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; let isCodeGenOnly = 1 in { - def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>, - CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; - def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>, - CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>, + ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; + def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>, + ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; + def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>, + ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; + } + def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, + CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6; + + let isCodeGenOnly = 1 in + def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>, + CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + + def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, + CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6; + + let isCodeGenOnly = 1 in + def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, + CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + + def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, + II_MOVZ_D>, CMov_I_F_FM<18, 17>, + INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; + def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, + II_MOVN_D>, CMov_I_F_FM<19, 17>, + INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; + + let DecoderNamespace = "MipsFP64" in { + def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>, + CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>, + CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + let isCodeGenOnly = 1 in { + def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>, + CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>, + CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + } } -} -def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>, - CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6; + def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>, + CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6; -let isCodeGenOnly = 1 in -def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>, - CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + let isCodeGenOnly = 1 in + def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>, + CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, - CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6; + def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, + CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6; -let isCodeGenOnly = 1 in -def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>, - CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -let AdditionalPredicates = [NotInMicroMips] in { -def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, - CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6; -def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, - CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6; - -def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, - MipsCMovFP_T>, CMov_F_F_FM<17, 1>, - INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; -def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, - MipsCMovFP_F>, CMov_F_F_FM<17, 0>, - INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; -} -let DecoderNamespace = "MipsFP64" in { - def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>, - CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; - def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>, - CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; -} + let isCodeGenOnly = 1 in + def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>, + CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, + CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6; + def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, + CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6; -// Instantiation of conditional move patterns. -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6; -defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6; -defm : MovzPats2, INSN_MIPS4_32_NOT_32R6_64R6; - -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats1, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats1, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats1, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats2, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats2, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats2, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; - -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6; - -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, - GPR_64; -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, - GPR_64; -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, - GPR_64; - -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6; -defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6; -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6; - -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; -defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6, - GPR_64; -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, - GPR_64; - -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; -defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6, - FGR_32; -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, - FGR_32; - -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; -defm : MovzPats0, - INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; -defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6, - FGR_64; -defm : MovzPats1, - INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, - FGR_64; -defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, - FGR_64; + def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, + MipsCMovFP_T>, CMov_F_F_FM<17, 1>, + INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; + def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, + MipsCMovFP_F>, CMov_F_F_FM<17, 0>, + INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; + let DecoderNamespace = "MipsFP64" in { + def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>, + CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>, + CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + } + + // Instantiation of conditional move patterns. + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6; + defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6; + defm : MovzPats2, INSN_MIPS4_32_NOT_32R6_64R6; + + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats1, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats1, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats1, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats2, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats2, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats2, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6; + + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, + GPR_64; + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, + GPR_64; + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, + GPR_64; + + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6; + defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6; + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6; + + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; + defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6, + GPR_64; + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, + GPR_64; + + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; + defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6, + FGR_32; + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, + FGR_32; + + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + defm : MovzPats0, + INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + defm : MovzPats1, INSN_MIPS4_32_NOT_32R6_64R6, + FGR_64; + defm : MovzPats1, + INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, + FGR_64; + defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, + FGR_64; +} // For targets that don't have conditional-move instructions // we have to match SELECT nodes with pseudo instructions. let usesCustomInserter = 1 in { diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll index 2a7ae5a71533..84c4bf677f94 100644 --- a/test/CodeGen/Mips/llvm-ir/add.ll +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -341,11 +341,10 @@ define signext i128 @add_i128_4(i128 signext %a) { ; MMR3: addiur2 $[[T0:[0-9]+]], $7, 4 ; MMR3: sltu $[[T1:[0-9]+]], $[[T0]], $7 - ; MMR3: sltu $[[T2:[0-9]+]], $[[T0]], $7 - ; MMR3: addu16 $[[T3:[0-9]+]], $6, $[[T2]] - ; MMR3: sltu $[[T4:[0-9]+]], $[[T3]], $6 - ; MMR3: movz $[[T4]], $[[T2]], $[[T1]] - ; MMR3: addu16 $[[T6:[0-9]+]], $5, $[[T4]] + ; MMR3: addu16 $[[T2:[0-9]+]], $6, $[[T1]] + ; MMR3: sltu $[[T3:[0-9]+]], $[[T2]], $6 + ; MMR3: movz $[[T3]], $[[T1]], $[[T1]] + ; MMR3: addu16 $[[T6:[0-9]+]], $5, $[[T3]] ; MMR3: sltu $[[T7:[0-9]+]], $[[T6]], $5 ; MMR3: addu16 $2, $4, $[[T7]] @@ -493,13 +492,12 @@ define signext i128 @add_i128_3(i128 signext %a) { ; MMR3: move $[[T1:[0-9]+]], $7 ; MMR3: addius5 $[[T1]], 3 ; MMR3: sltu $[[T2:[0-9]+]], $[[T1]], $7 - ; MMR3: sltu $[[T3:[0-9]+]], $[[T1]], $7 - ; MMR3: addu16 $[[T4:[0-9]+]], $6, $[[T3]] - ; MMR3: sltu $[[T5:[0-9]+]], $[[T4]], $6 - ; MMR3: movz $[[T5]], $[[T3]], $[[T2]] - ; MMR3: addu16 $[[T6:[0-9]+]], $5, $[[T5]] - ; MMR3: sltu $[[T7:[0-9]+]], $[[T6]], $5 - ; MMR3: addu16 $2, $4, $[[T7]] + ; MMR3: addu16 $[[T3:[0-9]+]], $6, $[[T2]] + ; MMR3: sltu $[[T4:[0-9]+]], $[[T3]], $6 + ; MMR3: movz $[[T4]], $[[T2]], $[[T2]] + ; MMR3: addu16 $[[T5:[0-9]+]], $5, $[[T4]] + ; MMR3: sltu $[[T6:[0-9]+]], $[[T5]], $5 + ; MMR3: addu16 $2, $4, $[[T6]] ; MMR6: move $[[T1:[0-9]+]], $7 ; MMR6: addius5 $[[T1]], 3 diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll index 79382e0df35a..5f18295cd635 100644 --- a/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -816,92 +816,89 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { ; ; MMR3-LABEL: lshr_i128: ; MMR3: # %bb.0: # %entry -; MMR3-NEXT: addiusp -48 -; MMR3-NEXT: .cfi_def_cfa_offset 48 -; MMR3-NEXT: sw $17, 44($sp) # 4-byte Folded Spill -; MMR3-NEXT: sw $16, 40($sp) # 4-byte Folded Spill +; MMR3-NEXT: addiusp -40 +; MMR3-NEXT: .cfi_def_cfa_offset 40 +; MMR3-NEXT: sw $17, 36($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $16, 32($sp) # 4-byte Folded Spill ; MMR3-NEXT: .cfi_offset 17, -4 ; MMR3-NEXT: .cfi_offset 16, -8 ; MMR3-NEXT: move $8, $7 -; MMR3-NEXT: sw $6, 32($sp) # 4-byte Folded Spill -; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $6, 24($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $4, 28($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $16, 68($sp) +; MMR3-NEXT: li16 $2, 64 +; MMR3-NEXT: subu16 $7, $2, $16 +; MMR3-NEXT: sllv $9, $5, $7 ; MMR3-NEXT: move $17, $5 -; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill -; MMR3-NEXT: lw $16, 76($sp) -; MMR3-NEXT: srlv $7, $7, $16 +; MMR3-NEXT: sw $5, 0($sp) # 4-byte Folded Spill +; MMR3-NEXT: andi16 $3, $7, 32 +; MMR3-NEXT: sw $3, 20($sp) # 4-byte Folded Spill +; MMR3-NEXT: li16 $2, 0 +; MMR3-NEXT: move $4, $9 +; MMR3-NEXT: movn $4, $2, $3 +; MMR3-NEXT: srlv $5, $8, $16 ; MMR3-NEXT: not16 $3, $16 -; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill +; MMR3-NEXT: sw $3, 16($sp) # 4-byte Folded Spill ; MMR3-NEXT: sll16 $2, $6, 1 -; MMR3-NEXT: sllv $3, $2, $3 -; MMR3-NEXT: li16 $4, 64 -; MMR3-NEXT: or16 $3, $7 +; MMR3-NEXT: sllv $2, $2, $3 +; MMR3-NEXT: or16 $2, $5 ; MMR3-NEXT: srlv $5, $6, $16 -; MMR3-NEXT: sw $5, 12($sp) # 4-byte Folded Spill -; MMR3-NEXT: subu16 $7, $4, $16 -; MMR3-NEXT: sllv $9, $17, $7 -; MMR3-NEXT: andi16 $2, $7, 32 -; MMR3-NEXT: sw $2, 28($sp) # 4-byte Folded Spill -; MMR3-NEXT: andi16 $17, $16, 32 -; MMR3-NEXT: sw $17, 16($sp) # 4-byte Folded Spill -; MMR3-NEXT: move $4, $9 -; MMR3-NEXT: li16 $6, 0 -; MMR3-NEXT: movn $4, $6, $2 -; MMR3-NEXT: movn $3, $5, $17 -; MMR3-NEXT: addiu $2, $16, -64 -; MMR3-NEXT: lw $5, 36($sp) # 4-byte Folded Reload -; MMR3-NEXT: srlv $5, $5, $2 -; MMR3-NEXT: sw $5, 20($sp) # 4-byte Folded Spill -; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload -; MMR3-NEXT: sll16 $6, $17, 1 -; MMR3-NEXT: sw $6, 4($sp) # 4-byte Folded Spill -; MMR3-NEXT: not16 $5, $2 +; MMR3-NEXT: sw $5, 4($sp) # 4-byte Folded Spill +; MMR3-NEXT: andi16 $3, $16, 32 +; MMR3-NEXT: sw $3, 12($sp) # 4-byte Folded Spill +; MMR3-NEXT: movn $2, $5, $3 +; MMR3-NEXT: addiu $3, $16, -64 +; MMR3-NEXT: or16 $2, $4 +; MMR3-NEXT: srlv $4, $17, $3 +; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill +; MMR3-NEXT: lw $4, 28($sp) # 4-byte Folded Reload +; MMR3-NEXT: sll16 $6, $4, 1 +; MMR3-NEXT: not16 $5, $3 ; MMR3-NEXT: sllv $5, $6, $5 -; MMR3-NEXT: or16 $3, $4 -; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload -; MMR3-NEXT: or16 $5, $4 -; MMR3-NEXT: srlv $1, $17, $2 -; MMR3-NEXT: andi16 $2, $2, 32 -; MMR3-NEXT: sw $2, 20($sp) # 4-byte Folded Spill -; MMR3-NEXT: movn $5, $1, $2 -; MMR3-NEXT: sllv $2, $17, $7 -; MMR3-NEXT: not16 $4, $7 -; MMR3-NEXT: lw $7, 36($sp) # 4-byte Folded Reload -; MMR3-NEXT: srl16 $6, $7, 1 -; MMR3-NEXT: srlv $4, $6, $4 -; MMR3-NEXT: sltiu $11, $16, 64 -; MMR3-NEXT: movn $5, $3, $11 +; MMR3-NEXT: lw $17, 8($sp) # 4-byte Folded Reload +; MMR3-NEXT: or16 $5, $17 +; MMR3-NEXT: srlv $1, $4, $3 +; MMR3-NEXT: andi16 $3, $3, 32 +; MMR3-NEXT: sw $3, 8($sp) # 4-byte Folded Spill +; MMR3-NEXT: movn $5, $1, $3 +; MMR3-NEXT: sltiu $10, $16, 64 +; MMR3-NEXT: movn $5, $2, $10 +; MMR3-NEXT: sllv $2, $4, $7 +; MMR3-NEXT: not16 $3, $7 +; MMR3-NEXT: lw $7, 0($sp) # 4-byte Folded Reload +; MMR3-NEXT: srl16 $4, $7, 1 +; MMR3-NEXT: srlv $4, $4, $3 ; MMR3-NEXT: or16 $4, $2 ; MMR3-NEXT: srlv $2, $7, $16 -; MMR3-NEXT: lw $3, 24($sp) # 4-byte Folded Reload -; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $3, 16($sp) # 4-byte Folded Reload ; MMR3-NEXT: sllv $3, $6, $3 ; MMR3-NEXT: or16 $3, $2 -; MMR3-NEXT: srlv $2, $17, $16 -; MMR3-NEXT: lw $6, 16($sp) # 4-byte Folded Reload -; MMR3-NEXT: movn $3, $2, $6 -; MMR3-NEXT: sltiu $10, $16, 64 +; MMR3-NEXT: lw $2, 28($sp) # 4-byte Folded Reload +; MMR3-NEXT: srlv $2, $2, $16 +; MMR3-NEXT: lw $17, 12($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $3, $2, $17 ; MMR3-NEXT: movz $5, $8, $16 +; MMR3-NEXT: li16 $6, 0 +; MMR3-NEXT: movz $3, $6, $10 +; MMR3-NEXT: lw $7, 20($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $4, $9, $7 +; MMR3-NEXT: lw $6, 4($sp) # 4-byte Folded Reload +; MMR3-NEXT: li16 $7, 0 +; MMR3-NEXT: movn $6, $7, $17 +; MMR3-NEXT: or16 $6, $4 +; MMR3-NEXT: lw $4, 8($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $1, $7, $4 ; MMR3-NEXT: li16 $7, 0 -; MMR3-NEXT: movz $3, $7, $10 -; MMR3-NEXT: lw $17, 28($sp) # 4-byte Folded Reload -; MMR3-NEXT: movn $4, $9, $17 -; MMR3-NEXT: lw $7, 12($sp) # 4-byte Folded Reload -; MMR3-NEXT: li16 $17, 0 -; MMR3-NEXT: movn $7, $17, $6 -; MMR3-NEXT: or16 $7, $4 -; MMR3-NEXT: lw $4, 20($sp) # 4-byte Folded Reload -; MMR3-NEXT: movn $1, $17, $4 -; MMR3-NEXT: li16 $17, 0 -; MMR3-NEXT: movn $1, $7, $11 -; MMR3-NEXT: lw $4, 32($sp) # 4-byte Folded Reload +; MMR3-NEXT: movn $1, $6, $10 +; MMR3-NEXT: lw $4, 24($sp) # 4-byte Folded Reload ; MMR3-NEXT: movz $1, $4, $16 -; MMR3-NEXT: movn $2, $17, $6 +; MMR3-NEXT: movn $2, $7, $17 ; MMR3-NEXT: li16 $4, 0 ; MMR3-NEXT: movz $2, $4, $10 ; MMR3-NEXT: move $4, $1 -; MMR3-NEXT: lw $16, 40($sp) # 4-byte Folded Reload -; MMR3-NEXT: lw $17, 44($sp) # 4-byte Folded Reload -; MMR3-NEXT: addiusp 48 +; MMR3-NEXT: lw $16, 32($sp) # 4-byte Folded Reload +; MMR3-NEXT: lw $17, 36($sp) # 4-byte Folded Reload +; MMR3-NEXT: addiusp 40 ; MMR3-NEXT: jrc $ra ; ; MMR6-LABEL: lshr_i128: diff --git a/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/test/CodeGen/Mips/llvm-ir/select-dbl.ll index 3f79a238888e..65fea4594903 100644 --- a/test/CodeGen/Mips/llvm-ir/select-dbl.ll +++ b/test/CodeGen/Mips/llvm-ir/select-dbl.ll @@ -25,7 +25,8 @@ ; RUN: -check-prefix=CMOV64 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=64R6 -; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 \ +; RUN: -asm-show-inst -mattr=+micromips -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=MM32R3 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=MM32R6 @@ -98,12 +99,12 @@ define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { ; ; MM32R3-LABEL: tst_select_i1_double: ; MM32R3: # %bb.0: # %entry -; MM32R3-NEXT: mtc1 $7, $f2 -; MM32R3-NEXT: mthc1 $6, $f2 -; MM32R3-NEXT: andi16 $2, $4, 1 -; MM32R3-NEXT: ldc1 $f0, 16($sp) -; MM32R3-NEXT: jr $ra -; MM32R3-NEXT: movn.d $f0, $f2, $2 +; MM32R3: mtc1 $7, $f2 #