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Commits on May 4, 2018

• [SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCI

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• [RegUsageInfoCollector] Bugfix for handling of register aliases.

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• [IRCE] Fix misuse of dyn_cast which leads to UB

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• [XRay][compiler-rt+docs] Introduce __xray_log_init_mode(...).

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• [MachineCSE] Rewrite a loop checking if a block is in a set of blocks without using a set. NFC.

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  Michael Zolotukhin

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• [LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.

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• [LoopIdiomRecognize] Use a regular array instead of a SmallVector and explicit ArrayRef.

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• [LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.

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Commits on May 3, 2018

• [LoopIdiomRecognize] Add a test case to show incorrect transformation of an infinite loop with side effets into a countable loop using ctlz.

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• AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo

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• [X86] Add WriteDPPD/WriteDPPS dot product scheduler classes

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• [X86][Znver1] Use SchedAlias to tag microcoded scheduler classes

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• Fix include of config.h that was incorrectly changed in r331184

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• [InstCombine] refine select-of-constants to bitwise ops

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• GlobalISel: Use a callback to compute constrained reg class for unallocatble registers

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• [ThinLTO] Add support for optimization remarks to thinBackend

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• [PowerPC] add more FMF debug output; NFC

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• [X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.

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• [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes

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• [PowerPC] add tests for FMF propagation; NFC

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• [DebugInfo] Correction for an assert in DIExpression::createFragmentExpression

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• Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"

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• use LLVM's standard CMakeLists.txt layout for llvm-xray

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• [CodeGen][X86][NFC] Copy two selectcc tests from AArch64.

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• [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes

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• ARM: don't try to over-align large vectors as arguments.

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• perform DSE through launder.invariant.group

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• Rename invariant.group.barrier to launder.invariant.group

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• [X86][AVX512] VPAVG instructions should be tagged as SchedWriteVecALU

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• [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM scheduler classes

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• [X86] Update MMX instructions to be tagged with X86SchedWriteWidths types

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• [WebAssembly] MC: Don't litter test directory.

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• Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"

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• [TableGen][NFC] Make ResourceCycles definitions more explicit.

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• [LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the left hand side of the 'and' matches the left hand side of the 'subtract'

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