Skip to content

Latest commit

 

History

History
11 lines (7 loc) · 638 Bytes

sparse.rst

File metadata and controls

11 lines (7 loc) · 638 Bytes

Sparse computation

The LLVM backends (CPU/CUDA) offer full functionality of spatially sparse computation in Taichi.

Please read our paper, watch the introduction video, or check out the SIGGRAPH Asia 2019 slides for more details on sparse computation.

Taichi elements implements an high-performance MLS-MPM solver on Taichi's sparse grids.