This crate contains simple code examples for Hippomenes.
This crate requires the Rust compiler for compiling, and the elf2mem
utility for generating the binary dump file Verilog uses to populate the ROM component.
To set up the Rust toolchain, consult Install Rust.
On Linux, this amounts to running:
curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
With the Rust toolchain set up, elf2mem
can be installed by cloning the elf2mem
repository, and installing the tool via cargo
:
git clone [email protected]:perlindgren/elf2mem.git
cargo install --path ./elf2mem
To compile one of the examples use:
cargo build --example <EXAMPLE> --release
To dump the generated binary as a Verilog .mem
file use:
elf2mem -f ./target/riscv32i-unknown-none-elf/release/examples/<EXAMPLE> -t binary.mem
To resynthesize, and replace the Hippomenes memory component, and reprogram your Arty board under Linux or Windows, the ../fpga/program_arty.sh
and ../fpga/program_arty.cmd
scripts can be used respectively.
Under Linux, all of the above steps can be performed via the runner, so running one of the examples on your board amounts to
cargo run --example <EXAMPLE> --release
The asm
example emits the contents of asm.s
as a global assembly block, and links it using memory.x
.
This is a simple example of running the RTIC framework.
Currently, the hippomenes fork of the framework ONLY supports hardware tasks WITH shared resources.