LicheeTang 蜂鸟E203 Core

A small 32-bit implementation of the RISC-V architecture

An APB bridge and mux generator based on the junctions/Poci chisel code

Verilog Matrix ALU

This is a custom CPU simulation created written in Verilog. The system is capable of operating upon matrices and integers, with support of matrices that are up to 4x4 with elements that are 16 bits…

HDL Project: Create a simplistic Matrix engine in Verilog with an ISA that performs some basic functions on 4x4 matrices.