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papi_events.csv
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papi_events.csv
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#
# Every CPU automatically has PAPI_TOT_CYC and PAPI_TOT_INS added
#
# Processor identifier and additional flags.
# The processor identifier *can not* contain any comma characters as these
# characters serve to delimit fields.
#
CPU,AMD64 (K7)
CPU,amd64_k7
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
CPU,AMD64
CPU,AMD64 (unknown model)
CPU,AMD64 (K8 RevB)
CPU,AMD64 (K8 RevC)
CPU,AMD64 (K8 RevD)
CPU,AMD64 (K8 RevE)
CPU,AMD64 (K8 RevF)
CPU,AMD64 (K8 RevG)
CPU,amd64_k8_revb
CPU,amd64_k8_revc
CPU,amd64_k8_revd
CPU,amd64_k8_reve
CPU,amd64_k8_revf
CPU,amd64_k8_revg
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY
PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED
PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY
PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:PACKED_SSE_AND_SSE2
# This definition give an accurate count of the instructions retired through the FP unit
# It counts just about everything except MMX and 3DNow instructions
# Unfortunately, it also counts loads and stores. Therefore the count will be uniformly
# high, but proportional to the work done.
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2
#/* This definition is speculative but gives good answers on our simple test cases
# It overcounts FP operations, sometimes by A LOT, but doesn't count loads and stores
PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY:OPS_ADD,NOTE,'Counts speculative adds and multiplies. Variable and higher than theoretical.'
#
CPU,AMD64 FPU RETIRED
#
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,NOTE,"Counts all retired floating point operations, including data movement. Precise, and proportional to work done, but much higher than theoretical."
#
CPU,AMD64 FPU SPECULATIVE
#
PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY:OPS_ADD,NOTE,"Counts speculative adds and multiplies. Variable and higher than theoretical."
#
CPU,AMD64 FPU SSE_SP
#
PRESET,PAPI_FP_OPS,DERIVED_SUB,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,DISPATCHED_FPU:OPS_STORE,NOTE,"Counts retired ops corrected for data motion. Optimized for single precision; lower than theoretical."
#
CPU,AMD64 FPU SSE_DP
#
PRESET,PAPI_FP_OPS,DERIVED_SUB,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,DISPATCHED_FPU:OPS_STORE_PIPE_LOAD_OPS,NOTE,"Counts retired ops corrected for data motion. Optimized for double precision; lower than theoretical."
#
########################
# AMD64 #
########################
CPU,AMD64 (Barcelona)
CPU,AMD64 (Barcelona RevB)
CPU,AMD64 (Barcelona RevC)
CPU,AMD64 (Family 10h RevB Barcelona)
CPU,AMD64 (Family 10h RevC Shanghai)
CPU,AMD64 (Family 10h RevD Istanbul)
CPU,AMD64 (Family 10h RevE)
CPU,amd64_fam10h_barcelona
CPU,amd64_fam10h_shanghai
CPU,amd64_fam10h_istanbul
CPU,amd64_fam11h_turion
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
#
# no L3_ preset definitions for multi-cores with shared L3 cache,
# as long as L3 events are automatically shadowed from core- to chip-space
# PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL
# PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL
# PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS:ALL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS:ALL,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY
PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED
PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY
PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:PACKED_SSE_AND_SSE2
#
# An analysis by Bill Homer of Cray indicates accurate counts over a range of conditions
# John McCalpin reports that OP_TYPE expands packed operation counts appropriately.
# Therefore, it is included in FP_OPS, but not in FP_INS.
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:OP_TYPE
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:OP_TYPE
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:OP_TYPE,NOTE,"Also includes subtract instructions"
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,"Counts both divide and square root instructions"
########################
# AMD64 fam12h llano #
########################
CPU,amd64_fam12h_llano
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
#
# no L3_ preset definitions for multi-cores with shared L3 cache,
# as long as L3 events are automatically shadowed from core- to chip-space
# PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL
# PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL
# PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS:ALL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS:ALL,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY
PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED
PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY
PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:SSE_AND_SSE2
#
# An analysis by Bill Homer of Cray indicates accurate counts over a range of conditions
# John McCalpin reports that OP_TYPE expands packed operation counts appropriately.
# Therefore, it is included in FP_OPS, but not in FP_INS.
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:OP_TYPE
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:OP_TYPE
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:OP_TYPE,NOTE,"Also includes subtract instructions"
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,"Counts both divide and square root instructions"
#########################
# AMD Fam14h Bobcat #
#########################
#
CPU,amd64_fam14h_bobcat
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_FLOATING_POINT_INSTRUCTIONS:ALL
PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:ANY
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:ALL
PRESET,PAPI_VEC_SP,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS
PRESET,PAPI_VEC_DP,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS
#
CPU,AMD64 (Family 15h RevB)
CPU,amd64_fam15h_interlagos
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
#
# not implemented: PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL
# not implemented: PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL
# not implemented: PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,UNIFIED_TLB_MISS:4K_DATA:2M_DATA:1GB_DATA
PRESET,PAPI_TLB_IM,NOT_DERIVED,UNIFIED_TLB_MISS:4K_INST:2M_INST:1G_INST
PRESET,PAPI_TLB_TL,NOT_DERIVED,UNIFIED_TLB_MISS:ALL
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_PRC,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY
PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_FPU_EMPTY
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPS:ALL
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:ALL
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS:SINGLE_MUL_ADD_OPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS:DOUBLE_MUL_ADD_OPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:SINGLE_MUL_ADD_OPS:DOUBLE_MUL_ADD_OPS,NOTE,"Also includes multiply-add instructions"
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:SINGLE_MUL_ADD_OPS:DOUBLE_MUL_ADD_OPS,NOTE,"Also includes subtract and multiply-add instructions"
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,"Counts both divide and square root instructions"
#
#
CPU,amd64_fam16h
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
#PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
# Only have 3 slots???
#PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
#
# Note, need access to special L2 uncore events
# to get L2 related events
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,DTLB_MISS,ITLB_MISS
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,INSTRUCTION_FETCH_STALL
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,"Counts both divide and square root instructions"
#
#
CPU,amd64_fam17h
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT
PRESET,PAPI_L1_ICH,DERIVED_SUB,32_BYTE_INSTRUCTION_CACHE_FETCH,32_BYTE_INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICM,NOT_DERIVED,32_BYTE_INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,32_BYTE_INSTRUCTION_CACHE_FETCH
PRESET,PAPI_L1_ICR,NOT_DERIVED,32_BYTE_INSTRUCTION_CACHE_FETCH
# Same event code, confusing name?
#PRESET,PAPI_L1_DCM,NOT_DERIVED,MAB_ALLOCATION_BY_PIPE
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,32_BYTE_INSTRUCTION_CACHE_FETCH
PRESET,PAPI_L2_ICA,NOT_DERIVED,32_BYTE_INSTRUCTION_CACHE_MISSES
#
# Note, need access to special L2 uncore events
# to get L2 related events
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_32K_L2_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_32K_L2_HIT:TLB_RELOAD_4K_L2_HIT
PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:IF1G:IF2M:IF4K
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
# Note, the processor supports various kinds of mispredictions
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,INSTRUCTION_PIPE_STALL:IC_STALL_ANY
#
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_ADD_SUB_FLOPS:SP_MULT_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_ADD_SUB_FLOPS:DP_MULT_FLOPS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_MULT_FLOPS:DP_MULT_FLOPS
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_ADD_SUB_FLOPS:DP_ADD_SUB_FLOPS
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_DIV_FLOPS:DP_DIV_FLOPS,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_DIV_FLOPS:DP_DIV_FLOPS,NOTE,"Counts both divide and square root instructions"
#
#
CPU,Intel architectural PMU
CPU,ix86arch
#
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
# Intel Atom
CPU,Intel Atom
CPU,atom
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
PRESET,PAPI_L1_DCM,DERIVED_SUB,L2_RQSTS:SELF:MESI,ICACHE:MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES
PRESET,PAPI_L1_ICH,DERIVED_SUB,ICACHE:ACCESSES,ICACHE:MISSES
#PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE:LD:ST
PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_CACHE:LD,L1D_CACHE:ST
PRESET,PAPI_L1_TCM,NOT_DERIVED,L2_RQSTS:SELF:MESI
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICM,NOT_DERIVED,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN:SELF:ANY
PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,L2_M_LINES_IN:SELF
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF
PRESET,PAPI_L2_DCA,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_ST:SELF:MESI
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_LD:SELF:ANY:MESI
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L2_ICH,DERIVED_SUB,L2_IFETCH:SELF:MESI,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:SELF:ANY:MESI,L2_LINES_IN:SELF:ANY
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:SELF:ANY:MESI
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI
#
PRESET,PAPI_CA_SNP,NOT_DERIVED,EXT_SNOOP:SELF:MESI
PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE
PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF
PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB:MISSES
PRESET,PAPI_TLB_DM,NOT_DERIVED,DATA_TLB_MISSES:DTLB_MISS
#
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:PRED_NOT_TAKEN:MISPRED_NOT_TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED
#
PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:ALL_DECODED
PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT_RCV
#PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY
#
#PRESET,PAPI_FP_INS,NOT_DERIVED,X87_COMP_OPS_EXE:ANY_AR
PRESET,PAPI_FP_INS,NOT_DERIVED,SIMD_INST_RETIRED:ANY
#PRESET,PAPI_FP_OPS,NOT_DERIVED,X87_COMP_OPS_EXE:ANY_AR
#PRESET,PAPI_FP_OPS,NOT_DERIVED,SIMD_UOPS_EXEC:AR
PRESET,PAPI_FP_OPS,DERIVED_ADD,SIMD_INST_RETIRED:ANY,X87_COMP_OPS_EXE:ANY_AR
PRESET,PAPI_FML_INS,NOT_DERIVED,MUL:AR
PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV:AR
PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR
#
# Intel Atom Silvermont
CPU,slm
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES
PRESET,PAPI_L1_ICH,DERIVED_SUB,ICACHE:ACCESSES,ICACHE:MISSES
PRESET,PAPI_L1_TCM,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_MISSES
PRESET,PAPI_L2_TCH,DERIVED_SUB,LLC_REFERENCES,LLC_MISSES
PRESET,PAPI_L2_TCA,NOT_DERIVED,LLC_REFERENCES
#
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:JCC
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED
#
PRESET,PAPI_RES_STL,NOT_DERIVED,UOPS_RETIRED:STALLS
#
#PRESET,PAPI_FP_INS,NOT_DERIVED,UOPS_RETIRED:X87
PRESET,PAPI_FML_INS,NOT_DERIVED,UOPS_RETIRED:MUL
PRESET,PAPI_FDV_INS,NOT_DERIVED,UOPS_RETIRED:DIV
#
CPU,Intel Nehalem
CPU,Intel Westmere
CPU,nhm
CPU,nhm_ex
CPU,wsm
CPU,wsm_dp
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTION_RETIRED
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I:MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I:READS
PRESET,PAPI_L1_ICH,NOT_DERIVED,L1I:HITS
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPL
#PRESET,PAPI_L1_TCM,NOT_DERIVED,L2_RQSTS:SELF:MESI
#PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI
#PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI
# OLD VALUE PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_RQSTS:MISS,L2_RQSTS:IFETCH_MISS
PRESET,PAPI_L2_DCM,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:RFO_MISS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:IFETCH_MISS
# OLD VALUE PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_RQSTS:MISS
PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:LD_MISS
#PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF
# OLD VALUE PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_DATA_RQSTS:ANY
PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPL
# OLD VALUE PRESET,PAPI_L2_DCR,DERIVED_SUB,L2_RQSTS:LOADS,L2_RQSTS:IFETCHES
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:LOADS
#PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:IFETCH_HIT
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:IFETCHES
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:REFERENCES, L2_RQSTS:MISS
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:REFERENCES
# OLD VALUE PRESET,PAPI_L2_TCR,NOT_DERIVED,L2_RQSTS:LOADS
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:LOADS,L2_RQSTS:IFETCHES
#PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI
#
PRESET,PAPI_L1_ICR,NOT_DERIVED,L1I:READS
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:LOADS
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_WRITE:RFO_MESI
PRESET,PAPI_L1_TCM,DERIVED_SUB,L2_RQSTS:REFERENCES,L2_RQSTS:PREFETCHES
PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:LD_HIT,L2_RQSTS:RFO_HIT
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_WRITE:RFO_MESI
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:IFETCHES
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:RFOS
PRESET,PAPI_L3_DCA,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:RFO_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,L2_RQSTS:LD_MISS
PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:IFETCH_MISS
PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:IFETCH_MISS
PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS
PRESET,PAPI_L3_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L3_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES
PRESET,PAPI_L3_TCR,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:IFETCH_MISS
PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_INST_RETIRED:LOADS,MEM_INST_RETIRED:STORES
#
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_INST_RETIRED:LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_INST_RETIRED:STORES
#
#PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE
#PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF
#PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:ANY
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISSES:ANY
PRESET,PAPI_TLB_TL,DERIVED_ADD,ITLB_MISSES:ANY, DTLB_MISSES:ANY
#
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_EXEC:TAKEN
PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_EXEC:ANY, BR_INST_EXEC:TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_EXEC:ANY
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_EXEC:ANY
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_EXEC:COND
PRESET,PAPI_BR_UCN,NOT_DERIVED,BR_INST_EXEC:DIRECT
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_EXEC:COND, BR_MISP_EXEC:COND
#
PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:DECODED
PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY
#
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP
# PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP
# PAPI_FP_OPS counts single and double precision SCALAR operations
# PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION:SSE_DOUBLE_PRECISION
# According to Stephane (Jan 2010), it's not allowed to combine unit masks for FP_COMP_OPS_EXE;
# we have to use two counters instead
#PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION,FP_COMP_OPS_EXE:SSE_DOUBLE_PRECISION
PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_FP,FP_COMP_OPS_EXE:X87
# PAPI_SP_OPS = single precision scalar ops + 3 * packed ops
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|3|*|+|,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION,FP_COMP_OPS_EXE:SSE_FP_PACKED
PRESET,PAPI_DP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_DOUBLE_PRECISION,FP_COMP_OPS_EXE:SSE_FP_PACKED
PRESET,PAPI_VEC_SP,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP_PACKED
PRESET,PAPI_VEC_DP,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP_PACKED
#PRESET,PAPI_FML_INS,NOT_DERIVED,MUL
#PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV
#PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR
#
# Not available on Westmere
#
CPU,Intel Nehalem
CPU,nhm
CPU,nhm_ex
#PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT:RCV
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_ALL_REF:ANY
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_ALL_REF:ANY,L1D:REPL
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_ALL_REF:ANY,L1I:READS
#
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_LD:MESI
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_ST:MESI
PRESET,PAPI_L1_TCR,DERIVED_ADD,L1D_CACHE_LD:MESI,L1I:READS
PRESET,PAPI_L2_TCW,NOT_DERIVED,L1D_CACHE_ST:MESI
#
# Intel SandyBridge and IvyBridge
CPU,snb
CPU,snb_ep
CPU,ivb
CPU,ivb_ep
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTION_RETIRED
#
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_STORE_LOCK_RQSTS:ALL
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
PRESET,PAPI_L1_TCM,DERIVED_ADD,ICACHE:MISSES,L1D:REPLACEMENT
#
PRESET,PAPI_L2_DCM,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_STORE_LOCK_RQSTS:ALL
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L2_TCA,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD
#
PRESET,PAPI_L3_DCA,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD
PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L3_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES
PRESET,PAPI_L3_TCR,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:RFO_MISS
PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
#
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:ALL_BRANCHES
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:CAUSES_A_WALK
#
PRESET,PAPI_FDV_INS,NOT_DERIVED,ARITH:FPU_DIV
PRESET,PAPI_STL_ICY,NOT_DERIVED,ILD_STALL:IQ_FULL
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOP_RETIRED:ANY_LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOP_RETIRED:ANY_STORES
#
# Counts scalars only; no SSE or AVX is counted; includes speculative
PRESET,PAPI_FP_INS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:X87
PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:X87
#
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|N2|8|*|+|+|,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,SIMD_FP_256:PACKED_SINGLE
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|N2|4|*|+|+|,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,SIMD_FP_256:PACKED_DOUBLE
PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|4|*|N1|8|*|+|,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,SIMD_FP_256:PACKED_SINGLE
PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|2|*|N1|4|*|+|,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,SIMD_FP_256:PACKED_DOUBLE
#
# Intel SandyBridge only
CPU,snb
CPU,snb_ep
#
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:RFO_ANY
PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_RD_HIT,L2_RQSTS:RFO_HITS
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:CONDITIONAL
PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:CONDITIONAL
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_MISP_RETIRED:ALL_BRANCHES
PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK
#
# Intel IvyBridge only
CPU,ivb
CPU,ivb_ep
#
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:ALL_RFO
PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:DEMAND_DATA_RD_HIT,L2_RQSTS:RFO_HIT
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:COND
PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:COND
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:COND,BR_MISP_RETIRED:ALL_BRANCHES
PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:COND,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:DEMAND_LD_MISS_CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK
#PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INTERRUPTS
#
# Intel Haswell events
# Using also for Broadwell events, this is what the Linux kernel does
CPU,hsw
CPU,hsw_ep
CPU,bdw
CPU,bdw_ep
CPU,skl
# Note, libpfm4 treats Kaby Lake as just a form of skylake
CPU,kbl
CPU,skx
# Note, libpfm4 treats Cascade Lake-X as just a form of skylake-X
CPU,clx
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_THREAD_UNHALTED:THREAD_P
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
#PRESET,PAPI_REF_CYC,NOT_DERIVED,CPU_CLK_THREAD_UNHALTED:REF_XCLK
# Loads and stores
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ALL_LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ALL_STORES
PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_UOPS_RETIRED:ALL_LOADS,MEM_UOPS_RETIRED:ALL_STORES
# L1 cache
#PRESET,PAPI_L1_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L1_HIT
#PRESET,PAPI_L1_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L1_MISS
PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
# Added by FMB
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD
# L2 cache
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_REFERENCES
# NOTE on IVB it is PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT
#PRESET,PAPI_L2_DCH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT
#PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
#PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:REFERENCES
#PRESET,PAPI_L2_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_HIT
#PRESET,PAPI_L2_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_MISS
# Added by FMB
PRESET,PAPI_L2_DCM,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
#PRESET,PAPI_L2_LDH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS
PRESET,PAPI_L2_TCA,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_REFERENCES,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD
# L3 cache
#PRESET,PAPI_L3_TCA,NOT_DERIVED,LONGEST_LAT_CACHE:REFERENCE
#PRESET,PAPI_L3_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT
#PRESET,PAPI_L3_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_MISS
# Added by FMB
PRESET,PAPI_L3_DCA,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD
PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS
PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
#PRESET,PAPI_L3_LDH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT
PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_MISS
PRESET,PAPI_L3_TCA,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L3_TCM,NOT_DERIVED,LLC_MISSES
PRESET,PAPI_L3_TCR,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:DEMAND_RFO_MISS
PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS
# SMP
PRESET,PAPI_CA_SNP,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_ANY
PRESET,PAPI_CA_SHR,NOT_DERIVED,OFFCORE_REQUESTS:ALL_DATA_RD
PRESET,PAPI_CA_CLN,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_RFO
# TLB
PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK,DTLB_STORE_MISSES:MISS_CAUSES_A_WALK
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:MISS_CAUSES_A_WALK
# Stalls
PRESET,PAPI_MEM_WCY,NOT_DERIVED,RESOURCE_STALLS:SB
PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY
PRESET,PAPI_STL_CCY,NOT_DERIVED,UOPS_RETIRED:ALL:c=1:i=1
PRESET,PAPI_FUL_ICY,DERIVED_ADD,IDQ:ALL_DSB_CYCLES_4_UOPS,IDQ:ALL_MITE_CYCLES_4_UOPS
PRESET,PAPI_FUL_CCY,NOT_DERIVED,UOPS_RETIRED:ALL:c=4
# Branches
PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:CONDITIONAL
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:CONDITIONAL
PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:CONDITIONAL
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_MISP_RETIRED:CONDITIONAL
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES
CPU,hsw
CPU,hsw_ep
CPU,bdw
CPU,bdw_ep
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_TRANS:DEMAND_DATA_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_TRANS:L1D_WB
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_TRANS:RFO
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_TRANS:RFO
PRESET,PAPI_PRF_DM,NOT_DERIVED,L2_RQSTS:L2_PF_MISS
PRESET,PAPI_STL_ICY,NOT_DERIVED,IDQ:EMPTY
PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_FWD
CPU,hsw
CPU,hsw_ep
PRESET,PAPI_CA_INV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HITM
CPU,bdw
CPU,bdw_ep
PRESET,PAPI_CA_INV,NOT_DERIVED,OFFCORE_RESPONSE_0:HITM
# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE
# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE
PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE
PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE
CPU,skl
CPU,skx
CPU,clx
# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE + 8*512B_PACKED_DOUBLE
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE
# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE + 16*512B_PACKED_SINGLE
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE
PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE
PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_RQSTS:ALL_RFO
PRESET,PAPI_L2_DCW,DERIVED_ADD,L2_RQSTS:DEMAND_RFO_HIT,L2_RQSTS:RFO_HIT
PRESET,PAPI_L2_TCW,DERIVED_ADD,L2_RQSTS:DEMAND_RFO_HIT,L2_RQSTS:RFO_HIT
PRESET,PAPI_PRF_DM,NOT_DERIVED,L2_RQSTS:PF_MISS
PRESET,PAPI_STL_ICY,NOT_DERIVED,IDQ_UOPS_NOT_DELIVERED:CYCLES_0_UOPS_DELIV_CORE
PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HIT_WITH_FWD
# End of hsw,bdw,skl,clx list
#
#
# Intel MIC / Xeon-Phi / Knights Landing
# Intel Knights Mill
#
CPU,knl
CPU,knm
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES
PRESET,PAPI_L1_ICH,NOT_DERIVED,ICACHE:HIT
#
PRESET,PAPI_L1_DCA,DERIVED_ADD,MEM_UOPS_RETIRED:ANY_LD,MEM_UOPS_RETIRED:ANY_ST
PRESET,PAPI_L1_DCM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_DCU_MISS
PRESET,PAPI_L1_TCM,DERIVED_ADD,MEM_UOPS_RETIRED:LD_DCU_MISS,ICACHE:MISSES
PRESET,PAPI_L1_LDM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_DCU_MISS
#
PRESET,PAPI_L2_TCA,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_MISSES
PRESET,PAPI_L2_TCH,DERIVED_SUB,LLC_REFERENCES,LLC_MISSES
PRESET,PAPI_L2_LDM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_L2_MISS
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ANY_LD
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ANY_ST
PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_UOPS_RETIRED:ANY_LD,MEM_UOPS_RETIRED:ANY_ST
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_UTLB_MISS
#
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:JCC
PRESET,PAPI_BR_UCN,DERIVED_SUB,BRANCH_INSTRUCTIONS_RETIRED,BR_INST_RETIRED:JCC
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN_JCC
PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_RETIRED:JCC,BR_INST_RETIRED:TAKEN_JCC
#
PRESET,PAPI_RES_STL,NOT_DERIVED,RS_FULL_STALL:ANY
PRESET,PAPI_STL_ICY,NOT_DERIVED,NO_ALLOC_CYCLES:ANY
#
# End of knl,knm list
CPU,Intel Core2
CPU,Intel Core
CPU,core
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_READS
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_READS,L1I_MISSES
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_REPL
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_ALL_REF
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_ALL_REF,L1D_REPL
PRESET,PAPI_L1_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_ALL_REF,L1I_READS
PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICM,NOT_DERIVED,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN:SELF:ANY
PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,L2_M_LINES_IN:SELF
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF
PRESET,PAPI_L2_DCA,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_ST:SELF:MESI
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_LD:SELF:ANY:MESI
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L2_ICH,DERIVED_SUB,L2_IFETCH:SELF:MESI,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:SELF:ANY:MESI,L2_LINES_IN:SELF:ANY
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:SELF:ANY:MESI
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI
#
PRESET,PAPI_LD_INS,NOT_DERIVED,INST_RETIRED:LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,INST_RETIRED:STORES
#
PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE
PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF
PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB:MISSES
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISSES:ANY
#
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:PRED_NOT_TAKEN:MISPRED_NOT_TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_EXEC
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISSP_EXEC
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_CND_EXEC
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_CND_EXEC,BR_CND_MISSP_EXEC
#
PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:DECODED
PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT_RCV
PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY
#
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_OPS_EXE
# This is an alternate definition of OPS that produces no error with calibrate
# the previous definition was identical to FP_INS
# PRESET,PAPI_FP_OPS,NOT_DERIVED,X87_OPS_RETIRED:ANY
# PRESET,PAPI_FP_OPS,DERIVED_ADD, FP_COMP_OPS_EXE, SIMD_COMP_INST_RETIRED:SCALAR_DOUBLE:PACKED_DOUBLE:SCALAR_SINGLE:PACKED_SINGLE
PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE
# PAPI_SP_OPS = FP_COMP_OPS_EXE + 3 * SIMD_COMP_INST_RETIRED:PACKED_SINGLE
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|3|*|+|,FP_COMP_OPS_EXE,SIMD_COMP_INST_RETIRED:PACKED_SINGLE
PRESET,PAPI_DP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE,SIMD_COMP_INST_RETIRED:PACKED_DOUBLE
PRESET,PAPI_VEC_SP,NOT_DERIVED,SIMD_COMP_INST_RETIRED:PACKED_SINGLE
PRESET,PAPI_VEC_DP,NOT_DERIVED,SIMD_COMP_INST_RETIRED:PACKED_DOUBLE
#
PRESET,PAPI_FML_INS,NOT_DERIVED,MUL
PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV
PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR
#
CPU,Intel Core Duo/Solo
CPU,coreduo
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_TAKEN_RET
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED
PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES
PRESET,PAPI_L2_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_INSTR_RET
PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_INSTR_RET
#
PRESET,PAPI_L1_DCM,NOT_DERIVED, DCACHE_REPL
PRESET,PAPI_L1_ICM,NOT_DERIVED, L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_DCM,DERIVED_SUB, L2_LINES_IN:SELF:ANY, BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICM,NOT_DERIVED, BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L1_TCM,NOT_DERIVED, L2_RQSTS:SELF:MESI
#PRESET,PAPI_L2_TCM,NOT_DERIVED, L2_LINES_IN:SELF:ANY
PRESET,PAPI_CA_SHR,NOT_DERIVED, L2_RQSTS:SELF:ANY:S_STATE
PRESET,PAPI_CA_CLN,NOT_DERIVED, BUS_TRANS_RFO:SELF
PRESET,PAPI_CA_ITV,NOT_DERIVED, BUS_TRANS_INVAL:SELF
PRESET,PAPI_TLB_IM,NOT_DERIVED, ITLB_MISSES
PRESET,PAPI_TLB_DM,NOT_DERIVED, DTLB_MISS
PRESET,PAPI_L1_LDM,NOT_DERIVED, L2_LD:SELF:MESI
PRESET,PAPI_L1_STM,NOT_DERIVED, L2_ST:SELF:MESI
PRESET,PAPI_L2_LDM,DERIVED_SUB, L2_LINES_IN:SELF:ANY, L2_M_LINES_IN:SELF
PRESET,PAPI_L2_STM,NOT_DERIVED, L2_M_LINES_IN:SELF
PRESET,PAPI_BTAC_M,NOT_DERIVED, PREF_RQSTS_DN
PRESET,PAPI_HW_INT,NOT_DERIVED, HW_INT_RX
PRESET,PAPI_BR_CN,NOT_DERIVED, BR_CND_EXEC
PRESET,PAPI_BR_TKN,NOT_DERIVED, BR_TAKEN_RET
PRESET,PAPI_BR_NTK,DERIVED_SUB, BR_INSTR_RET,BR_TAKEN_RET
PRESET,PAPI_BR_MSP,NOT_DERIVED, BR_MISSP_EXEC
PRESET,PAPI_BR_PRC,DERIVED_SUB, BR_INSTR_RET,BR_MISPRED_RET
PRESET,PAPI_TOT_IIS,NOT_DERIVED, INSTR_DECODED