-
Notifications
You must be signed in to change notification settings - Fork 44
/
hexagon.cpp
1069 lines (922 loc) · 32.4 KB
/
hexagon.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* A Hexagon Processor module for IDAPRO.
*
* Author: Willem Hengeveld <[email protected]>
*
*/
#include <name.hpp>
#include <idp.hpp>
#include <auto.hpp> // atype_t
#include <loader.hpp> // HT_IDP
#include <offset.hpp> // HT_IDP
#include <string>
#include <vector>
#include <bfd.h>
#include <dis-asm.h>
#include <stdlib.h>
#include <stdint.h>
#include <map>
#include <list>
#include "logging.h"
#include "pmbase.h"
#ifdef TRACELOG
FILE *g_log = NULL;
#endif
#if IDA_SDK_VERSION >= 700
#ifdef IDA70BETA3
#define get_many_bytes(ea, buf, size) get_bytes(ea, buf, size)
#else
#define get_many_bytes(ea, buf, size) get_bytes(buf, size, ea)
#endif
#define procName procname
#endif
#ifdef _WIN32
#define strtoll _strtoui64
#endif
static const char *const shnames[] = { "QDSP6", NULL };
static const char *const lnames[] = { "Qualcomm Hexagon DSP v4", NULL };
// for debugging
std::string hexdump(const char*buf, size_t n)
{
std::string s;
s.resize(n*3);
char *p = &s[0];
while (n--)
p += qsnprintf(p, 4, " %02x", (unsigned char)*buf++);
return s;
}
// object providing an output target for the bfd code, so
// this IDA module will be able to use the output.
struct disasmoutput {
std::string text;
void initstream(disassemble_info*info)
{
info->fprintf_func = (fprintf_ftype)staticprintf;
info->stream = this;
}
__attribute__((__format__ (__printf__, 2, 0)))
int vprintf(const char*fmt, va_list va)
{
text.resize(text.size()+256);
size_t n= vsnprintf(&text[text.size()-256], 256, fmt, va);
text.resize(text.size()-256+n);
return n;
}
__attribute__((__format__ (__printf__, 2, 0)))
static int staticprintf(disasmoutput*obj, const char*fmt, ...)
{
va_list va;
va_start(va, fmt);
int rc= obj->vprintf(fmt, va);
va_end(va);
return rc;
}
};
// object providing the bfd code access to bytes in the IDA database
class memory {
public:
void initinfo(disassemble_info* info)
{
info->application_data = this;
info->read_memory_func = staticread;
info->memory_error_func = staticperror;
info->print_address_func = staticprintaddr;
info->symbol_at_address_func = staticsymbolataddr;
info->symbol_is_valid = staticsymbol_is_valid;
}
int read(bfd_vma memaddr, uint8_t *myaddr, unsigned int len, struct disassemble_info *info)
{
if (!get_many_bytes(memaddr, myaddr, len))
return 1;
else
return 0;
}
void perror(int status, bfd_vma memaddr, struct disassemble_info *info)
{
hextracelog("error(%d, %08lx)\n", status, memaddr);
}
// defined after hexagon_disasm
void printaddr(bfd_vma addr, struct disassemble_info *info);
int symbolataddr(bfd_vma addr, struct disassemble_info *info)
{
hextracelog("symataddr(%08lx)\n", addr);
return 0;
}
bfd_boolean symbol_is_valid(asymbol *sym, struct disassemble_info *info)
{
hextracelog("valid(%08lx, '%s', 0x%x)\n", sym->value, sym->name, sym->flags);
return true;
}
private:
static int staticread(bfd_vma memaddr, uint8_t *myaddr, unsigned int len, struct disassemble_info *info)
{
return ((memory*)info->application_data)->read(memaddr, myaddr, len, info);
}
static void staticperror(int status, bfd_vma memaddr, struct disassemble_info *info)
{
return ((memory*)info->application_data)->perror(status, memaddr, info);
}
static void staticprintaddr(bfd_vma addr, struct disassemble_info *info)
{
return ((memory*)info->application_data)->printaddr(addr, info);
}
static int staticsymbolataddr(bfd_vma addr, struct disassemble_info *info)
{
return ((memory*)info->application_data)->symbolataddr(addr, info);
}
static bfd_boolean staticsymbol_is_valid(asymbol *sym, struct disassemble_info *info)
{
return ((memory*)info->application_data)->symbol_is_valid(sym, info);
}
};
extern "C" const bfd_arch_info_type bfd_hexagon_arch;
// object wrapping calls to the objdump code
struct hexagon_disasm {
disassembler_ftype disfn;
disasmoutput out;
disassemble_info info;
memory mem;
struct state {
state( std::vector<uint32_t> addrs, std::vector<uint32_t> imms, std::string text)
: addrs(addrs), imms(imms), text(text)
{
}
std::vector<uint32_t> addrs;
std::vector<uint32_t> imms;
std::string text;
};
std::vector<uint32_t> addrs;
std::vector<uint32_t> imms;
std::string text;
int insnsize;
const bfd_arch_info_type *find_arch(const char*arch)
{
for (auto p= &bfd_hexagon_arch; p ; p= p->next)
if (strstr(p->printable_name, arch))
return p;
return &bfd_hexagon_arch;
}
hexagon_disasm()
{
bfd abfd= {0};
abfd.arch_info= find_arch("v55");
disfn= hexagon_get_disassembler(&abfd);
memset(&info,0,sizeof(info));
out.initstream(&info);
info.flavour = bfd_target_elf_flavour;
info.arch = bfd_arch_unknown; // bfd_arch_hexagon == 29 in hexagon source
info.octets_per_byte = 1;
info.endian_code = info.endian = BFD_ENDIAN_LITTLE;
info.bytes_per_chunk= 4;
info.display_endian= BFD_ENDIAN_LITTLE;
mem.initinfo(&info);
}
// called from memory.printaddr
void add_address(uint32_t addr)
{
addrs.push_back(addr);
out.text += "@";
}
void calldisasm(ea_t ea)
{
static ea_t lastea;
// note: the first instruction of a segment ( without valid preceeding instructions )
// may be disassembled incorrectly when it uses 'immext', because static variables inside objdump
// are not reset correctly.
//
// todo: process dummy NOPs to clear state.
// then keep track of hexagon packet starts by using SetFlags(0x20000000)
//
// todo: always disasm complete packet, then feed ida information per packet.
//
// * packet ends in: insn with PP=11, or a duplexinsn: PP=00
if (lastea!=ea && lastea!=ea-4) {
for (int i=-12 ; i<0 ; i+=4) {
addrs.clear();
imms.clear();
out.text.clear();
dbgprintf("disfn(%08x) catchup(%d)\n", ea+i, i);
disfn(ea+i, &info);
}
}
addrs.clear();
imms.clear();
out.text.clear();
dbgprintf("disfn(%08x)\n", ea);
disfn(ea, &info);
dbgprintf(" -> '%s'\n", out.text.c_str());
lastea= ea;
insnsize= 4;
}
int disasm(ea_t ea)
{
if (cachelookup(ea))
return 4;
calldisasm(ea);
//std::string version1= out.text;
text= out.text;
check_constants();
//dbgprintf("disasm(%08x) -> %s :: %s\n", ea, version1.c_str(), out.text.c_str());
cachestate(ea);
return insnsize;
}
void check_constants()
{
size_t pos= 0;
while (pos != std::string::npos) {
size_t h1= text.find('#', pos);
if (h1==std::string::npos)
break;
size_t n1= text.find_first_not_of('#', h1);
if (n1==std::string::npos)
break;
size_t e1= text.find_first_not_of("-0123456789abcdefx", n1);
char *endptr=(e1==std::string::npos) ? (&text[0]+text.size()) : &text[e1];
if (e1>n1) {
char *p;
int64_t value= strtoll(&text[n1], &p, 0);
if (p!=endptr) {
errprintf("NOTE: strtoll decoded differently: str='%s', num=%d..%d, strtoll: ..%d\n",
text.c_str(), (int)n1, (int)e1, int(p-&text[0]));
}
//dbgprintf("const: (#)%d .. (^#)%d (e)%d (p)%d (endnum)%d '%s' -> %d\n", (int)h1, (int)n1, (int)e1, int(p-&text[0]), int(endptr-&text[0]), text.c_str(), value);
imms.push_back(value);
text.replace(n1, e1-n1, "$");
}
pos= n1+1;
}
}
typedef std::map<ea_t, state> statemap_t;
typedef std::list<ea_t> history_t;
statemap_t _cache;
history_t _history;
bool cachelookup(ea_t ea)
{
auto i= _cache.find(ea);
if (i==_cache.end())
return false;
addrs= i->second.addrs;
imms= i->second.imms;
text= i->second.text;
dbgprintf("cache found(%zd/%zd) %08x\n", _cache.size(), _history.size(), ea);
return true;
}
void cachestate(ea_t ea)
{
_cache.insert(statemap_t::value_type(ea, state(addrs, imms, text)));
_history.push_back(ea);
if (_history.size()==16) {
_cache.erase(_history.front());
_history.pop_front();
}
}
};
// global object for objdump wrapper
hexagon_disasm H;
void memory::printaddr(bfd_vma addr, struct disassemble_info *info)
{
H.add_address(addr);
//hextracelog("addr(%08lx)", addr);
}
void dumpdb()
{
char buf[512];
if (get_input_file_path(buf, 512))
hextracelog("in: %s\n", buf);
}
// -------- hexagon instruction magic
bool haspp(uint32_t w)
{
return (w&0xc000)!=0;
}
bool is_duplex_insn(uint32_t w)
{
return (w&0xc000)==0;
}
bool is_packet_end(uint32_t w)
{
return ((w&0xc000)==0xc000) || is_duplex_insn(w);
}
// 01110001ii1xxxxxPPiiiiiiiiiiiiii Rx.L=#u16
bool is_load_low(uint32_t w)
{
return haspp(w) && ((w&0xff200000)==0x71200000);
}
// 01110010ii1xxxxxPPiiiiiiiiiiiiii Rx.H=#u16
bool is_load_high(uint32_t w)
{
return haspp(w) && ((w&0xff200000)==0x72200000);
}
bool isjumpfunc(ea_t ea)
{
return (get_dword(ea )==0xBFFD7F1D // { r29 = add (r29, #-8)
&& get_dword(ea+ 4)==0xA79DFCFE // memw (r29 + #-8) = r28 }
&& is_load_high(get_dword(ea+ 8)) // r28.h = #0x42F7
&& is_load_low(get_dword(ea+ 12)) // r28.l = #0x9F10
&& get_dword(ea+16)==0xB01D411D // { r29 = add (r29, #8)
&& get_dword(ea+20)==0x529C4000 // jumpr r28
&& get_dword(ea+24)==0x919DC01C); // r28 = memw (r29 + #0) }
}
uint16_t getloadhalfword(uint32_t w)
{
return (w&0x3fff) | ((w>>(22-14))&0xc000);
}
uint32_t getjumpfunctarget(ea_t ea)
{
uint16_t high= getloadhalfword(get_dword(ea+ 8));
uint16_t low = getloadhalfword(get_dword(ea+ 12));
return (high<<16)|low;
}
int get_load_regnum(uint32_t w)
{
return (w>>16)&0x1f;
}
// 0101101iiiiiiiiiPPiiiiiiiiiiiii0 call #r22:2
// 01011101ii0iiiiiPPi-0-uuiiiiiii- if (Pu) call #r15:2
// 01011101ii1iiiiiPPi-0-uuiiiiiii- if (!Pu) call #r15:2
bool is_immediate_call_insn(uint32_t w)
{
if (is_duplex_insn(w))
return false;
return ((w&0xFF000800)==0x5D000000) // if ( ? Pu4 ) call #r15:2
|| ((w&0xFE000001)==0x5A000000);// call #r22:2
// H.disasm(ea);
// if (H.text.find("call")!=H.text.npos)
// return 2;
}
// 01010000101sssssPP-------------- callr Rs
// 01010001000sssssPP----uu-------- if (Pu) callr Rs
// 01010001001sssssPP----uu-------- if (!Pu) callr Rs
bool is_register_call_insn(uint32_t w)
{
if (is_duplex_insn(w))
return false;
return ((w&0xFFE00000)==0x50a00000) // callr Rs32
|| ((w&0xFFC00000)==0x51000000);// if ( ? Pu4 ) callr Rs32
}
// 01010010100sssssPP-------------- jumpr Rs
bool is_register_jump(uint32_t w)
{
if (is_duplex_insn(w))
return false;
return (w&0xffe00000)==0x52800000; // jumpr Rs
}
int get_jump_register(uint32_t w)
{
return (w>>16)&0x1f;
}
// 0101100iiiiiiiiiPPiiiiiiiiiiiii- jump #r22:2
// 0001-110--iiddddPPIIIIIIiiiiiii- Rd=#U6 ; jump #r9:2
// 0001-111--iissssPP--ddddiiiiiii- Rd=Rs ; jump #r9:2
bool is_relative_jump(uint32_t w)
{
if (is_duplex_insn(w))
return false;
return ((w&0xfe000000)==0x58000000) // jump #imm
|| ((w&0xf6000000)==0x16000000); // Rd16 = [ #U6 | Rs16 ] ; jump #r9:2
}
// L2 1111101---0-- dealloc_return
// L2 1111111---0-- jumpr R31 Return
// 2109876543210
bool is_sub_return(uint16_t w)
{
return (w&0x1f44) == 0x1f40;
}
bool is_return(uint32_t w)
{
if (is_register_jump(w) && get_jump_register(w)==31) // jumpr r31
return true;
if (!is_duplex_insn(w)) {
return ((w&0xffff3c1f)==0x961e001e); // 1001011000011110PP0000-----11110 dealloc_return
}
uint8_t iclass= ((w>>29)<<1) | ((w>>13)&1);
uint16_t ilow= w&0x1fff;
uint16_t ihigh= (w>>16)&0x1fff;
// note: jump ( and i assume deallocreturn ) must be in slot#0
if (iclass==1 && is_sub_return(ilow))
return true;
if (iclass==2 && is_sub_return(ilow))
return true;
if (iclass==5 && is_sub_return(ilow))
return true;
return false;
}
bool is_immext(uint32_t w)
{
return haspp(w)
&& ((w&0xf0000000)==0);
}
// note: wrong, and not yet used
// - i should include conditional jumps as well.
bool is_basic_block_end(uint32_t w)
{
if (is_register_jump(w))
return true;
if (is_relative_jump(w))
return true;
if (is_return(w))
return true;
return false;
}
enum insns {
insn_other,
insn_call,
insn_jump,
insn_stop
};
// these instructions are only used internally in this processor module,
// they are not actually shown.
instruc_t Instructions[] = {
{ "", 0 },
{ "call", CF_CALL },
{ "jump", CF_JUMP },
{ "stop", CF_STOP },
};
void force_offset(const insn_t &cmd, int n, ea_t base, bool issub = false)
{
uint32_t target= cmd.ops[0].value + base;
if ( !is_off(get_flags(cmd.ea), n)
|| get_offbase(cmd.ea, n) != base )
{
if (is_mapped(target)) {
refinfo_t ri;
ri.init(REF_OFF32|REFINFO_NOBASE|(issub ? REFINFO_SUBTRACT : 0), base);
int rc1= op_offset_ex(cmd.ea, n, &ri);
dbgprintf("%08x->%08x opoff base=%08x -> %d\n", cmd.ea, target, base, rc1);
}
else {
dbgprintf("%08x opoff base=%08x, target %08x not enabled\n", cmd.ea, base, target);
}
}
else {
dbgprintf("%08x->%08x opoff already done\n", cmd.ea, target);
}
}
// module registration
static asm_t gas = {
ASH_HEXF3|ASD_DECF0|ASO_OCTF1|ASB_BINF3|AS_N2CHR|AS_LALIGN|AS_1TEXT|AS_ONEDUP|AS_COLON,
1, // uflag
"GNU assembler", // name
0, // help
NULL, // header
".org", // origin
".end", // end
"@", // comment string
'"', // string delimiter
'\'', // char delimiter
"\"'", // special symbols in char and string constants
".ascii", // ascii
".byte", // byte
".short", // word
".long", // dword
".quad", // qword
NULL, // oword (16 bytes)
".float", // float
".double", // double
NULL, // tbyte (no information about this directive)
NULL, // packreal
".ds.#s(b,w,l,d) #d, #v", // arrays (#h,#d,#v,#s(...)
".ds.b %s", // bss
".equ", // equ
NULL, // seg
".", // char *a_curip;
NULL, // function header
NULL, // function footer
".globl", // public
NULL, // weak
".extern", // extrn
NULL, // comdef
NULL, // get name of type
".align", // align
'(', ')', // lbrace, rbrace
"%", // mod
"&", // and
"|", // or
"^", // xor
"~", // not
">>", // shl
"<<", // shr
NULL, // sizeof
0, // flag2
NULL, // cmnt2
NULL, // low8
NULL, // high8
NULL, // low16
NULL, // high16
NULL, // include
NULL, // vstruc
NULL, // rva
NULL, // yword
};
asm_t *asms[] = { &gas, NULL };
static const char *const RegNames[] =
{
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "SP", "FP", "LR",
"sa0", "lc0", "sa1", "lc1", "p3", "p2", "p1", "p0", "m0", "m1", "usr", "pc", "ugp", "gp",
"cs", "ds"
};
#define rVcs (qnumber(RegNames)-2)
#define rVds (qnumber(RegNames)-1)
//--------------------------------------------------------------------------
static const uchar retcode_jmplr[] = { 0x00, 0xc0, 0x9f, 0x52 };
static const bytes_t retcodes[] =
{
{ sizeof(retcode_jmplr), retcode_jmplr },
{ 0, NULL }
};
class hexagon_module : public processor_module {
public:
int ana_insn(insn_t &cmd) override
{
hextracelog("ana(%08x)\n", cmd.ea);
if (cmd.ea & 3)
return 0;
H.disasm(cmd.ea);
if (H.text.find("<unknown>")!=H.text.npos)
return 0;
static ea_t prevea; // what instruction did we previously process?
static int packetflags; // used to keep track of the current packet properties
// when not going through the code linearly reset the flags.
if (prevea+4!=cmd.ea) {
packetflags= 0;
}
cmd.size= H.insnsize;
uint32_t opcode= get_dword(cmd.ea);
// handle instruction packet boundaries
if (is_return(opcode)) {
packetflags |= CF_STOP;
if (is_packet_end(opcode))
cmd.itype= insn_stop;
else
cmd.itype= insn_other;
}
else if (is_immediate_call_insn(opcode)) {
cmd.itype= insn_call;
}
else if (is_relative_jump(opcode) || is_register_jump(opcode) || is_return(opcode)) {
packetflags |= CF_STOP;
if (is_packet_end(opcode))
cmd.itype= insn_stop;
else
cmd.itype= insn_other;
}
else {
if (is_packet_end(opcode)) {
if (packetflags&CF_STOP)
cmd.itype= insn_stop;
else
cmd.itype= insn_other;
}
else {
cmd.itype= insn_other;
}
}
dbgprintf("%08x -> type: %x: %s, flags=%x: %s\n", cmd.ea, cmd.itype, Instructions[cmd.itype].name, packetflags, H.text.c_str());
// translate operands
op_t *op= cmd.ops;
op_t *opend = cmd.ops+6;
int ia= 0;
int im= 0;
for (std::string::iterator i= H.text.begin() ; i != H.text.end() ; ++i)
{
switch(*i) {
case '@':
if (op==opend) {
errprintf("too many operands: '%s'\n", H.text.c_str());
}
else if (ia<H.addrs.size()) {
op->type= (cmd.itype || H.text.find("jump")!=H.text.npos) ? o_near : o_mem;
op->addr= H.addrs[ia++];
op->dtype = dt_dword;
dbgprintf("ana->op%d : adr %08x, t=%d\n", op->n, op->addr, op->type);
op++;
}
else {
errprintf("too many addresses(%d>=%zd): '%s'\n", ia, H.addrs.size(), H.text.c_str());
}
break;
case '$':
if (op==opend) {
errprintf("too many operands: '%s'\n", H.text.c_str());
}
else if (im<H.imms.size()) {
op->type= o_imm;
op->value= H.imms[im++];
op->dtype = dt_dword;
dbgprintf("ana->op%d : imm %08x\n", op->n, op->value);
op++;
}
else {
errprintf("too many immediates: '%s'\n", H.text.c_str());
}
break;
}
}
if (is_packet_end(opcode))
packetflags= 0;
prevea= cmd.ea;
return cmd.size;
}
int emu_insn(const insn_t& cmd) override
{
hextracelog("emu(%08x), itype=%d\n", cmd.ea, cmd.itype);
uint32_t insn= get_dword(cmd.ea);
// note: insn_jump and insn_stop do not cause a cref fl_F
if (cmd.itype==insn_call || cmd.itype==insn_other) {
//printf("adding flow %08x -> +%d\n", cmd.ea, cmd.size);
cmd.add_cref(cmd.ea+cmd.size, 0, fl_F);
}
// attempt to convert Rx32.[hl] = #u16 instruction pairs to real offsets
// problem is that doing so causes ida to get stuck trying to 'emu'
// the current instruction
if (is_load_low(insn)) {
int i=4;
while (i<=16) {
uint32_t previnsn= get_dword(cmd.ea-i);
if (is_load_high(previnsn)) {
if (get_load_regnum(insn)==get_load_regnum(previnsn)) {
force_offset(cmd, 0, getloadhalfword(previnsn)<<16);
break;
}
}
uint32_t nextinsn= get_dword(cmd.ea+i);
if (is_load_high(nextinsn)) {
if (get_load_regnum(insn)==get_load_regnum(nextinsn)) {
force_offset(cmd, 0, getloadhalfword(nextinsn)<<16);
break;
}
}
i+=4;
}
}
for (int i=0 ; i<6 ; i++)
{
if (cmd.ops[i].type==o_near) {
dbgprintf("adding cref\n");
if (!is_immediate_call_insn(insn))
cmd.add_cref(cmd.ops[i].addr, i, fl_JN);
else
cmd.add_cref(cmd.ops[i].addr, i, fl_CN);
}
else if (cmd.ops[i].type==o_mem) {
dbgprintf("adding dref\n");
// todo: figure out if we are loading or storing.
cmd.add_dref(cmd.ops[i].addr, i, dr_R);
}
else if (cmd.ops[i].type==o_imm) {
if (!is_immext(insn)) {
if (is_mapped(cmd.ops[i].value))
force_offset(cmd, i, 0);
if (is_off(get_flags(cmd.ea), i)) {
dbgprintf("adding drefs\n");
//cmd.add_dref(target, i, dr_O);
cmd.add_off_drefs(cmd.ops[i], dr_O, 0/*outflags*/);
}
}
else {
op_num(cmd.ea, i);
}
}
}
// trace stack pointer -> add_auto_stkpnt2(get_func(cmd.ea), cmd.ea+cmd.size, delta);
// r29 = {add|sub}(r29, #)
//
// create stackvars:
// ua_stkvar2(x, x.addr, 0) && op_stkvar(cmd.ea, x.n)
return 1;
}
void out_insn(outctx_t &ctx) override
{
auto &cmd = ctx.insn;
//char buf[MAXSTR];
//init_output_buffer(buf, sizeof(buf));
hextracelog("out(%08x)\n", cmd.ea);
H.disasm(cmd.ea);
ctx.out_mnemonic();
std::string txt= H.text;
int io= 0;
for (std::string::iterator i= txt.begin() ; i != txt.end() ; ++i)
{
//dbgprintf("%p [ %p-%p ] : %02x\n", &*i, &*txt.begin(), &*txt.end(), *i);
switch(*i) {
case '$':
case '@':
if (io==6) {
errprintf("@%08x/%d: too many operands: '%s'\n", (uint32_t)cmd.ea, int(i-txt.begin()), txt.c_str());
return;
}
else {
ctx.out_one_operand(io++);
}
break;
default:
ctx.out_char(*i);
}
}
//term_output_buffer();
//dbgprintf("out:%s\n", buf);
//gl_comm = 1; // generate a user defined comment on this line
//MakeLine(buf, -1);
ctx.out_immchar_cmts();
ctx.flush_outbuf();
}
int out_operand(outctx_t &ctx, const op_t &op) override
{
auto &cmd = ctx.insn;
//dbgprintf("op %d: d:%x/f:%x/t:%x, value=%x, addr=%x\n", op.n, op.dtype, op.flags, op.type, op.value, op.addr);
if (op.type==o_near || op.type==o_mem) {
qstring symbuf;
ssize_t n= get_name_expr(&symbuf, cmd.ea+op.offb, op.n, op.addr, op.addr);
if (n>0)
ctx.out_line(symbuf.c_str());
else
ctx.out_value(op, OOF_ADDR);
return 1;
}
else {
ctx.out_value(op, OOFW_IMM);
return 1;
}
return -1;
//ctx.gen_printf(-1, "op");
}
// ----- output functions
void out_header(outctx_t &ctx) override
{
hextracelog("added header\n");
ctx.gen_cmt_line("Processor : %s", inf.procName);
ctx.gen_cmt_line("Target assembler: %s", ash.name);
ctx.gen_cmt_line("Byte sex : %s", inf_is_be() ? "Big endian" : "Little endian");
ctx.gen_cmt_line("");
ctx.gen_cmt_line("Hexagon processor module (c) 2017 GSMK");
ctx.gen_cmt_line("author: Willem Jan Hengeveld, [email protected]");
//if ( ash.header != NULL )
// for ( auto ptr=ash.header; *ptr != NULL; ptr++ )
// ctx.gen_printf(0,COLSTR("%s",SCOLOR_ASMDIR),*ptr);
}
void out_footer(outctx_t &ctx) override
{
hextracelog("added footer\n");
qstring name = get_colored_name(BADADDR, inf.start_ea);
ctx.gen_printf(-1,COLSTR("%s",SCOLOR_ASMDIR) " %s", ash.end, name.c_str());
}
int out_segstart(outctx_t &ctx, segment_t &seg) override
{
hextracelog("segment start(%08x)\n", seg.start_ea);
ctx.gen_cmt_line("segstart");
return 0;
}
int out_segend(outctx_t &ctx, segment_t &seg) override
{
hextracelog("segment end(%08x)\n", seg.start_ea);
ctx.gen_cmt_line("segend");
return 0;
}
int out_mnem(outctx_t &outctx) override
{
// the hexagon instruction consists only of operands.
return 1;
}
/* code&0xFFFF0000 == 0xA09D0000 - allocframe
* localsize = code&0x7FF
*
* subinsn: code&0x1E00 == 0x1C00
* localsize = (code>>4)&0x1F
*
* locate __save_rX_through_rY type functions:
* memd (r30 + #0xFFFFFFD0) = r27:26
*
A 011uuuuuudddd Rd = add(r29,#u6:2) Add immediate to stack pointer
L2 1110uuuuudddd Rd = memw(r29+#u5:2) Load word from stack
L2 11110uuuuuddd Rdd = memd(r29+#u5:3) Load pair from stack
S2 0100uuuuutttt memw(r29+#u5:2) = Rt Store word to stack
S2 0101ssssssttt memd(r29+#s6:3) = Rtt Store pair to stack
S2 1110uuuuu---- allocframe(#u5:3) Allocate stack frame
*/
int create_func_frame(func_t &pfn) override
{
return 0;
}
void newfile(const char *fname) override
{
// extra linefeeds to increase visibility of this message
msg("\n\n");
msg("Hexagon/QDSP6 processor module v1.1 (C) 2017 GSMK, author: Willem Jan Hengeveld, [email protected]\n");
msg("based on hexagon objdump from https://www.codeaurora.org/patches/quic/hexagon/4.0/Hexagon_Tools_source.tgz\n");
msg("\n");
}
virtual int is_sane_insn(const insn_t &cmd, int no_crefs) override
{
hextracelog("is_sane_insn(%08x, %d)\n", cmd.ea, no_crefs);
// zero not an insn
if (get_dword(cmd.ea)==0)
return 0;
// no more than 4 nops considered normal
for (int i=0 ; i<4 ; i++)
if (get_dword(cmd.ea+4*i)!=0x7f004000)
return 1;
return 0;
}
virtual int is_jump_func(func_t &pfn, ea_t *jump_target, ea_t *func_pointer) override
{
if (isjumpfunc(pfn.start_ea)) {
*jump_target= getjumpfunctarget(pfn.start_ea);
if (func_pointer)
*func_pointer= -1;
hextracelog("is_jump_func(%08x)-> yes: %08x\n", pfn.start_ea, *jump_target);
return 1;
}
else {
hextracelog("is_jump_func(%08x)-> no\n", pfn.start_ea);
}
return 0;
}
// only when PR_DELAYED is set in LPH.flags
virtual int is_basic_block_end(const insn_t &insn, bool call_insn_stops_block) override
{
hextracelog("is_basic_block_end(%d)\n", call_insn_stops_block);
if (::is_basic_block_end(get_dword(insn.ea)))
return 1;
return 0;
}
virtual int is_call_insn(const insn_t &insn) override
{
bool iscall= false;
if (is_immediate_call_insn(get_dword(insn.ea)))
iscall= true;
hextracelog("is_call_insn(%08x) -> %d\n", insn.ea, iscall);
if (iscall)
return 1;
return 0;
}
virtual int is_ret_insn(const insn_t &insn, bool strict) override
{
hextracelog("is_ret_insn(%08x, %d)\n", insn.ea, strict);
uint32_t opcode= get_dword(insn.ea);
if (is_return(opcode))
return 1;
return 0;
}
virtual int creating_segm(segment_t &seg) override
{
if (seg.type == SEG_CODE)
seg.align = saRelDble;
return 1;
}
};