TODO

ENHANCEMENTS needed:
====================

1)  Add "user grouping" to the visualizer

2)  Support multi-output drawing objects. Partially done.

3)  Provide back-annotation to Verilog and a Verilog viewer (with values?)

4)  Provide user-defined pretty printers for signal values. Partially done.



TODO to move Voss to ">=" Forte/ReFlect.
========================================

1) Add dynamic weakening to the STE engine (done, but not very efficient)

2) Add SMT solver (?)
   - Add a WSTE engine

3) Add fork primitive
   - Create a para_eval mechanism

4) Add GUI based debugger for fl.

5) Add named fields in type constructors + default values.

6) Add nlet functionality + defaults

7) Add timeout command.

8) Fix clet/cletrec for arguments that are reference variables.
    Need to copy the current value into new refvar and keep that new
    node as the cached argument.

9) Add clean_clet <fn>.

10) Add slettype (symbolic_lettype) consstruct to make types that can be
    used symbolically in pattern matching.

11) Add a default pretty printer for all userdefined datatypes.

12) Add an efficient GSTE engine.

13) Create a regression test environment based on Quick check.

DONE: 
=====

1)  Add non_lazy 
2)  Add then
3)  Add FSEQ
4)  Add printf/sprintf/fprintf functions
5)  Add fopen, fclose, fflush functions
6)  Add proper GUI front end (90% done)
7)  Add gen_catch
8)  Add tcl_eval and proper front end
9)  Add extapi functionality (simple version)
10) Add help system
11) Add bexpr
12) Add the DIR functions.
11) Add SAT solver
12) Add if-then-else binder
13) Add save_xyz and load_xyz for any monomorphic type xyz
14) Add dot drawing of g_ptr for debugging
15) Add the  'let foo x when (x > 12) = ... type of guarded definition.
16) Make load a proper function
17) Add support for external parsers
18) Add support for creating temporary files (in the VossII tmp directory)
19) Add open_overload
20) Add implicitly overloaded functions
21) Add large number of list functions
22) Add circuit visualization support
23) Add proper zero-delay RTL simulation
24) Create Verilog compiler
25) Add top-level val()
26) Replace def_list with a proper symbol table
27) Fix the tcl_eval and callbacks to handle very large strings (send directly
instead of going through an internal string representation).
28) Fix open_overload to allow polymorphic functions to be overloaded.  That would allow functions to be extended to pairs and lists etc!
29) Add definition of polymorphic type constructors (e.g., *a tree)
30)  Make the Show BDD colors and Show values (as well as the time) "sticky" for New fanin.
31)  Display the values of multi-dimensional variables as a list of values
32)  Add waveform viewer
33) Add bSTE
34) Add tables to fl
35) Add fanin_dfs, _bfs and fanout_... functionality. 
36) Fixed the save_fsm and load_fsm functions.