diff --git a/MCInst.c b/MCInst.c index e5c5e4fcce..d6f513ad2d 100644 --- a/MCInst.c +++ b/MCInst.c @@ -42,6 +42,7 @@ void MCInst_insert(MCInst *inst, int index, MCOperand *Op) cs_mem_free(Op); } +// do not free @Op void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) { int i; @@ -173,8 +174,7 @@ MCOperand *MCOperand_CreateReg(unsigned Reg) return op; } -/* -MCOperand *MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) +MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) { MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); @@ -183,7 +183,6 @@ MCOperand *MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) return op; } -*/ void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) { @@ -204,8 +203,7 @@ MCOperand *MCOperand_CreateImm(int64_t Val) return op; } -/* -MCOperand *MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) +MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val) { MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); @@ -214,7 +212,6 @@ MCOperand *MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) return op; } -*/ void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) { diff --git a/MCInst.h b/MCInst.h index 7ba0aecebb..e3371618d8 100644 --- a/MCInst.h +++ b/MCInst.h @@ -81,10 +81,18 @@ MCOperand *MCOperand_CreateImm(int64_t Val); MCOperand *MCOperand_CreateFPImm(double Val); +// create Reg operand in the next slot void MCOperand_CreateReg0(MCInst *inst, unsigned Reg); +// create Reg operand use the last-unused slot +MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg); + +// create Imm operand in the next slot void MCOperand_CreateImm0(MCInst *inst, int64_t Val); +// create Imm operand in the last-unused slot +MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val); + /// MCInst - Instances of this class represent a single low-level machine /// instruction. struct MCInst { @@ -107,8 +115,12 @@ void MCInst_Init(cs_struct *handle, MCInst *inst); void MCInst_clear(MCInst *inst); +// free operand after inserting void MCInst_insert(MCInst *inst, int index, MCOperand *Op); +// do not free operand after inserting +void MCInst_insert0(MCInst *inst, int index, MCOperand *Op); + void MCInst_setOpcode(MCInst *inst, unsigned Op); unsigned MCInst_getOpcode(const MCInst*); diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c index 8409e5cf60..5c341ba87e 100644 --- a/arch/ARM/ARMDisassembler.c +++ b/arch/ARM/ARMDisassembler.c @@ -408,11 +408,11 @@ static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, // AL predicate is not allowed on Thumb1 branches. if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(Val)); + MCOperand_CreateImm0(Inst, Val); if (Val == ARMCC_AL) { - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } else - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_CPSR)); + MCOperand_CreateReg0(Inst, ARM_CPSR); return MCDisassembler_Success; } @@ -556,13 +556,13 @@ static void AddThumb1SBit(MCInst *MI, bool InITBlock) if (i == MCInst_getNumOperands(MI)) break; if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) { if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i-1])) continue; - MCInst_insert(MI, i, MCOperand_CreateReg(InITBlock ? 0 : ARM_CPSR)); + MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); return; } } - //MI.insert(I, MCOperand_CreateReg(InITBlock ? 0 : ARM_CPSR)); - MCInst_insert(MI, i, MCOperand_CreateReg(InITBlock ? 0 : ARM_CPSR)); + //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); + MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); } // Most Thumb instructions don't have explicit predicates in the @@ -625,20 +625,20 @@ static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) for (i = 0; i < NumOps; ++i) { if (i == MCInst_getNumOperands(MI)) break; if (MCOperandInfo_isPredicate(&OpInfo[i])) { - MCInst_insert(MI, i, MCOperand_CreateImm(CC)); + MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); if (CC == ARMCC_AL) - MCInst_insert(MI, i+1, MCOperand_CreateReg(0)); + MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); else - MCInst_insert(MI, i+1, MCOperand_CreateReg(ARM_CPSR)); + MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); return S; } } - MCInst_insert(MI, i, MCOperand_CreateImm(CC)); + MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); if (CC == ARMCC_AL) - MCInst_insert(MI, i+1, MCOperand_CreateReg(0)); + MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); else - MCInst_insert(MI, i+1, MCOperand_CreateReg(ARM_CPSR)); + MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); return S; } @@ -902,7 +902,7 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, return MCDisassembler_Fail; Register = GPRDecoderTable[RegNo]; - MCInst_addOperand(Inst, MCOperand_CreateReg(Register)); + MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } @@ -925,7 +925,7 @@ static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, DecodeStatus S = MCDisassembler_Success; if (RegNo == 15) { - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_APSR_NZCV)); + MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); return MCDisassembler_Success; } @@ -959,7 +959,7 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, S = MCDisassembler_SoftFail; RegisterPair = GPRPairDecoderTable[RegNo/2]; - MCInst_addOperand(Inst, MCOperand_CreateReg(RegisterPair)); + MCOperand_CreateReg0(Inst, RegisterPair); return S; } @@ -990,7 +990,7 @@ static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, return MCDisassembler_Fail; } - MCInst_addOperand(Inst, MCOperand_CreateReg(Register)); + MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } @@ -1023,7 +1023,7 @@ static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, return MCDisassembler_Fail; Register = SPRDecoderTable[RegNo]; - MCInst_addOperand(Inst, MCOperand_CreateReg(Register)); + MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } @@ -1046,7 +1046,7 @@ static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, return MCDisassembler_Fail; Register = DPRDecoderTable[RegNo]; - MCInst_addOperand(Inst, MCOperand_CreateReg(Register)); + MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } @@ -1083,7 +1083,7 @@ static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, RegNo >>= 1; Register = QPRDecoderTable[RegNo]; - MCInst_addOperand(Inst, MCOperand_CreateReg(Register)); + MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } @@ -1104,7 +1104,7 @@ static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, return MCDisassembler_Fail; Register = DPairDecoderTable[RegNo]; - MCInst_addOperand(Inst, MCOperand_CreateReg(Register)); + MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } @@ -1127,7 +1127,7 @@ static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, return MCDisassembler_Fail; Register = DPairSpacedDecoderTable[RegNo]; - MCInst_addOperand(Inst, MCOperand_CreateReg(Register)); + MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } @@ -1135,9 +1135,9 @@ static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val) - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_CPSR)); + MCOperand_CreateReg0(Inst, ARM_CPSR); else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); return MCDisassembler_Success; } @@ -1147,7 +1147,7 @@ static DecodeStatus DecodeSOImmOperand(MCInst *Inst, unsigned Val, uint32_t imm = Val & 0xFF; uint32_t rot = (Val & 0xF00) >> 7; uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); - MCInst_addOperand(Inst, MCOperand_CreateImm(rot_imm)); + MCOperand_CreateImm0(Inst, rot_imm); return MCDisassembler_Success; } @@ -1185,7 +1185,7 @@ static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, Shift = ARM_AM_rrx; Op = Shift | (imm << 3); - MCInst_addOperand(Inst, MCOperand_CreateImm(Op)); + MCOperand_CreateImm0(Inst, Op); return S; } @@ -1222,7 +1222,7 @@ static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, break; } - MCInst_addOperand(Inst, MCOperand_CreateImm(Shift)); + MCOperand_CreateImm0(Inst, Shift); return S; } @@ -1343,7 +1343,7 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, if (msb != 31) msb_mask = (1U << (msb+1)) - 1; lsb_mask = (1U << lsb) - 1; - MCInst_addOperand(Inst, MCOperand_CreateImm(~(msb_mask ^ lsb_mask))); + MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); return S; } @@ -1399,8 +1399,8 @@ static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, break; } - MCInst_addOperand(Inst, MCOperand_CreateImm(coproc)); - MCInst_addOperand(Inst, MCOperand_CreateImm(CRd)); + MCOperand_CreateImm0(Inst, coproc); + MCOperand_CreateImm0(Inst, CRd); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; @@ -1438,7 +1438,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, case ARM_STC_PRE: case ARM_STCL_PRE: imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm); - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); break; case ARM_t2LDC2_POST: case ARM_t2LDC2L_POST: @@ -1461,7 +1461,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, default: // The 'option' variant doesn't encode 'U' in the immediate since // the immediate is unsigned [0,255]. - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); break; } @@ -1587,11 +1587,11 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, Opc = ARM_AM_rrx; imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); } else { - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); - MCInst_addOperand(Inst, MCOperand_CreateImm(tmp)); + MCOperand_CreateImm0(Inst, tmp); } if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) @@ -1639,7 +1639,7 @@ static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); else shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); - MCInst_addOperand(Inst, MCOperand_CreateImm(shift)); + MCOperand_CreateImm0(Inst, shift); return S; } @@ -1822,12 +1822,12 @@ static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; if (type) { - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); - MCInst_addOperand(Inst, MCOperand_CreateImm(U | (imm << 4) | Rm)); + MCOperand_CreateReg0(Inst, 0); + MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); } else { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(U)); + MCOperand_CreateImm0(Inst, U); } if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) @@ -1859,7 +1859,7 @@ static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, break; } - MCInst_addOperand(Inst, MCOperand_CreateImm(mode)); + MCOperand_CreateImm0(Inst, mode); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; @@ -1961,8 +1961,7 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, fieldFromInstruction_4(Insn, 20, 1) == 0)) return MCDisassembler_Fail; - MCInst_addOperand(Inst, - MCOperand_CreateImm(fieldFromInstruction_4(Insn, 0, 4))); + MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); return S; } @@ -2007,22 +2006,22 @@ static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, if (imod && M) { MCInst_setOpcode(Inst, ARM_CPS3p); - MCInst_addOperand(Inst, MCOperand_CreateImm(imod)); - MCInst_addOperand(Inst, MCOperand_CreateImm(iflags)); - MCInst_addOperand(Inst, MCOperand_CreateImm(mode)); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + MCOperand_CreateImm0(Inst, mode); } else if (imod && !M) { MCInst_setOpcode(Inst, ARM_CPS2p); - MCInst_addOperand(Inst, MCOperand_CreateImm(imod)); - MCInst_addOperand(Inst, MCOperand_CreateImm(iflags)); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); if (mode) S = MCDisassembler_SoftFail; } else if (!imod && M) { MCInst_setOpcode(Inst, ARM_CPS1p); - MCInst_addOperand(Inst, MCOperand_CreateImm(mode)); + MCOperand_CreateImm0(Inst, mode); if (iflags) S = MCDisassembler_SoftFail; } else { // imod == '00' && M == '0' --> UNPREDICTABLE MCInst_setOpcode(Inst, ARM_CPS1p); - MCInst_addOperand(Inst, MCOperand_CreateImm(mode)); + MCOperand_CreateImm0(Inst, mode); S = MCDisassembler_SoftFail; } @@ -2048,17 +2047,17 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, if (imod && M) { MCInst_setOpcode(Inst, ARM_t2CPS3p); - MCInst_addOperand(Inst, MCOperand_CreateImm(imod)); - MCInst_addOperand(Inst, MCOperand_CreateImm(iflags)); - MCInst_addOperand(Inst, MCOperand_CreateImm(mode)); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); + MCOperand_CreateImm0(Inst, mode); } else if (imod && !M) { MCInst_setOpcode(Inst, ARM_t2CPS2p); - MCInst_addOperand(Inst, MCOperand_CreateImm(imod)); - MCInst_addOperand(Inst, MCOperand_CreateImm(iflags)); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, iflags); if (mode) S = MCDisassembler_SoftFail; } else if (!imod && M) { MCInst_setOpcode(Inst, ARM_t2CPS1p); - MCInst_addOperand(Inst, MCOperand_CreateImm(mode)); + MCOperand_CreateImm0(Inst, mode); if (iflags) S = MCDisassembler_SoftFail; } else { // imod == '00' && M == '0' --> this is a HINT instruction @@ -2066,7 +2065,7 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, // HINT are defined only for immediate in [0..4] if(imm > 4) return MCDisassembler_Fail; MCInst_setOpcode(Inst, ARM_t2HINT); - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); } return S; @@ -2091,7 +2090,7 @@ static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); return S; } @@ -2115,7 +2114,7 @@ static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; @@ -2166,7 +2165,7 @@ static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, if (!add) imm *= (unsigned int)-1; if (imm == 0 && !add) imm = (unsigned int)INT32_MIN; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); //if (Rn == 15) // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); @@ -2186,9 +2185,9 @@ static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, return MCDisassembler_Fail; if (U) - MCInst_addOperand(Inst, MCOperand_CreateImm(ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm))); + MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)); else - MCInst_addOperand(Inst, MCOperand_CreateImm(ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm))); + MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)); return S; } @@ -2219,7 +2218,7 @@ static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; int imm32 = SignExtend32(tmp << 1, 25); - MCInst_addOperand(Inst, MCOperand_CreateImm(imm32)); + MCOperand_CreateImm0(Inst, imm32); return Status; } @@ -2235,11 +2234,11 @@ static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, if (pred == 0xF) { MCInst_setOpcode(Inst, ARM_BLXi); imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; - MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(imm, 26))); + MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); return S; } - MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(imm, 26))); + MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; @@ -2258,9 +2257,9 @@ static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; if (!align) - MCInst_addOperand(Inst, MCOperand_CreateImm(0)); + MCOperand_CreateImm0(Inst, 0); else - MCInst_addOperand(Inst, MCOperand_CreateImm(4 << align)); + MCOperand_CreateImm0(Inst, 4 << align); return S; } @@ -2455,7 +2454,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, case ARM_VLD2b8wb_register: case ARM_VLD2b16wb_register: case ARM_VLD2b32wb_register: - MCInst_addOperand(Inst, MCOperand_CreateImm(0)); + MCOperand_CreateImm0(Inst, 0); break; case ARM_VLD3d8_UPD: case ARM_VLD3d16_UPD: @@ -2490,7 +2489,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, // // The fixed offset encodes as Rm == 0xd, so we check for that. if (Rm == 0xd) { - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); break; } // Fall through to handle the register offset variant. @@ -2665,7 +2664,7 @@ static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, case ARM_VST2b32wb_register: if (Rm == 0xF) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(0)); + MCOperand_CreateImm0(Inst, 0); break; case ARM_VST3d8_UPD: case ARM_VST3d16_UPD: @@ -2694,7 +2693,7 @@ static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, switch (MCInst_getOpcode(Inst)) { default: if (Rm == 0xD) - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); else if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; @@ -2907,7 +2906,7 @@ static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); // The fixed offset post-increment encodes Rm == 0xd. The no-writeback // variant encodes Rm == 0xf. Anything else is a register offset post- @@ -2954,11 +2953,11 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, } if (Rm != 0xF) - MCInst_addOperand(Inst, MCOperand_CreateImm(0)); + MCOperand_CreateImm0(Inst, 0); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xD && Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) @@ -2992,10 +2991,10 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(0)); + MCOperand_CreateImm0(Inst, 0); if (Rm == 0xD) - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); else if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; @@ -3045,10 +3044,10 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm == 0xD) - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); else if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; @@ -3079,7 +3078,7 @@ static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; } - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); switch (MCInst_getOpcode(Inst)) { case ARM_VORRiv4i16: @@ -3118,7 +3117,7 @@ static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(8 << size)); + MCOperand_CreateImm0(Inst, 8 << size); return S; } @@ -3126,28 +3125,28 @@ static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateImm(8 - Val)); + MCOperand_CreateImm0(Inst, 8 - Val); return MCDisassembler_Success; } static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateImm(16 - Val)); + MCOperand_CreateImm0(Inst, 16 - Val); return MCDisassembler_Success; } static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateImm(32 - Val)); + MCOperand_CreateImm0(Inst, 32 - Val); return MCDisassembler_Success; } static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateImm(64 - Val)); + MCOperand_CreateImm0(Inst, 64 - Val); return MCDisassembler_Success; } @@ -3205,32 +3204,32 @@ static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, case ARM_tADR: break; // tADR does not explicitly represent the PC as an operand. case ARM_tADDrSPi: - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_SP)); + MCOperand_CreateReg0(Inst, ARM_SP); break; } - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); return S; } static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Val << 1, 12))); + MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); return MCDisassembler_Success; } static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Val, 21))); + MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); return MCDisassembler_Success; } static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateImm(Val << 1)); + MCOperand_CreateImm0(Inst, Val << 1); return MCDisassembler_Success; } @@ -3260,7 +3259,7 @@ static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); return S; } @@ -3270,7 +3269,7 @@ static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, { unsigned imm = Val << 2; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); return MCDisassembler_Success; @@ -3279,8 +3278,8 @@ static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_SP)); - MCInst_addOperand(Inst, MCOperand_CreateImm(Val)); + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } @@ -3309,7 +3308,7 @@ static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, return MCDisassembler_Fail; if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); return S; } @@ -3598,7 +3597,7 @@ static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, else imm = -imm; } - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); return S; } @@ -3607,12 +3606,12 @@ static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val == 0) - MCInst_addOperand(Inst, MCOperand_CreateImm(INT32_MIN)); + MCOperand_CreateImm0(Inst, INT32_MIN); else { int imm = Val & 0xFF; if (!(Val & 0x100)) imm *= -1; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm * 4)); + MCOperand_CreateImm0(Inst, imm * 4); } return MCDisassembler_Success; @@ -3645,7 +3644,7 @@ static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); return S; } @@ -3658,7 +3657,7 @@ static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, imm = INT32_MIN; else if (!(Val & 0x100)) imm *= -1; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); return MCDisassembler_Success; } @@ -3793,7 +3792,7 @@ static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); return S; } @@ -3803,9 +3802,9 @@ static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, { unsigned imm = fieldFromInstruction_2(Insn, 0, 7); - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_SP)); - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_SP)); - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateImm0(Inst, imm); return MCDisassembler_Success; } @@ -3821,14 +3820,14 @@ static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_SP)); + MCOperand_CreateReg0(Inst, ARM_SP); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler_Fail; } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_SP)); - MCInst_addOperand(Inst, MCOperand_CreateReg(ARM_SP)); + MCOperand_CreateReg0(Inst, ARM_SP); + MCOperand_CreateReg0(Inst, ARM_SP); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } @@ -3842,8 +3841,8 @@ static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; unsigned flags = fieldFromInstruction_2(Insn, 0, 3); - MCInst_addOperand(Inst, MCOperand_CreateImm(imod)); - MCInst_addOperand(Inst, MCOperand_CreateImm(flags)); + MCOperand_CreateImm0(Inst, imod); + MCOperand_CreateImm0(Inst, flags); return MCDisassembler_Success; } @@ -3857,7 +3856,7 @@ static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(add)); + MCOperand_CreateImm0(Inst, add); return S; } @@ -3880,7 +3879,7 @@ static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); int imm32 = SignExtend32(tmp << 1, 25); - MCInst_addOperand(Inst, MCOperand_CreateImm(imm32)); + MCOperand_CreateImm0(Inst, imm32); return MCDisassembler_Success; } @@ -3890,7 +3889,7 @@ static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, if (Val == 0xA || Val == 0xB) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(Val)); + MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } @@ -3963,24 +3962,23 @@ static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, unsigned imm = fieldFromInstruction_4(Val, 0, 8); switch (byte) { case 0: - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); break; case 1: - MCInst_addOperand(Inst, MCOperand_CreateImm((imm << 16) | imm)); + MCOperand_CreateImm0(Inst, (imm << 16) | imm); break; case 2: - MCInst_addOperand(Inst, MCOperand_CreateImm((imm << 24) | (imm << 8))); + MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); break; case 3: - MCInst_addOperand(Inst, MCOperand_CreateImm((imm << 24) | (imm << 16) | - (imm << 8) | imm)); + MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); break; } } else { unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; unsigned rot = fieldFromInstruction_4(Val, 7, 5); unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); - MCInst_addOperand(Inst, MCOperand_CreateImm(imm)); + MCOperand_CreateImm0(Inst, imm); } return MCDisassembler_Success; @@ -3989,7 +3987,7 @@ static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { - MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Val << 1, 9))); + MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); return MCDisassembler_Success; } @@ -4011,7 +4009,7 @@ static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); int imm32 = SignExtend32(tmp << 1, 25); - MCInst_addOperand(Inst, MCOperand_CreateImm(imm32)); + MCOperand_CreateImm0(Inst, imm32); return MCDisassembler_Success; } @@ -4021,7 +4019,7 @@ static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, if (Val & ~0xf) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(Val)); + MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } @@ -4031,7 +4029,7 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, if (Val & ~0xf) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(Val)); + MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } @@ -4039,7 +4037,7 @@ static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (!Val) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(Val)); + MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } @@ -4247,18 +4245,18 @@ static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(index)); + MCOperand_CreateImm0(Inst, index); return S; } @@ -4311,18 +4309,18 @@ static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(index)); + MCOperand_CreateImm0(Inst, index); return S; } @@ -4374,20 +4372,20 @@ static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(index)); + MCOperand_CreateImm0(Inst, index); return S; } @@ -4435,20 +4433,20 @@ static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(index)); + MCOperand_CreateImm0(Inst, index); return S; } @@ -4501,13 +4499,13 @@ static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) @@ -4516,7 +4514,7 @@ static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(index)); + MCOperand_CreateImm0(Inst, index); return S; } @@ -4562,13 +4560,13 @@ static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) @@ -4577,7 +4575,7 @@ static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(index)); + MCOperand_CreateImm0(Inst, index); return S; } @@ -4639,13 +4637,13 @@ static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) @@ -4656,7 +4654,7 @@ static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(index)); + MCOperand_CreateImm0(Inst, index); return S; } @@ -4709,13 +4707,13 @@ static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(align)); + MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else - MCInst_addOperand(Inst, MCOperand_CreateReg(0)); + MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) @@ -4726,7 +4724,7 @@ static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(index)); + MCOperand_CreateImm0(Inst, index); return S; } @@ -4800,8 +4798,8 @@ static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, if (mask == 0x0) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(pred)); - MCInst_addOperand(Inst, MCOperand_CreateImm(mask)); + MCOperand_CreateImm0(Inst, pred); + MCOperand_CreateImm0(Inst, mask); return S; } @@ -4889,7 +4887,7 @@ static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; Val |= sign1 << 12; - MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Val, 13))); + MCOperand_CreateImm0(Inst, SignExtend32(Val, 13)); return MCDisassembler_Success; } @@ -4901,7 +4899,7 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, // Shift of "asr #32" is not allowed in Thumb2 mode. if (Val == 0x20) S = MCDisassembler_SoftFail; - MCInst_addOperand(Inst, MCOperand_CreateImm(Val)); + MCOperand_CreateImm0(Inst, Val); return S; } @@ -4961,7 +4959,7 @@ static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(64 - imm)); + MCOperand_CreateImm0(Inst, 64 - imm); return S; } @@ -4992,7 +4990,7 @@ static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(64 - imm)); + MCOperand_CreateImm0(Inst, 64 - imm); return S; } @@ -5043,13 +5041,13 @@ static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val, if (Rt == Rt2) S = MCDisassembler_SoftFail; - MCInst_addOperand(Inst, MCOperand_CreateImm(cop)); - MCInst_addOperand(Inst, MCOperand_CreateImm(opc1)); + MCOperand_CreateImm0(Inst, cop); + MCOperand_CreateImm0(Inst, opc1); if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler_Fail; - MCInst_addOperand(Inst, MCOperand_CreateImm(CRm)); + MCOperand_CreateImm0(Inst, CRm); return S; }