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ISSIE has an extensive library of schematic components available in the 'Catalogue' menu. Components include low-level gates, flipflops, and multiplexers, as well as larger blocks: RAMs, ROMs, configurable n-bit registers, counters and adders. Viewer components are used to (optionally) view simulation waveforms of nodes on sub-sheets. Wire label components allow any number of nodes on one design sheet to be connected without visible wires. More complex functions can quickly be constructed as sub-sheets and then used as a 'custom component' (found under 'THIS PROJECT'). Custom components can have shape and I/O positions altered at any time via an intuitive and fast drag and drop GUI |
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Hierarcical Design with Schematic Components |
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ISSIE schematic component ports are connected using drag-and-drop: each connection represents a wire or bus. ISSIE has two methods of routing wires: <b>auto-routing</b> and <b>manual-routing</b>. <br><br> Wires will all start out as auto-routed, which means that the wire’s path is created automatically by the program. This path will update when moving any connected components. ISSIE also allows for manual routing, where the user may manipulate segments of the wire as desired to make the circuit more readable. Much care has been put into a user interface for routing which <i>just works</i> quickly with no learning curve. |
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The ISSIE canvas is fully customisable to allow the creation of readable and good-looking schematics. <b>Specifically:</b> <br><br> (a) Rotate, flip and Move all symbols <br> (b) Change and move around the symbols' labels <br> (c) Manually route wires as you like <br> (d) Auto-align elements <br> (e) Select the wire type you desire (radiussed, jump or modern wires) |
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Canvas Customization |
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ISSIE allows users to create combinational components by defining their logic in Verilog. Such component can be used as a Custom Component in all designs. <br> <br> For more information see the <a href="/issie/verilog-comp/">Verilog Component page</a> |
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Step Simulation allows the user to 'step' or cycle through each clock tick, and view the current design sheet's Output and Viewer component information. It also allows users to view how the state changes in stateful components such as RAM. |
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Waveform Simulation allows the user to see the values in each selected set of connected wires (net) over time as a waveform. The waveform simulator uses a drag-and-drop GUI to delete or reorder waveforms, and a separate project explorer window to add them. Hovering on a waveform name highlights its component and all connected busses on its design sheet. Any design sheet may be viewed or edited and the simulation refreshed to see changes immediately. The values in the waveform simulator can be viewed in various formats: binary, hexadecimal, unsigned decimal and signed decimal. The Waveform Simulator uses a draggable sidebar to partition screen space dynamically between waveforms and circuit. <br><br>
Waveform Simulation also allows for the simulation and contents viewing of memory components such as RAM. |
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Waveform Simulation |
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ISSIE allows users to view the truth table for a selected circuit of combinational logic. This can be either the full truth table or a reduced one by denoting all Don't Cares with 'X's. <br> <br> Furthermore, users can set any number of inputs as algebra. The resultant truth table will show outputs as a function of the inputs. |
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Users may convert their ISSIE schematic design into a Verilog file using the "Write design as Verilog" option found in the header bar of the application. This allows great flexibility as ISSIE designs may be used in more complex design tools and other programs that use Verilog; allowing ISSIE to be used as a top-level design that can be further developed if needed. Verilog output for simulation or synthesis is documented as part of the Verilog write process, this includes links to a <a href=" http://bygone.clairexen.net/yosys/download.html">YoSys</a> workflow for synthesis on FPGAs. Imperial College users can download a pre-installed VM for this workflow, the VHDL output is standalone and should work with other synthesis methods |
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ISSIE allows users to directly edit the contents of Memory components, for more versatility and ease of use. Memory contents can also be exported and imported via .ram files |
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