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Commits on Mar 9, 2012

• Add support for r600 (AMD GPUs HD2XXX - HD6XXX) target triplet.

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  asl

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• Factor out the analysis of addition and subtraction in ComputeMaskedBits. Reuse

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  nlewycky

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• [llvm.py] Initial skeleton for Python LLVM bindings

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  indygreg

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• misched: handle scheduling region boundaries nicely.

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• Use uint16_t to store opcodes in static tables in X86 backend.

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  topperc

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• Fix undefined behavior in the Mips backend.

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  Ahmed Charles

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• misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.

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• misched comments

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• revert 152356: verify misched changes using -misched=shuffle.

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• Fix a silly restriction on the fast-path for hash_combine_range. This

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  chandlerc

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• Undo a previous restriction on the inline cost calculation which Nick

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  chandlerc

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• Fix a regression from r147481.

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  Chad Rosier

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• misched: allow the default scheduler to be one chosen by the target.

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  atrick

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• Added TargetPassConfig::enablePass

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• Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().

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  Evan Cheng

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Commits on Mar 8, 2012

• Silence unused function warning when graphviz is not available.

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  d0k

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• Remove the no longer existent psp triple from a test.

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  d0k

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• Have llvm-mc --version print the list of registered targets like llc does.

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  CunningBaldrick

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• Revert commit 152300 (ddunbar) since it still seems to be breaking

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• Use uint16_t to store instruction implicit uses and defs. Reduces static data.

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  topperc

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• [ADT] Change the trivial FoldingSetNodeID::Add* methods to be inline, reapplied

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  ddunbar

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• Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:

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  kaomoneus

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• Re-commit r152202 hopefully fixing the MSVC linker error.

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  topperc

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• Revert r152288, "[ADT] Change the trivial FoldingSetNodeID::Add* methods to be

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• Test case for r152280, r152285 and r152290.

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  ahatanak

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• Invoke setTargetDAGCombine for SELECT.

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  ahatanak

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• [ADT] Change the trivial FoldingSetNodeID::Add* methods to be inline.

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  ddunbar

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• Swap the operands of a select node if the false (the second) operand is 0.

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  ahatanak

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• Rotate two of the functions used to count bonuses for the inline cost

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  chandlerc

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• Set minimum function alignment to 3 if target is Mips64.

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  ahatanak

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• This patch eliminates redundant instructions that produce 0.

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  ahatanak

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• misched interface: Expose the MachineScheduler pass.

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  atrick

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• ARM don't use MCRelaxAll, as it's not safe on ARM.

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  Jim Grosbach

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Commits on Mar 7, 2012

• Improved support in RuntimeDyldMachO for generating

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  scallanan

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• Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.

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