-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy patha2gx_create.tcl
152 lines (128 loc) · 6.48 KB
/
a2gx_create.tcl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
#
# Copyright (C) 2013 Vlad Lazarenko <[email protected]>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
set PROJECT_NAME $env(PROJECT_NAME)
project_new ${PROJECT_NAME} -overwrite
set_global_assignment -name TOP_LEVEL_ENTITY ${PROJECT_NAME}_top
set_global_assignment -name FAMILY "Arria II GX"
set_global_assignment -name DEVICE EP2AGX260FF35I3
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "0"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP "85"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SMART_RECOMPILE ON
### Setup timing constraints.
set_global_assignment -name SDC_FILE ${PROJECT_NAME}.sdc
### Source files..
set RTL_FILES $env(RTL_FILES)
foreach f ${RTL_FILES} {
set_global_assignment -name VERILOG_FILE ${f}
}
### QIP files...
set QIP_FILES $env(QIP_FILES)
foreach f ${QIP_FILES} {
set_global_assignment -name QIP_FILE ${f}
}
### PIN assignments ###
# 100 MHz Clock
set_location_assignment PIN_AJ19 -to clk_top_100_p
#set_location_assignment PIN_AK19 -to clk_top_100_n
set_instance_assignment -name IO_STANDARD LVDS -to clk_top_100_p
# 125 MHz Clock
set_location_assignment PIN_F18 -to clk_top_125_p
set_instance_assignment -name IO_STANDARD LVDS -to clk_top_125_p
# Reset button (PB1, active low)
set_location_assignment PIN_AL7 -to global_reset_n
set_instance_assignment -name IO_STANDARD "1.8 V" -to global_reset_n
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to global_reset_n
# PCIe
set_location_assignment PIN_AE29 -to pcie_refclk
set_location_assignment PIN_N1 -to pcie_rstn
set_location_assignment PIN_AN33 -to pcie_rx_in0
set_location_assignment PIN_AL33 -to pcie_rx_in1
set_location_assignment PIN_AJ33 -to pcie_rx_in2
set_location_assignment PIN_AG33 -to pcie_rx_in3
set_location_assignment PIN_AM31 -to pcie_tx_out0
set_location_assignment PIN_AK31 -to pcie_tx_out1
set_location_assignment PIN_AH31 -to pcie_tx_out2
set_location_assignment PIN_AF31 -to pcie_tx_out3
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_rstn
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_in0
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_in1
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_in2
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_in3
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_out0
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_out1
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_out2
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_out3
# PCIe LEDs
set_location_assignment PIN_E1 -to pcie_led[0]
set_location_assignment PIN_R9 -to pcie_led[1]
set_location_assignment PIN_H3 -to pcie_led[2]
set_location_assignment PIN_D2 -to pcie_led[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_led
# Ethernet RGMII
set_location_assignment PIN_D25 -to eth_tx_clk
set_location_assignment PIN_V6 -to eth_rx_clk
set_location_assignment PIN_D17 -to eth_rx_ctrl
set_location_assignment PIN_G20 -to eth_tx_ctrl
set_location_assignment PIN_M20 -to eth_reset_n
set_location_assignment PIN_E21 -to eth_rgmii_in[0]
set_location_assignment PIN_E24 -to eth_rgmii_in[1]
set_location_assignment PIN_E22 -to eth_rgmii_in[2]
set_location_assignment PIN_F24 -to eth_rgmii_in[3]
set_location_assignment PIN_J20 -to eth_rgmii_out[0]
set_location_assignment PIN_C25 -to eth_rgmii_out[1]
set_location_assignment PIN_G22 -to eth_rgmii_out[2]
set_location_assignment PIN_G21 -to eth_rgmii_out[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_ctrl
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_ctrl
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rgmii_in
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_reset_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rgmii_out
# Ethernet MDIO
set_location_assignment PIN_K20 -to eth_mdc
set_location_assignment PIN_N20 -to eth_mdio
project_close