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kwboot.c
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kwboot.c
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/*
* Boot a Marvell SoC, with Xmodem over UART0.
* supports Kirkwood, Dove, Avanta, Armada 370, Armada XP, Armada 375,
* Armada 38x and Armada 39x.
*
* (c) 2012 Daniel Stodden <[email protected]>
* (c) 2021 Pali Rohár <[email protected]>
* (c) 2021 Marek Behún <[email protected]>
*
* References:
* - "88F6180, 88F6190, 88F6192, and 88F6281: Integrated Controller: Functional
* Specifications" December 2, 2008. Chapter 24.2 "BootROM Firmware".
* https://web.archive.org/web/20130730091033/https://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
* - "88AP510: High-Performance SoC with Integrated CPU, 2D/3D Graphics
* Processor, and High-Definition Video Decoder: Functional Specifications"
* August 3, 2011. Chapter 5 "BootROM Firmware"
* https://web.archive.org/web/20120130172443/https://www.marvell.com/application-processors/armada-500/assets/Armada-510-Functional-Spec.pdf
* - "88F6665, 88F6660, 88F6658, 88F6655, 88F6655F, 88F6650, 88F6650F, 88F6610,
* and 88F6610F Avanta LP Family Integrated Single/Dual CPU Ecosystem for
* Gateway (GW), Home Gateway Unit (HGU), and Single Family Unit (SFU)
* Functional Specifications" Doc. No. MV-S108952-00, Rev. A. November 7, 2013.
* Chapter 7 "Boot Flow"
* CONFIDENTIAL, no public documentation available
* - "88F6710, 88F6707, and 88F6W11: ARMADA(R) 370 SoC: Functional Specifications"
* May 26, 2014. Chapter 6 "BootROM Firmware".
* https://web.archive.org/web/20140617183701/https://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-FunctionalSpec-datasheet.pdf
* - "MV78230, MV78260, and MV78460: ARMADA(R) XP Family of Highly Integrated
* Multi-Core ARMv7 Based SoC Processors: Functional Specifications"
* May 29, 2014. Chapter 6 "BootROM Firmware".
* https://web.archive.org/web/20180829171131/https://www.marvell.com/embedded-processors/armada-xp/assets/ARMADA-XP-Functional-SpecDatasheet.pdf
* - "BobCat2 Control and Management Subsystem Functional Specifications"
* Doc. No. MV-S109400-00, Rev. A. December 4, 2014.
* Chapter 1.6 BootROM Firmware
* CONFIDENTIAL, no public documentation available
* - "AlleyCat3 and PONCat3 Highly Integrated 1/10 Gigabit Ethernet Switch
* Control and Management Subsystem: Functional Specifications"
* Doc. No. MV-S109693-00, Rev. A. May 20, 2014.
* Chapter 1.6 BootROM Firmware
* CONFIDENTIAL, no public documentation available
* - "ARMADA(R) 375 Value-Performance Dual Core CPU System on Chip: Functional
* Specifications" Doc. No. MV-S109377-00, Rev. A. September 18, 2013.
* Chapter 7 "Boot Sequence"
* CONFIDENTIAL, no public documentation available
* - "88F6810, 88F6811, 88F6821, 88F6W21, 88F6820, and 88F6828: ARMADA(R) 38x
* Family High-Performance Single/Dual CPU System on Chip: Functional
* Specifications" Doc. No. MV-S109094-00, Rev. C. August 2, 2015.
* Chapter 7 "Boot Flow"
* CONFIDENTIAL, no public documentation available
* - "88F6920, 88F6925 and 88F6928: ARMADA(R) 39x High-Performance Dual Core CPU
* System on Chip Functional Specifications" Doc. No. MV-S109896-00, Rev. B.
* December 22, 2015. Chapter 7 "Boot Flow"
* CONFIDENTIAL, no public documentation available
* - "Marvell boot image parser", Marvell U-Boot 2013.01, version 18.06. September 17, 2015.
* https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2013.01-armada-18.06/tools/marvell/doimage_mv/hdrparser.c
* - "Marvell doimage Tool", Marvell U-Boot 2013.01, version 18.06. August 30, 2015.
* https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2013.01-armada-18.06/tools/marvell/doimage_mv/doimage.c
*
* Storage location / offset of different image types:
* - IBR_HDR_SPI_ID (0x5A):
* SPI image can be stored at any 2 MB aligned offset in the first 16 MB of
* SPI-NOR or parallel-NOR. Despite the type name it really can be stored on
* parallel-NOR and cannot be stored on other SPI devices, like SPI-NAND.
* So it should have been named NOR image, not SPI image. This image type
* supports XIP - Execute In Place directly from NOR memory. Destination
* address of the XIP image is set to 0xFFFFFFFF and execute address to the
* absolute offset in bytes from the beginning of NOR memory.
*
* - IBR_HDR_NAND_ID (0x8B):
* NAND image can be stored either at any 2 MB aligned offset in the first
* 16 MB of SPI-NAND or at any blocksize aligned offset in the first 64 MB
* of parallel-NAND.
*
* - IBR_HDR_PEX_ID (0x9C):
* PEX image is used for booting from PCI Express device. Source address
* stored in image is ignored by BootROM. It is not the BootROM who parses
* or loads data part of the PEX image. BootROM just configures SoC to the
* PCIe endpoint mode and let the PCIe device on the other end of the PCIe
* link (which must be in Root Complex mode) to load kwbimage into SoC's
* memory and tell BootROM physical address.
*
* - IBR_HDR_UART_ID (0x69):
* UART image can be transfered via xmodem protocol over first UART.
* Unlike all other image types, header size stored in the image must be
* multiply of the 128 bytes (for all other image types it can be any size)
* and data part of the image does not have to contain 32-bit checksum
* (all other image types must have valid 32-bit checksum in its data part).
* And data size stored in the image is ignored. A38x BootROM determinates
* size of the data part implicitly by the end of the xmodem transfer.
* A38x BootROM has a bug which cause that BootROM loads data part of UART
* image into RAM target address increased by one byte when source address
* and header size stored in the image header are not same. So UART image
* should be constructed in a way that there is no gap between header and
* data part.
*
* - IBR_HDR_I2C_ID (0x4D):
* It is unknown for what kind of storage is used this image. It is not
* specified in any document from References section.
*
* - IBR_HDR_SATA_ID (0x78):
* SATA image can be stored at sector 1 (after the MBR table), sector 34
* (after the GPT table) or at any next sector which is aligned to 2 MB and
* is in the first 16 MB of SATA disk. Note that source address in SATA image
* is stored in sector unit and not in bytes like for any other images.
* Unfortunately sector size is disk specific, in most cases it is 512 bytes
* but there are also Native 4K SATA disks which have 4096 bytes long sectors.
*
* - IBR_HDR_SDIO_ID (0xAE):
* SDIO image can be stored on different medias:
* - SD(SC) card
* - SDHC/SDXC card
* - eMMC HW boot partition
* - eMMC user data partition / MMC card
* It cannot be stored on SDIO card despite the image name.
*
* For SD(SC)/SDHC/SDXC cards, image can be stored at the same locations as
* the SATA image (sector 1, sector 34 or any 2 MB aligned sector) but within
* the first 64 MB. SDHC and SDXC cards have fixed 512 bytes long sector size.
* Old SD(SC) cards unfortunately can have also different sector sizes, mostly
* 1024 bytes long sector sizes and also can be changed at runtime.
*
* For MMC-compatible devices, image can be stored at offset 0 or at offset
* 2 MB. If MMC device supports HW boot partitions then image must be stored
* on the HW partition as is configured in the EXT_CSC register (it can be
* either boot or user data).
*
* Note that source address for SDIO image is stored in byte unit, like for
* any other images (except SATA). Marvell Functional Specifications for
* A38x and A39x SoCs say that source address is in sector units, but this
* is purely incorrect information. A385 BootROM really expects source address
* for SDIO images in bytes and also Marvell tools generate SDIO image with
* source address in byte units.
*/
#include "kwbimage.h"
#include "mkimage.h"
#include "version.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
#include <image.h>
#include <libgen.h>
#include <fcntl.h>
#include <errno.h>
#include <unistd.h>
#include <stdint.h>
#include <time.h>
#include <sys/stat.h>
#include <pthread.h>
#ifdef __linux__
#include "termios_linux.h"
#else
#include <termios.h>
#endif
/*
* These functions are in <term.h> header file, but this header file conflicts
* with "termios_linux.h" header file. So declare these functions manually.
*/
extern int setupterm(const char *, int, int *);
extern char *tigetstr(const char *);
/*
* Marvell BootROM UART Sensing
*/
static unsigned char kwboot_msg_boot[] = {
0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
};
static unsigned char kwboot_msg_debug[] = {
0xDD, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
};
/* Defines known to work on Kirkwood */
#define KWBOOT_MSG_RSP_TIMEO 50 /* ms */
/* Defines known to work on Armada XP */
#define KWBOOT_MSG_RSP_TIMEO_AXP 10 /* ms */
/*
* Xmodem Transfers
*/
#define SOH 1 /* sender start of block header */
#define EOT 4 /* sender end of block transfer */
#define ACK 6 /* target block ack */
#define NAK 21 /* target block negative ack */
#define KWBOOT_XM_BLKSZ 128 /* xmodem block size */
struct kwboot_block {
uint8_t soh;
uint8_t pnum;
uint8_t _pnum;
uint8_t data[KWBOOT_XM_BLKSZ];
uint8_t csum;
} __packed;
#define KWBOOT_BLK_RSP_TIMEO 2000 /* ms */
#define KWBOOT_HDR_RSP_TIMEO 10000 /* ms */
/* ARM code to change baudrate */
static unsigned char kwboot_baud_code[] = {
/* ; #define UART_BASE 0xd0012000 */
/* ; #define DLL 0x00 */
/* ; #define DLH 0x04 */
/* ; #define LCR 0x0c */
/* ; #define DLAB 0x80 */
/* ; #define LSR 0x14 */
/* ; #define TEMT 0x40 */
/* ; #define DIV_ROUND(a, b) ((a + b/2) / b) */
/* ; */
/* ; u32 set_baudrate(u32 old_b, u32 new_b) { */
/* ; while */
/* ; (!(readl(UART_BASE + LSR) & TEMT)); */
/* ; u32 lcr = readl(UART_BASE + LCR); */
/* ; writel(UART_BASE + LCR, lcr | DLAB); */
/* ; u8 old_dll = readl(UART_BASE + DLL); */
/* ; u8 old_dlh = readl(UART_BASE + DLH); */
/* ; u16 old_dl = old_dll | (old_dlh << 8); */
/* ; u32 clk = old_b * old_dl; */
/* ; u16 new_dl = DIV_ROUND(clk, new_b); */
/* ; u8 new_dll = new_dl & 0xff; */
/* ; u8 new_dlh = (new_dl >> 8) & 0xff; */
/* ; writel(UART_BASE + DLL, new_dll); */
/* ; writel(UART_BASE + DLH, new_dlh); */
/* ; writel(UART_BASE + LCR, lcr & ~DLAB); */
/* ; msleep(5); */
/* ; return 0; */
/* ; } */
/* ; r0 = UART_BASE */
0x0d, 0x02, 0xa0, 0xe3, /* mov r0, #0xd0000000 */
0x12, 0x0a, 0x80, 0xe3, /* orr r0, r0, #0x12000 */
/* ; Wait until Transmitter FIFO is Empty */
/* .Lloop_txempty: */
/* ; r1 = UART_BASE[LSR] & TEMT */
0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */
0x40, 0x00, 0x11, 0xe3, /* tst r1, #0x40 */
0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_txempty */
/* ; Set Divisor Latch Access Bit */
/* ; UART_BASE[LCR] |= DLAB */
0x0c, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x0c] */
0x80, 0x10, 0x81, 0xe3, /* orr r1, r1, #0x80 */
0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */
/* ; Read current Divisor Latch */
/* ; r1 = UART_BASE[DLH]<<8 | UART_BASE[DLL] */
0x00, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x00] */
0xff, 0x10, 0x01, 0xe2, /* and r1, r1, #0xff */
0x01, 0x20, 0xa0, 0xe1, /* mov r2, r1 */
0x04, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x04] */
0xff, 0x10, 0x01, 0xe2, /* and r1, r1, #0xff */
0x41, 0x14, 0xa0, 0xe1, /* asr r1, r1, #8 */
0x02, 0x10, 0x81, 0xe1, /* orr r1, r1, r2 */
/* ; Read old baudrate value */
/* ; r2 = old_baudrate */
0x74, 0x20, 0x9f, 0xe5, /* ldr r2, old_baudrate */
/* ; Calculate base clock */
/* ; r1 = r2 * r1 */
0x92, 0x01, 0x01, 0xe0, /* mul r1, r2, r1 */
/* ; Read new baudrate value */
/* ; r2 = new_baudrate */
0x70, 0x20, 0x9f, 0xe5, /* ldr r2, new_baudrate */
/* ; Calculate new Divisor Latch */
/* ; r1 = DIV_ROUND(r1, r2) = */
/* ; = (r1 + r2/2) / r2 */
0xa2, 0x10, 0x81, 0xe0, /* add r1, r1, r2, lsr #1 */
0x02, 0x40, 0xa0, 0xe1, /* mov r4, r2 */
0xa1, 0x00, 0x54, 0xe1, /* cmp r4, r1, lsr #1 */
/* .Lloop_div1: */
0x84, 0x40, 0xa0, 0x91, /* movls r4, r4, lsl #1 */
0xa1, 0x00, 0x54, 0xe1, /* cmp r4, r1, lsr #1 */
0xfc, 0xff, 0xff, 0x9a, /* bls .Lloop_div1 */
0x00, 0x30, 0xa0, 0xe3, /* mov r3, #0 */
/* .Lloop_div2: */
0x04, 0x00, 0x51, 0xe1, /* cmp r1, r4 */
0x04, 0x10, 0x41, 0x20, /* subhs r1, r1, r4 */
0x03, 0x30, 0xa3, 0xe0, /* adc r3, r3, r3 */
0xa4, 0x40, 0xa0, 0xe1, /* mov r4, r4, lsr #1 */
0x02, 0x00, 0x54, 0xe1, /* cmp r4, r2 */
0xf9, 0xff, 0xff, 0x2a, /* bhs .Lloop_div2 */
0x03, 0x10, 0xa0, 0xe1, /* mov r1, r3 */
/* ; Set new Divisor Latch Low */
/* ; UART_BASE[DLL] = r1 & 0xff */
0x01, 0x20, 0xa0, 0xe1, /* mov r2, r1 */
0xff, 0x20, 0x02, 0xe2, /* and r2, r2, #0xff */
0x00, 0x20, 0x80, 0xe5, /* str r2, [r0, #0x00] */
/* ; Set new Divisor Latch High */
/* ; UART_BASE[DLH] = r1>>8 & 0xff */
0x41, 0x24, 0xa0, 0xe1, /* asr r2, r1, #8 */
0xff, 0x20, 0x02, 0xe2, /* and r2, r2, #0xff */
0x04, 0x20, 0x80, 0xe5, /* str r2, [r0, #0x04] */
/* ; Clear Divisor Latch Access Bit */
/* ; UART_BASE[LCR] &= ~DLAB */
0x0c, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x0c] */
0x80, 0x10, 0xc1, 0xe3, /* bic r1, r1, #0x80 */
0x0c, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0c] */
/* ; Loop 0x2dc000 (2998272) cycles */
/* ; which is about 5ms on 1200 MHz CPU */
/* ; r1 = 0x2dc000 */
0xb7, 0x19, 0xa0, 0xe3, /* mov r1, #0x2dc000 */
/* .Lloop_sleep: */
0x01, 0x10, 0x41, 0xe2, /* sub r1, r1, #1 */
0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
0xfc, 0xff, 0xff, 0x1a, /* bne .Lloop_sleep */
/* ; Jump to the end of execution */
0x01, 0x00, 0x00, 0xea, /* b end */
/* ; Placeholder for old baudrate value */
/* old_baudrate: */
0x00, 0x00, 0x00, 0x00, /* .word 0 */
/* ; Placeholder for new baudrate value */
/* new_baudrate: */
0x00, 0x00, 0x00, 0x00, /* .word 0 */
/* end: */
};
/* ARM code from binary header executed by BootROM before changing baudrate */
static unsigned char kwboot_baud_code_binhdr_pre[] = {
/* ; #define UART_BASE 0xd0012000 */
/* ; #define THR 0x00 */
/* ; #define LSR 0x14 */
/* ; #define THRE 0x20 */
/* ; */
/* ; void send_preamble(void) { */
/* ; const u8 *str = "$baudratechange"; */
/* ; u8 c; */
/* ; do { */
/* ; while */
/* ; ((readl(UART_BASE + LSR) & THRE)); */
/* ; c = *str++; */
/* ; writel(UART_BASE + THR, c); */
/* ; } while (c); */
/* ; } */
/* ; Preserve registers for BootROM */
0xfe, 0x5f, 0x2d, 0xe9, /* push { r1 - r12, lr } */
/* ; r0 = UART_BASE */
0x0d, 0x02, 0xa0, 0xe3, /* mov r0, #0xd0000000 */
0x12, 0x0a, 0x80, 0xe3, /* orr r0, r0, #0x12000 */
/* ; r2 = address of preamble string */
0x00, 0x20, 0x8f, 0xe2, /* adr r2, .Lstr_preamble */
/* ; Skip preamble data section */
0x03, 0x00, 0x00, 0xea, /* b .Lloop_preamble */
/* ; Preamble string */
/* .Lstr_preamble: */
0x24, 0x62, 0x61, 0x75, /* .asciz "$baudratechange" */
0x64, 0x72, 0x61, 0x74,
0x65, 0x63, 0x68, 0x61,
0x6e, 0x67, 0x65, 0x00,
/* ; Send preamble string over UART */
/* .Lloop_preamble: */
/* */
/* ; Wait until Transmitter Holding is Empty */
/* .Lloop_thre: */
/* ; r1 = UART_BASE[LSR] & THRE */
0x14, 0x10, 0x90, 0xe5, /* ldr r1, [r0, #0x14] */
0x20, 0x00, 0x11, 0xe3, /* tst r1, #0x20 */
0xfc, 0xff, 0xff, 0x0a, /* beq .Lloop_thre */
/* ; Put character into Transmitter FIFO */
/* ; r1 = *r2++ */
0x01, 0x10, 0xd2, 0xe4, /* ldrb r1, [r2], #1 */
/* ; UART_BASE[THR] = r1 */
0x00, 0x10, 0x80, 0xe5, /* str r1, [r0, #0x0] */
/* ; Loop until end of preamble string */
0x00, 0x00, 0x51, 0xe3, /* cmp r1, #0 */
0xf8, 0xff, 0xff, 0x1a, /* bne .Lloop_preamble */
};
/* ARM code for returning from binary header back to BootROM */
static unsigned char kwboot_baud_code_binhdr_post[] = {
/* ; Return 0 - no error */
0x00, 0x00, 0xa0, 0xe3, /* mov r0, #0 */
0xfe, 0x9f, 0xbd, 0xe8, /* pop { r1 - r12, pc } */
};
/* ARM code for jumping to the original image exec_addr */
static unsigned char kwboot_baud_code_data_jump[] = {
0x04, 0xf0, 0x1f, 0xe5, /* ldr pc, exec_addr */
/* ; Placeholder for exec_addr */
/* exec_addr: */
0x00, 0x00, 0x00, 0x00, /* .word 0 */
};
static const char kwb_baud_magic[16] = "$baudratechange";
static int kwboot_verbose;
static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO;
static int blk_rsp_timeo = KWBOOT_BLK_RSP_TIMEO;
static ssize_t
kwboot_write(int fd, const char *buf, size_t len)
{
ssize_t tot = 0;
while (tot < len) {
ssize_t wr = write(fd, buf + tot, len - tot);
if (wr < 0 && errno == EINTR)
continue;
else if (wr < 0)
return wr;
tot += wr;
}
return tot;
}
static void
kwboot_printv(const char *fmt, ...)
{
va_list ap;
if (kwboot_verbose) {
va_start(ap, fmt);
vprintf(fmt, ap);
va_end(ap);
fflush(stdout);
}
}
static void
__spinner(void)
{
const char seq[] = { '-', '\\', '|', '/' };
const int div = 8;
static int state, bs;
if (state % div == 0) {
fputc(bs, stdout);
fputc(seq[state / div % sizeof(seq)], stdout);
fflush(stdout);
}
bs = '\b';
state++;
}
static void
kwboot_spinner(void)
{
if (kwboot_verbose)
__spinner();
}
static void
__progress(int pct, char c)
{
const int width = 70;
static const char *nl = "";
static int pos;
if (pos % width == 0)
printf("%s%3d %% [", nl, pct);
fputc(c, stdout);
nl = "]\n";
pos = (pos + 1) % width;
if (pct == 100) {
while (pos && pos++ < width)
fputc(' ', stdout);
fputs(nl, stdout);
nl = "";
pos = 0;
}
fflush(stdout);
}
static void
kwboot_progress(int _pct, char c)
{
static int pct;
if (_pct != -1)
pct = _pct;
if (kwboot_verbose)
__progress(pct, c);
if (pct == 100)
pct = 0;
}
static int
kwboot_tty_recv(int fd, void *buf, size_t len, int timeo)
{
int rc, nfds;
fd_set rfds;
struct timeval tv;
ssize_t n;
rc = -1;
FD_ZERO(&rfds);
FD_SET(fd, &rfds);
tv.tv_sec = 0;
tv.tv_usec = timeo * 1000;
if (tv.tv_usec > 1000000) {
tv.tv_sec += tv.tv_usec / 1000000;
tv.tv_usec %= 1000000;
}
do {
nfds = select(fd + 1, &rfds, NULL, NULL, &tv);
if (nfds < 0 && errno == EINTR)
continue;
else if (nfds < 0)
goto out;
else if (!nfds) {
errno = ETIMEDOUT;
goto out;
}
n = read(fd, buf, len);
if (n < 0 && errno == EINTR)
continue;
else if (n <= 0)
goto out;
buf = (char *)buf + n;
len -= n;
} while (len > 0);
rc = 0;
out:
return rc;
}
static int
kwboot_tty_send(int fd, const void *buf, size_t len, int nodrain)
{
if (!buf)
return 0;
if (kwboot_write(fd, buf, len) < 0)
return -1;
if (nodrain)
return 0;
return tcdrain(fd);
}
static int
kwboot_tty_send_char(int fd, unsigned char c)
{
return kwboot_tty_send(fd, &c, 1, 0);
}
static speed_t
kwboot_tty_baudrate_to_speed(int baudrate)
{
switch (baudrate) {
#ifdef B4000000
case 4000000:
return B4000000;
#endif
#ifdef B3500000
case 3500000:
return B3500000;
#endif
#ifdef B3000000
case 3000000:
return B3000000;
#endif
#ifdef B2500000
case 2500000:
return B2500000;
#endif
#ifdef B2000000
case 2000000:
return B2000000;
#endif
#ifdef B1500000
case 1500000:
return B1500000;
#endif
#ifdef B1152000
case 1152000:
return B1152000;
#endif
#ifdef B1000000
case 1000000:
return B1000000;
#endif
#ifdef B921600
case 921600:
return B921600;
#endif
#ifdef B614400
case 614400:
return B614400;
#endif
#ifdef B576000
case 576000:
return B576000;
#endif
#ifdef B500000
case 500000:
return B500000;
#endif
#ifdef B460800
case 460800:
return B460800;
#endif
#ifdef B307200
case 307200:
return B307200;
#endif
#ifdef B230400
case 230400:
return B230400;
#endif
#ifdef B153600
case 153600:
return B153600;
#endif
#ifdef B115200
case 115200:
return B115200;
#endif
#ifdef B76800
case 76800:
return B76800;
#endif
#ifdef B57600
case 57600:
return B57600;
#endif
#ifdef B38400
case 38400:
return B38400;
#endif
#ifdef B19200
case 19200:
return B19200;
#endif
#ifdef B9600
case 9600:
return B9600;
#endif
#ifdef B4800
case 4800:
return B4800;
#endif
#ifdef B2400
case 2400:
return B2400;
#endif
#ifdef B1800
case 1800:
return B1800;
#endif
#ifdef B1200
case 1200:
return B1200;
#endif
#ifdef B600
case 600:
return B600;
#endif
#ifdef B300
case 300:
return B300;
#endif
#ifdef B200
case 200:
return B200;
#endif
#ifdef B150
case 150:
return B150;
#endif
#ifdef B134
case 134:
return B134;
#endif
#ifdef B110
case 110:
return B110;
#endif
#ifdef B75
case 75:
return B75;
#endif
#ifdef B50
case 50:
return B50;
#endif
default:
#ifdef BOTHER
return BOTHER;
#else
return B0;
#endif
}
}
static int
_is_within_tolerance(int value, int reference, int tolerance)
{
return 100 * value >= reference * (100 - tolerance) &&
100 * value <= reference * (100 + tolerance);
}
static int
kwboot_tty_change_baudrate(int fd, int baudrate)
{
struct termios tio;
speed_t speed;
int rc;
rc = tcgetattr(fd, &tio);
if (rc)
return rc;
speed = kwboot_tty_baudrate_to_speed(baudrate);
if (speed == B0) {
errno = EINVAL;
return -1;
}
#ifdef BOTHER
if (speed == BOTHER)
tio.c_ospeed = tio.c_ispeed = baudrate;
#endif
rc = cfsetospeed(&tio, speed);
if (rc)
return rc;
rc = cfsetispeed(&tio, speed);
if (rc)
return rc;
rc = tcsetattr(fd, TCSANOW, &tio);
if (rc)
return rc;
rc = tcgetattr(fd, &tio);
if (rc)
return rc;
if (cfgetospeed(&tio) != speed || cfgetispeed(&tio) != speed)
goto baud_fail;
#ifdef BOTHER
/*
* Check whether set baudrate is within 3% tolerance.
* If BOTHER is defined, Linux always fills out c_ospeed / c_ispeed
* with real values.
*/
if (!_is_within_tolerance(tio.c_ospeed, baudrate, 3))
goto baud_fail;
if (!_is_within_tolerance(tio.c_ispeed, baudrate, 3))
goto baud_fail;
#endif
return 0;
baud_fail:
fprintf(stderr, "Could not set baudrate to requested value\n");
errno = EINVAL;
return -1;
}
static int
kwboot_open_tty(const char *path, int baudrate)
{
int rc, fd, flags;
struct termios tio;
rc = -1;
fd = open(path, O_RDWR | O_NOCTTY | O_NDELAY);
if (fd < 0)
goto out;
rc = tcgetattr(fd, &tio);
if (rc)
goto out;
cfmakeraw(&tio);
tio.c_cflag |= CREAD | CLOCAL;
tio.c_cflag &= ~(CSTOPB | HUPCL | CRTSCTS);
tio.c_cc[VMIN] = 1;
tio.c_cc[VTIME] = 0;
rc = tcsetattr(fd, TCSANOW, &tio);
if (rc)
goto out;
flags = fcntl(fd, F_GETFL);
if (flags < 0)
goto out;
rc = fcntl(fd, F_SETFL, flags & ~O_NDELAY);
if (rc)
goto out;
rc = kwboot_tty_change_baudrate(fd, baudrate);
if (rc)
goto out;
rc = fd;
out:
if (rc < 0) {
if (fd >= 0)
close(fd);
}
return rc;
}
static void *
kwboot_msg_write_handler(void *arg)
{
int tty = *(int *)((void **)arg)[0];
const void *msg = ((void **)arg)[1];
int rsp_timeo = msg_rsp_timeo;
int i, dummy_oldtype;
/* allow to cancel this thread at any time */
pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, &dummy_oldtype);
while (1) {
/* write 128 samples of message pattern into the output queue without waiting */
for (i = 0; i < 128; i++) {
if (kwboot_tty_send(tty, msg, 8, 1) < 0) {
perror("\nFailed to send message pattern");
exit(1);
}
}
/* wait until output queue is transmitted and then make pause */
if (tcdrain(tty) < 0) {
perror("\nFailed to send message pattern");
exit(1);
}
/* BootROM requires pause on UART after it detects message pattern */
usleep(rsp_timeo * 1000);
}
}
static int
kwboot_msg_start_thread(pthread_t *thread, int *tty, void *msg)
{
void *arg[2];
int rc;
arg[0] = tty;
arg[1] = msg;
rc = pthread_create(thread, NULL, kwboot_msg_write_handler, arg);
if (rc) {
errno = rc;
return -1;
}
return 0;
}
static int
kwboot_msg_stop_thread(pthread_t thread)
{
int rc;
rc = pthread_cancel(thread);
if (rc) {
errno = rc;
return -1;
}
rc = pthread_join(thread, NULL);
if (rc) {
errno = rc;
return -1;
}
return 0;
}
static int
kwboot_bootmsg(int tty)
{
struct kwboot_block block;
pthread_t write_thread;
int rc, err;
char c;
/* flush input and output queue */
tcflush(tty, TCIOFLUSH);
rc = kwboot_msg_start_thread(&write_thread, &tty, kwboot_msg_boot);
if (rc) {
perror("Failed to start write thread");
return rc;
}
kwboot_printv("Sending boot message. Please reboot the target...");
err = 0;
while (1) {
kwboot_spinner();
rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo);
if (rc && errno == ETIMEDOUT) {
continue;
} else if (rc) {
err = errno;
break;
}
if (c == NAK)
break;
}
kwboot_printv("\n");
rc = kwboot_msg_stop_thread(write_thread);
if (rc) {
perror("Failed to stop write thread");
return rc;
}
if (err) {
errno = err;
perror("Failed to read response for boot message pattern");
return -1;
}
/*
* At this stage we have sent more boot message patterns and BootROM
* (at least on Armada XP and 385) started interpreting sent bytes as
* part of xmodem packets. If BootROM is expecting SOH byte as start of
* a xmodem packet and it receives byte 0xff, then it throws it away and
* sends a NAK reply to host. If BootROM does not receive any byte for
* 2s when expecting some continuation of the xmodem packet, it throws
* away the partially received xmodem data and sends NAK reply to host.
*
* Therefore for starting xmodem transfer we have two options: Either
* wait 2s or send 132 0xff bytes (which is the size of xmodem packet)
* to ensure that BootROM throws away any partially received data.
*/
/* flush output queue with remaining boot message patterns */
rc = tcflush(tty, TCOFLUSH);
if (rc) {
perror("Failed to flush output queue");
return rc;
}
/* send one xmodem packet with 0xff bytes to force BootROM to re-sync */
memset(&block, 0xff, sizeof(block));
rc = kwboot_tty_send(tty, &block, sizeof(block), 0);
if (rc) {
perror("Failed to send sync sequence");
return rc;
}
/*
* Sending 132 bytes via 115200B/8-N-1 takes 11.45 ms, reading 132 bytes
* takes 11.45 ms, so waiting for 30 ms should be enough.
*/
usleep(30 * 1000);
/* flush remaining NAK replies from input queue */
rc = tcflush(tty, TCIFLUSH);
if (rc) {
perror("Failed to flush input queue");