Bootstrap options G and F are reported incorrectly (G instead
of F and vice versa). This patch fixes this.

Signed-off-by: Felix Radensky <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>

On platforms where SPD EEPROM and another EEPROM have adjacent
I2C addresses SPD_EEPROM_ADDRESS should be defined as a single
element array, otherwise DDR2 setup code would fail with the
following error:

ERROR: Unknown DIMM detected in slot 1

However, fixing SPD_EEPROM_ADDRESS would result in another
error:

ERROR: DIMM's DDR1 and DDR2 type can not be mixed.

This happens because initdram() routine does not explicitly
initialize dimm_populated array. This patch fixes the problem.

Signed-off-by: Felix Radensky <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>

The list of 4xx SoCs that should send type 1 PCI transactions
is not defined correctly. As a result PCI-PCI bridges and devices
behind them are not identified. The following 4xx variants should
send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.

Signed-off-by: Felix Radensky <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>

A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch adds a CPLD
version detection for Kilauea and code to reconfigure the EBC controller
(chip select 2) for the old CPLD if no new version is found.

Additionally the CPLD version is printed upon bootup:

Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0)

Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Wolfgang Denk <[email protected]>
Cc: Zhang Bao Quan <[email protected]>

Update CHANGELOG

Signed-off-by: Wolfgang Denk <[email protected]>