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4 | 4 |
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5 | 5 | #ifndef HAVE_FEENABLEEXCEPT
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6 | 6 | #if defined(__APPLE__) && defined(__MACH__)
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| 7 | +#if defined __i386__ || defined __x86_64__ |
7 | 8 |
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8 | 9 | // Public domain polyfill for feenableexcept on OS X
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9 | 10 | // http://www-personal.umich.edu/~williams/archive/computation/fe-handling-example.c
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@@ -46,6 +47,70 @@ inline int fedisableexcept(unsigned int excepts)
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46 | 47 | return fesetenv(&fenv) ? -1 : old_excepts;
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47 | 48 | }
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48 | 49 |
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| 50 | +#elif defined __arm64__ |
| 51 | + |
| 52 | +/* |
| 53 | + Yoinked and adapted this ARM64 implementation of floating point exceptions from |
| 54 | + https://android.googlesource.com/platform/bionic/+/a147a1d/libm/arm64/fenv.c |
| 55 | + */ |
| 56 | + |
| 57 | +/*- |
| 58 | + * Copyright (c) 2004 David Schultz <[email protected]> |
| 59 | + * All rights reserved. |
| 60 | + * |
| 61 | + * Redistribution and use in source and binary forms, with or without |
| 62 | + * modification, are permitted provided that the following conditions |
| 63 | + * are met: |
| 64 | + * 1. Redistributions of source code must retain the above copyright |
| 65 | + * notice, this list of conditions and the following disclaimer. |
| 66 | + * 2. Redistributions in binary form must reproduce the above copyright |
| 67 | + * notice, this list of conditions and the following disclaimer in the |
| 68 | + * documentation and/or other materials provided with the distribution. |
| 69 | + * |
| 70 | + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 71 | + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 72 | + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 73 | + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 74 | + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 75 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 76 | + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 77 | + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 78 | + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 79 | + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 80 | + * SUCH DAMAGE. |
| 81 | + * |
| 82 | + * $FreeBSD: libm/aarch64/fenv.c $ |
| 83 | + */ |
| 84 | + |
| 85 | + |
| 86 | +#define FPCR_EXCEPT_SHIFT 8 |
| 87 | + |
| 88 | +// FPCR, Floating-point Control Register. |
| 89 | +#define __get_fpcr(__fpcr) __asm__ __volatile__("mrs %0,fpcr" : "=r" (__fpcr)) |
| 90 | +#define __set_fpcr(__fpcr) __asm__ __volatile__("msr fpcr,%0" : :"ri" (__fpcr)) |
| 91 | + |
| 92 | +inline int feenableexcept(int mask) { |
| 93 | + unsigned long long old_fpcr, new_fpcr; |
| 94 | + __get_fpcr(old_fpcr); |
| 95 | + new_fpcr = old_fpcr | ((mask & FE_ALL_EXCEPT) << FPCR_EXCEPT_SHIFT); |
| 96 | + if (new_fpcr != old_fpcr) { |
| 97 | + __set_fpcr(new_fpcr); |
| 98 | + } |
| 99 | + return ((old_fpcr >> FPCR_EXCEPT_SHIFT) & FE_ALL_EXCEPT); |
| 100 | +} |
| 101 | + |
| 102 | +inline int fedisableexcept(int mask) { |
| 103 | + unsigned long long old_fpcr, new_fpcr; |
| 104 | + __get_fpcr(old_fpcr); |
| 105 | + new_fpcr = old_fpcr & ~((mask & FE_ALL_EXCEPT) << FPCR_EXCEPT_SHIFT); |
| 106 | + if (new_fpcr != old_fpcr) { |
| 107 | + __set_fpcr(new_fpcr); |
| 108 | + } |
| 109 | + return ((old_fpcr >> FPCR_EXCEPT_SHIFT) & FE_ALL_EXCEPT); |
| 110 | +} |
| 111 | + |
| 112 | +#endif |
| 113 | + |
49 | 114 | #else
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50 | 115 | inline int feenableexcept(unsigned int excepts)
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51 | 116 | {
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