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Commits on May 3, 2018

• [X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.

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• [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes

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• [PowerPC] add tests for FMF propagation; NFC

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• [DebugInfo] Correction for an assert in DIExpression::createFragmentExpression

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• Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"

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• use LLVM's standard CMakeLists.txt layout for llvm-xray

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• [CodeGen][X86][NFC] Copy two selectcc tests from AArch64.

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• [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes

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• ARM: don't try to over-align large vectors as arguments.

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• perform DSE through launder.invariant.group

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• Rename invariant.group.barrier to launder.invariant.group

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• [X86][AVX512] VPAVG instructions should be tagged as SchedWriteVecALU

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• [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM scheduler classes

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• [X86] Update MMX instructions to be tagged with X86SchedWriteWidths types

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• [WebAssembly] MC: Don't litter test directory.

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• Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"

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• [TableGen][NFC] Make ResourceCycles definitions more explicit.

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• [LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the left hand side of the 'and' matches the left hand side of the 'subtract'

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• [LoopIdiomRecognize] Add a test case showing that we transform to ctpop without fully checking the 'x & (x-1)' part.

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• [LoopIdiomRecognize] Remove unnecessary cast from BinaryOperator to Instruction. NFC

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• lit: flesh out SubsituteCaptures further

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• Re-enable "[SCEV] Make computeExitLimit more simple and more powerful"

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  Max Kazantsev

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• [Support] Support building LLVM for Fuchsia

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• [ObjCARC] Convert an if to an early continue. NFC

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• Commit r331416 breaks the big-endian PPC bot. On the big endian build, we

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• [gcov] Switch to an explicit if clunky array to satisfy some compilers

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• MachineInst support mapping SDNode fast math flags for support in Back End code generation

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  Michael Berg

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Commits on May 2, 2018

• [PowerPC] Implement isMaskAndCmp0FoldingBeneficial

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• [WebAssembly] MC: Create and use first class section symbols

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• [MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer.

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• [PowerPC] No CTR loop if the candidate exiting block is in a different loop

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• [GCOV] Emit the writeout function as nested loops of global data.

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• [llvm-rc] Default to writing the output next to the input, if no output is specified

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• [llvm-cvtres] Allow parameters preceded by '-' in addition to '/'

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• [llvm-objcopy] Add --discard-all (-x) option

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