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Commits on Nov 20, 2024

• Update README.md

  jbilander

  authored
  88774e4

Commits on Aug 31, 2024

• Update README.md

  jbilander

  authored
  a19e91a

• add pin-assignment picture

  jbilander

  committed
  acdf882

Commits on Aug 15, 2024

• Corrected C20 value from 0.01uF to 0.1uF

  jbilander

  committed
  c5a8cc5

Commits on Jul 1, 2024

• Corrected values for capacitors C4,C5,C8,C11 to 1uF and the reference for the Winslow plug to U8 to match the BOM

  jbilander

  committed
  9efeb6a

• Update README.md

  jbilander

  authored
  e81b559

Commits on May 17, 2024

• Update README.md

  jbilander

  authored
  d39ed1d

• Update README.md

  jbilander

  authored
  0f67e6f

• Add images of rev2d

  jbilander

  committed
  531eeeb

• small fix/improvement adding a second GND-via for pin 47,48 on U4

  jbilander

  committed
  f53667a

Commits on May 14, 2024

• deleted file

  jbilander

  committed
  8118a25

• Add schematic pdf

  jbilander

  committed
  758dd21

• silkscreen fixes

  jbilander

  committed
  418c749

• Update README.md

  jbilander

  authored
  f253737

• Added pull-up resistor (R2) to VCC for pin 41, added JLCJLCJLCJLC to silkscreen for orderno placement, bumped version to Rev. 2E

  jbilander

  committed
  023cd0a

Commits on Apr 18, 2024

• Update README.md

  jbilander

  authored
  ed8b3da

Commits on Apr 16, 2024

• Update README.md

  jbilander

  authored
  f3e110b

Commits on Apr 15, 2024

• Added schematic pdf

  jbilander

  committed
  befbb51

• removed old schematic pdfs

  jbilander

  committed
  2b27584

• Improved routing, E1,L3 set to GND, removed debug-pin, E4,E5 set to NC, moved A3_FPGA to pad F4, Removed DONE-signal (not needed).

  jbilander

  committed
  d81febc

Commits on Feb 18, 2024

• Update README.md

  jbilander

  authored
  7a3f0c9

• Added schematic pdf

  jbilander

  committed
  7e6283b

• Assigning 3V3 to unused clock inputs H6, L3 and GND to H4, N2, N3, G10, E13 and for better grounding to J5, J6, E12, swapped position of TCK and TMS in resistor array

  jbilander

  committed
  1896b9b

• Removed CONFIG_SEL and repurposed trace for nCONFIG pull-up routing it through D8 to reach E7 (nCONFIG pad)

  jbilander

  committed
  8118140

Commits on Feb 10, 2024

• Update README.md

  jbilander

  authored
  4fa85d9

• added image

  jbilander

  committed
  1cff217

Commits on Feb 9, 2024

• Update README.md

  jbilander

  authored
  0b56023

• added image

  jbilander

  committed
  7a4427b

• Update README.md

  jbilander

  authored
  e6e4fdb

• Merge branch 'main' of https://github.com/jbilander/ReAgnus

  jbilander

  committed
  05cf035

• Added images

  jbilander

  committed
  7784580

Commits on Feb 2, 2024

• Update README.md

  jbilander

  authored
  d6662b7

Commits on Feb 1, 2024

• Update README.md

  jbilander

  authored
  5cd4d9b

• Added images

  jbilander

  committed
  fcd451f

Commits on Oct 23, 2023

• small cosmetic fix of RGA2 trace

  jbilander

  committed
  d9f58c9

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