Verilog Ethernet components for FPGA implementation

Open source FPGA-based NIC and platform for in-network compute

HDL libraries and projects

Verilog library for ASIC and FPGA designers

An Open-source FPGA IP Generator

🌱 Open source ecosystem for open FPGA boards

3-stage RV32IMACZb* processor with debug

A tiny Open POWER ISA softcore written in VHDL 2008

A High-performance Timing Analysis Tool for VLSI Systems

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

A DDR3 memory controller in Verilog for various FPGAs

An open source SPI flash emulator and monitor

Verilog SDRAM memory controller

Opensource DDR3 Controller

USB3 PIPE interface for Xilinx 7-Series

SystemVerilog synthesis tool

Fearless hardware design

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitatio…

FPGA Logic Analyzer and GUI

Plugins for Yosys developed as part of the F4PGA project.

Minimal DVI / HDMI Framebuffer

Introductory course into static timing analysis (STA).

Xilinx Unisim Library in Verilog

PanoLogic Zero Client G1 reverse engineering info

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an…

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs