From e39aae81e1a40ba495893f1c4e04b23401eca3a3 Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Tue, 10 Apr 2018 19:03:12 +0200 Subject: [PATCH] core: crypto: arm32: add counter increment in ce_aes_ctr_encrypt() Commit 628a9a10ca36 ("ltc: ctr: improve performance") reveals a bug in the Aarch32 accelerated crypto code (AES CTR mode), which causes xtest 9159 to fail with some invalid buffer content: encrypting 96 bytes of data in one pass does not yield the same result than encrypting 3 * 32 bytes. The problem is fixed by adding a missing counter increment in ce_aes_ctr_encrypt(). Fixes: 9ff4f2ccc026 ("arm32: AES using ARMv8-A cryptographic extensions") Signed-off-by: Jerome Forissier Tested-by: Jerome Forissier (HiKey960) Acked-by: Joakim Bech Acked-by: Jens Wiklander --- core/lib/libtomcrypt/src/ciphers/aes_modes_armv8a_ce_a32.S | 1 + 1 file changed, 1 insertion(+) diff --git a/core/lib/libtomcrypt/src/ciphers/aes_modes_armv8a_ce_a32.S b/core/lib/libtomcrypt/src/ciphers/aes_modes_armv8a_ce_a32.S index d02714d28ee..38cd06ab3fc 100644 --- a/core/lib/libtomcrypt/src/ciphers/aes_modes_armv8a_ce_a32.S +++ b/core/lib/libtomcrypt/src/ciphers/aes_modes_armv8a_ce_a32.S @@ -296,6 +296,7 @@ ce_aes_ctr_encrypt: .Lctrloop3x: subs r4, r4, #3 bmi .Lctr1x + add r6, r6, #1 vmov q0, q6 vmov q1, q6 rev ip, r6