From 381382d4262dfa72d8450dc69f080a676305187d Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Fri, 16 Apr 2021 11:42:05 +0000 Subject: [PATCH 001/511] MAINTAINERS: gemini: add missing dts pattern The MAINTAINERS entry for cortina/gemini miss all dts of this platform. Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index bd7aff0c120f20..bf6aaf61bdbc3b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1810,6 +1810,7 @@ F: Documentation/devicetree/bindings/arm/gemini.txt F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt +F: arch/arm/boot/dts/gemini* F: arch/arm/mach-gemini/ F: drivers/net/ethernet/cortina/ F: drivers/pinctrl/pinctrl-gemini.c From fc5b59b945b546e27977e99a5ca6fe61179ff0d2 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 28 Apr 2021 17:48:30 +0000 Subject: [PATCH 002/511] ARM: dts: gemini: rename mdio to the right name ethernet-phy is not the right name for mdio, fix it. Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dns-313.dts | 2 +- arch/arm/boot/dts/gemini-nas4220b.dts | 2 +- arch/arm/boot/dts/gemini-rut1xx.dts | 2 +- arch/arm/boot/dts/gemini-wbd111.dts | 2 +- arch/arm/boot/dts/gemini-wbd222.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts index c6f3d90e3e90ce..b8acc6eaaa6d72 100644 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -140,7 +140,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; /* Uses MDC and MDIO */ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 43c45f7e1e0a34..13112a8a5dd88d 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -62,7 +62,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts index 9611ddf0679274..79f17988884fdd 100644 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini-rut1xx.dts @@ -56,7 +56,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts index 3a2761dd460f99..5602ba8f30f2f1 100644 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini-wbd111.dts @@ -68,7 +68,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts index 52b4dbc0c0723f..a4a260c36d752f 100644 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini-wbd222.dts @@ -67,7 +67,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ From 3d3bb3d27cd371d3edb43eeb1beb8ae4e92a356d Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 28 Apr 2021 18:54:57 +0000 Subject: [PATCH 003/511] ARM: dts: gemini-rut1xx: remove duplicate ethernet node Two ethernet node was added by commit 95220046a62c ("ARM: dts: Add ethernet to a bunch of platforms") and commit d6d0cef55e5b ("ARM: dts: Add the FOTG210 USB host to Gemini boards") This patch removes the duplicate one. Fixes: d6d0cef55e5b ("ARM: dts: Add the FOTG210 USB host to Gemini boards") Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-rut1xx.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts index 79f17988884fdd..0ebda4efd9d0fb 100644 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini-rut1xx.dts @@ -125,18 +125,6 @@ }; }; - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - usb@68000000 { status = "okay"; }; From 483f3645b3f7acfd1c78a19d51b80c0656161974 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Mon, 3 May 2021 18:52:28 +0000 Subject: [PATCH 004/511] ARM: dts: gemini: add device_type on pci Fixes DT warning on pci node by adding the missing device_type. Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 065ed10a79fa7e..07448c03dac9e1 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -286,6 +286,7 @@ clock-names = "PCLK", "PCICLK"; pinctrl-names = "default"; pinctrl-0 = <&pci_default_pins>; + device_type = "pci"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; From 0e00c9135b62e9a59f6dfb7e479f1f7abbb1c3d3 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Mon, 3 May 2021 19:50:48 +0000 Subject: [PATCH 005/511] ARM: dts: gemini: use the right rtc compatible The rtc compatible was not following the dt-binding. Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 07448c03dac9e1..23271d537ae5b6 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -191,7 +191,7 @@ }; rtc@45000000 { - compatible = "cortina,gemini-rtc"; + compatible = "cortina,gemini-rtc", "faraday,ftrtc010"; reg = <0x45000000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_RTC>; From d5c24e20daf09587cbc221d40be1ba92673e8d94 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 6 May 2021 14:55:11 -0300 Subject: [PATCH 006/511] ARM: dts: rockchip: Fix thermal sensor cells o rk322x The number of cells to be used with a thermal sensor specifier must be "1". Fix this. Signed-off-by: Ezequiel Garcia Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20210506175514.168365-2-ezequiel@collabora.com --- arch/arm/boot/dts/rk322x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 208f2124509536..9f02ba7a0cc2da 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -517,7 +517,7 @@ pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <0>; + #thermal-sensor-cells = <1>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; From dfbfb86a43f9a5bbd166d88bca9e07ee4e1bff31 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 26 Jan 2021 12:02:20 +0100 Subject: [PATCH 007/511] ARM: dts: rockchip: fix pinctrl sleep nodename for rk3036-kylin and rk3288 A test with the command below aimed at powerpc generates notifications in the Rockchip ARM tree. Fix pinctrl "sleep" nodename by renaming it to "suspend" for rk3036-kylin and rk3288 make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/powerpc/sleep.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210126110221.10815-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 2 +- arch/arm/boot/dts/rk3288.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 7154b827ea2f07..e817eba8c622ba 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -390,7 +390,7 @@ }; }; - sleep { + suspend { global_pwroff: global-pwroff { rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 05557ad02b33cb..24b903240cb3cc 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1582,7 +1582,7 @@ drive-strength = <12>; }; - sleep { + suspend { global_pwroff: global-pwroff { rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; }; From bbac8bd65f5402281cb7b0452c1c5f367387b459 Mon Sep 17 00:00:00 2001 From: Cameron Nemo Date: Tue, 4 May 2021 16:36:13 +0800 Subject: [PATCH 008/511] arm64: dts: rockchip: Enable USB3 for rk3328 Rock64 Enable USB3 nodes for the rk3328-based PINE Rock64 board. The separate power regulator is not added as it is controlled by the same GPIO line as the existing VBUS regulators, so it is already enabled. Also there is no port representation to tie the regulator to. [wens@csie.org: Rebased onto v5.12] Signed-off-by: Cameron Nemo [wens@csie.org: Rewrote commit message] Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20210504083616.9654-2-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 3bef1f39bc6e13..1b0f7e4551ea49 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -381,6 +381,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; From 75f95927334dea863f16f4ecd29cc709edc3c6ad Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 4 May 2021 16:36:14 +0800 Subject: [PATCH 009/511] arm64: dts: rockchip: Enable USB3 for rk3328 ROC-RK3328-CC Enable USB3 nodes for the ROC-RK3328-CC board. The separate power regulator is not added as it is controlled by the same GPIO line as the existing VBUS regulators, so it is already enabled. Also there is no port representation to tie the regulator to. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20210504083616.9654-3-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index a05732b59f3804..bdf0ca07eae9da 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -363,6 +363,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; From bf340c8084d2932936f385ebf48c4734b2911457 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 4 May 2021 16:36:15 +0800 Subject: [PATCH 010/511] arm64: dts: rockchip: Enable USB3 for rk3328 Rock Pi E Enable USB3 nodes for the Rock Pi E board. The VBUS regulator device node was added when the board was first introduced. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20210504083616.9654-4-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts index c7e31efdd2e112..07538951a3a671 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts @@ -382,6 +382,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; From d49f120e27dc1689e11a14e9714e63a390dd4520 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 4 May 2021 16:36:16 +0800 Subject: [PATCH 011/511] arm64: dts: rockchip: Enable USB3 Ethernet on rk3328 NanoPi R2S The NanoPi R2S has a Realtek RTL8153B USB 3.0 Ethernet chip connected to the USB 3.0 pins of the RK3328 SoC. Power to the chip is controlled by a GPIO line toggled transistor switch, which is not a full-blown voltage regulator. At least in Linux, the USB 3.0 XHCI controller has two ports: the first port is for legacy USB 2.0 and slower, while the second port is for USB 3.0. Since the Ethernet chip supports USB 3.0, it should be described as connected to the second port. Add the device nodes for the power switch and Ethernet chip, and enable the USB 3.0 controller. The USB device node follows the standard USB device binding. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20210504083616.9654-5-wens@kernel.org Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts index f807bc066ccb9c..64cf07ee3d10cb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts @@ -14,6 +14,7 @@ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; aliases { + ethernet1 = &rtl8153; mmc0 = &sdmmc; }; @@ -101,6 +102,18 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vdd_5v_lan: vdd-5v-lan { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lan_vdd_pin>; + pinctrl-names = "default"; + regulator-name = "vdd_5v_lan"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; }; &cpu0 { @@ -309,6 +322,12 @@ }; }; + lan { + lan_vdd_pin: lan-vdd-pin { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; @@ -368,6 +387,19 @@ dr_mode = "host"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /* Second port is for USB 3.0 */ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; + }; +}; + &usb_host0_ehci { status = "okay"; }; From 6a11ffc2cc54d89719d5b2f3ca44244cebd7ed2e Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Mon, 26 Apr 2021 19:46:52 +0800 Subject: [PATCH 012/511] arm64: dts: rockchip: rename LED label for NanoPi R4S However "sys" is not a valid function, and it is always on. Let's keep existing functions. Fixes: db792e9adbf85f ("rockchip: rk3399: Add support for FriendlyARM NanoPi R4S") Suggested-by: Pavel Machek Signed-off-by: Tianling Shen Acked-by: Pavel Machek Link: https://lore.kernel.org/r/20210426114652.29542-1-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts index fa580988764388..cef4d18b599dd1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts @@ -33,7 +33,7 @@ sys_led: led-sys { gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "red:sys"; + label = "red:power"; default-state = "on"; }; From e6526f90696e6a7d722d04b958f15b97d6fd9ce6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 26 Apr 2021 17:59:16 +0800 Subject: [PATCH 013/511] arm64: dts: rockchip: Drop fephy pinctrl from gmac2phy on rk3328 rock-pi-e Turns out the fephy pins are already claimed in the phy node, which is rightfully where they should be claimed. Drop the pinctrl properties from the gmac2phy node for the ROCK Pi E. Fixes: b918e81f2145 ("arm64: dts: rockchip: rk3328: Add Radxa ROCK Pi E") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20210426095916.14574-1-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts index 07538951a3a671..018a3a5075c72e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts @@ -177,8 +177,6 @@ }; &gmac2phy { - pinctrl-names = "default"; - pinctrl-0 = <&fephyled_linkm1>, <&fephyled_rxm1>; status = "okay"; }; From 642593eec32571ff9288ddf3fa09792d3efb275f Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 6 May 2021 08:11:34 -0300 Subject: [PATCH 014/511] arm64: dts: rockchip: add timer0 clocks on rk3368 The timer driver requires pclk and sclk clocks to be present in the device tree node, so add them. Signed-off-by: Ezequiel Garcia Link: https://lore.kernel.org/r/20210506111136.3941-2-ezequiel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index dfc6376171d032..4c64fbefb48342 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -664,6 +664,8 @@ compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = ; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; + clock-names = "pclk", "timer"; }; spdif: spdif@ff880000 { From 954d5986afa50c178ea7554e6abdd611d08f5ade Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 13 Apr 2021 15:17:09 +0100 Subject: [PATCH 015/511] arm64: dts: rockchip: Use only supported PCIe link speed on rk3399 The max link speed supported by the rk3399 is already set in the rk3399.dtsi file so don't set unsupported link speeds in device specific DTs. This is the same fix as 642fb27. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20210413141709.845592-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 1 - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 1 - arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 16fd58c4a80f3f..8c0ff6c96e0378 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -510,7 +510,6 @@ }; &pcie0 { - max-link-speed = <2>; num-lanes = <2>; vpcie0v9-supply = <&vcca0v9_s3>; vpcie1v8-supply = <&vcca1v8_s3>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 7d0a7c6977039c..b28888ea9262ee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -474,7 +474,6 @@ &pcie0 { ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <4>; pinctrl-0 = <&pcie_clkreqnb_cpm>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index c0074b3ed4af79..01d1a75c8b4d3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -329,7 +329,6 @@ &pcie0 { ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <4>; pinctrl-0 = <&pcie_clkreqnb_cpm>; pinctrl-names = "default"; From a7ecfad495f8af63a5cb332c91f60ab2018897f5 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 26 Jan 2021 12:02:21 +0100 Subject: [PATCH 016/511] arm64: dts: rockchip: fix pinctrl sleep nodename for rk3399.dtsi A test with the command below aimed at powerpc generates notifications in the Rockchip arm64 tree. Fix pinctrl "sleep" nodename by renaming it to "suspend" for rk3399.dtsi make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/powerpc/sleep.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210126110221.10815-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 634a91af8e83bd..7c1b69f3a4c11d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -2354,7 +2354,7 @@ }; }; - sleep { + suspend { ap_pwroff: ap-pwroff { rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; }; From 7b46d674ac000b101fdad92cf16cc11d90b72f86 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 6 May 2021 08:11:35 -0300 Subject: [PATCH 017/511] ARM: dts: rockchip: Fix the timer clocks order Fixed order is the device-tree convention. The timer driver currently gets clocks by name, so no changes are needed there. Signed-off-by: Ezequiel Garcia Link: https://lore.kernel.org/r/20210506111136.3941-3-ezequiel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 8 ++++---- arch/arm/boot/dts/rk3288.dtsi | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 2298a8d840ba32..2c08ae60e4a137 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -150,16 +150,16 @@ compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; reg = <0x2000e000 0x20>; interrupts = ; - clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; - clock-names = "timer", "pclk"; + clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; + clock-names = "pclk", "timer"; }; timer6: timer@200380a0 { compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; reg = <0x200380a0 0x20>; interrupts = ; - clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; + clock-names = "pclk", "timer"; }; i2s0: i2s@1011a000 { diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 24b903240cb3cc..1e6594f8a293df 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -196,8 +196,8 @@ compatible = "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = ; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; }; display-subsystem { From 6b023929666f0be5df75f5e0278d1b70effadf42 Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Fri, 7 May 2021 11:02:29 +0200 Subject: [PATCH 018/511] ARM: dts: rockchip: Fix IOMMU nodes properties on rk322x Add '#" to iommu-cells properties. Remove useless interrupt-names properties Signed-off-by: Benjamin Gaignard Link: https://lore.kernel.org/r/20210507090232.233049-4-benjamin.gaignard@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 9f02ba7a0cc2da..25f83f2f5618e0 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -558,10 +558,9 @@ compatible = "rockchip,iommu"; reg = <0x20020800 0x100>; interrupts = ; - interrupt-names = "vpu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; - iommu-cells = <0>; + #iommu-cells = <0>; status = "disabled"; }; @@ -569,10 +568,9 @@ compatible = "rockchip,iommu"; reg = <0x20030480 0x40>, <0x200304c0 0x40>; interrupts = ; - interrupt-names = "vdec_mmu"; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; - iommu-cells = <0>; + #iommu-cells = <0>; status = "disabled"; }; @@ -602,7 +600,6 @@ compatible = "rockchip,iommu"; reg = <0x20053f00 0x100>; interrupts = ; - interrupt-names = "vop_mmu"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -623,10 +620,9 @@ compatible = "rockchip,iommu"; reg = <0x20070800 0x100>; interrupts = ; - interrupt-names = "iep_mmu"; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; - iommu-cells = <0>; + #iommu-cells = <0>; status = "disabled"; }; From 304b8fbc950bae102f29ee1e8e8557f2fd08d69a Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Fri, 7 May 2021 11:02:30 +0200 Subject: [PATCH 019/511] ARM: dts: rockchip: Remove useless interrupt-names on IOMMU node on rk3036 Remove useless interrupt-names property for IOMMU node Signed-off-by: Benjamin Gaignard Link: https://lore.kernel.org/r/20210507090232.233049-5-benjamin.gaignard@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index e24230d50a7804..9ccefa8282babc 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -140,7 +140,6 @@ compatible = "rockchip,iommu"; reg = <0x10118300 0x100>; interrupts = ; - interrupt-names = "vop_mmu"; clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; From 2bf375982f4a58a95e8b5184565b23677900012c Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Fri, 7 May 2021 11:02:31 +0200 Subject: [PATCH 020/511] arm64: dts: rockchip: Remove useless interrupt-names properties from px30 IOMMU nodes Remove useless interrupt-names properties for IOMMU nodes Signed-off-by: Benjamin Gaignard Link: https://lore.kernel.org/r/20210507090232.233049-6-benjamin.gaignard@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 09baa8a167ce65..86644e24aa5f23 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1087,7 +1087,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff460f00 0x0 0x100>; interrupts = ; - interrupt-names = "vopb_mmu"; clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; clock-names = "aclk", "iface"; power-domains = <&power PX30_PD_VO>; @@ -1128,7 +1127,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff470f00 0x0 0x100>; interrupts = ; - interrupt-names = "vopl_mmu"; clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; clock-names = "aclk", "iface"; power-domains = <&power PX30_PD_VO>; From fd5ef505453f995b4ce6ef6e43ddc15967a94a96 Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:24 +0300 Subject: [PATCH 021/511] ARM: dts: sun8i: r40: add /omit-if-no-ref/ to pinmux nodes for UARTs 0&3 This patch adds the /omit-if-no-ref/ keyword to the pio nodes for UART0 and UART3 pins of the R40 SoC, which would reduce the fdt size on boards which do not use these UARTs. Signed-off-by: Ivan Uvarov 1 file changed, 3 insertions(+) Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-2-i.uvarov@cognitivepilot.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5ad3b9efd1248..0b257a07792fc8 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -631,16 +631,19 @@ function = "spi1"; }; + /omit-if-no-ref/ uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; }; + /omit-if-no-ref/ uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7"; function = "uart3"; }; + /omit-if-no-ref/ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { pins = "PG8", "PG9"; function = "uart3"; From 492dd7309aed4d2313a6f9d9a26f88707f51161b Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:25 +0300 Subject: [PATCH 022/511] ARM: dts: sun8i: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7 The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40 SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to an RS485 converter, and the rest broken out directly via labeled headers. The board also contains a micro-SD slot connected to SDC3. This patch adds settings to R40's pinmux node for MMC3 and those UARTs that were not already mapped, which would allow us to make use of all available UARTs and the micro-SD slot on this board in a further patch. Reviewed-by: Andre Przywara Signed-off-by: Ivan Uvarov 1 file changed, 41 insertions(+) Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-3-i.uvarov@cognitivepilot.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 0b257a07792fc8..03e054c0bac40c 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -357,6 +357,8 @@ clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC3>; reset-names = "ahb"; + pinctrl-0 = <&mmc3_pins>; + pinctrl-names = "default"; interrupts = ; status = "disabled"; #address-cells = <1>; @@ -601,6 +603,15 @@ bias-pull-up; }; + /omit-if-no-ref/ + mmc3_pins: mmc3-pins { + pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; + function = "mmc3"; + drive-strength = <30>; + bias-pull-up; + }; + /omit-if-no-ref/ spi0_pc_pins: spi0-pc-pins { pins = "PC0", "PC1", "PC2"; @@ -637,6 +648,18 @@ function = "uart0"; }; + /omit-if-no-ref/ + uart2_pi_pins: uart2-pi-pins { + pins = "PI18", "PI19"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ + pins = "PI16", "PI17"; + function = "uart2"; + }; + /omit-if-no-ref/ uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7"; @@ -648,6 +671,24 @@ pins = "PG8", "PG9"; function = "uart3"; }; + + /omit-if-no-ref/ + uart4_pg_pins: uart4-pg-pins { + pins = "PG10", "PG11"; + function = "uart4"; + }; + + /omit-if-no-ref/ + uart5_ph_pins: uart5-ph-pins { + pins = "PH6", "PH7"; + function = "uart5"; + }; + + /omit-if-no-ref/ + uart7_pi_pins: uart7-pi-pins { + pins = "PI20", "PI21"; + function = "uart7"; + }; }; wdt: watchdog@1c20c90 { From 157da630c7ff848439f721257f26655b5ae2d856 Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:26 +0300 Subject: [PATCH 023/511] dt-bindings: add compatible vendor prefix for Forlinx Baoding Forlinx Embedded Technology Co., Ltd. is the manufacturer of the Allwinner R40/A40i-powered FETA40i-C SoM and the OKA40i-C dev/carrier board based on it. This patch adds the DT vendor prefix for Forlinx in preparation for a further patch, which includes a devicetree for the OKA40i-C board. Signed-off-by: Ivan Uvarov 1 file changed, 2 insertions(+) Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-4-i.uvarov@cognitivepilot.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b868cefc7c5500..44e59ee2ae9022 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -409,6 +409,8 @@ patternProperties: description: Firefly "^focaltech,.*": description: FocalTech Systems Co.,Ltd + "^forlinx,.*": + description: Baoding Forlinx Embedded Technology Co., Ltd. "^frida,.*": description: Shenzhen Frida LCD Co., Ltd. "^friendlyarm,.*": From ed85561fe39c994e9ba1a97614b5269158a98ca9 Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:27 +0300 Subject: [PATCH 024/511] dt-bindings: arm: add compatible for Forlinx OKA40i-C and FETA40i-C The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i SoC. The OKA40i-C is a carrier/development board by the same company based on this SoM. This patch adds compatible strings for these two devices in preparation for the next patch containing a devicetree for them. Signed-off-by: Ivan Uvarov 1 file changed, 6 insertions(+) Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-5-i.uvarov@cognitivepilot.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ac750025a2eba1..ec8108483b49a7 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -224,6 +224,12 @@ properties: - const: empire-electronix,m712 - const: allwinner,sun5i-a13 + - description: Forlinx OKA40i-C Development board + items: + - const: forlinx,oka40i-c + - const: forlinx,feta40i-c + - const: allwinner,sun8i-r40 + - description: FriendlyARM NanoPi A64 items: - const: friendlyarm,nanopi-a64 From d0aac8cbbd0ce601ef38317a3f69028b6910bace Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Wed, 7 Apr 2021 14:14:28 +0300 Subject: [PATCH 025/511] ARM: dts: sun8i: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i. SoM specifications: - SoC: R40 or A40i - PMIC: AXP221S - RAM: 1GiB/2GiB DDR3 (dual-rank) - eMMC: 8GB, - Mates with carrier board via four 80-pin connectors (AXK6F80337YG). OKA40i-C is a carrier board by the same manufacturer for this SoM, whose main purpose is as a development board with a wide variety of peripherals: - Power: DC5V barrel or USB OTG or 4.2V Lipo battery - Video out: HDMI, TV out, LVDS - WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0) - Ethernet: 10/100Mbps - Storage: µSD, fullsize SD, eMMC (on SoM), SATA - USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B) - UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS) - Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header - Mini PCIe slot with sim holder for WLAN modem - Smart card holder - RTC (RX8010SJ) - Two user LEDs - Three user buttons (via KeyADC). This patch adds a devicetree for the aforementioned SoM and devboard. In order to reflect the modularity of this devboard and simplify adding support for future hardware based on the same SoM, the devicetree is split: Everything pertaining to the SoM itself is described in a separate .dtsi file, which is included by the devboard's .dts. Reviewed-by: Andre Przywara Signed-off-by: Ivan Uvarov 3 files changed, 310 insertions(+) Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210407111428.3755684-6-i.uvarov@cognitivepilot.com --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-r40-feta40i.dtsi | 106 ++++++++++++ arch/arm/boot/dts/sun8i-r40-oka40i-c.dts | 203 +++++++++++++++++++++++ 3 files changed, 310 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r40-feta40i.dtsi create mode 100644 arch/arm/boot/dts/sun8i-r40-oka40i-c.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e750..1754b562e0b99f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1234,6 +1234,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ sun8i-s3-elimo-initium.dtb \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi new file mode 100644 index 00000000000000..265e0fa57a32af --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai +// Copyright (C) 2017 Icenowy Zheng + +#include "sun8i-r40.dtsi" + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_aldo2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_dcdc1>; + vcc-pc-supply = <®_aldo2>; + vcc-pd-supply = <®_dcdc1>; + vcc-pf-supply = <®_dldo4>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts new file mode 100644 index 00000000000000..0bd1336206b839 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai +// Copyright (C) 2017 Icenowy Zheng + +/dts-v1/; +#include "sun8i-r40-feta40i.dtsi" + +#include +#include + +/ { + model = "Forlinx OKA40i-C"; + compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40"; + + aliases { + ethernet0 = &gmac; + serial0 = &uart0; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; /* RS485 */ + serial7 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-5 { /* this is how the leds are labeled on the board */ + gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + + led-6 { + gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo2>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_dcdc1>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11 + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10 + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_dc1sw { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-lcd"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pg_pins>; + status = "okay"; +}; + +&uart5 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart5_ph_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; From f2948781a72f0d8cf2adf31758c357f2f35e6c79 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:38 +0200 Subject: [PATCH 026/511] ARM: dts: rockchip: Fix power-controller node names for rk3066a Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 252750c97f97ff..bbc3bff508560e 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -755,7 +755,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3066_PD_VIO { + power-domain@RK3066_PD_VIO { reg = ; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -782,7 +782,7 @@ <&qos_rga>; }; - pd_video@RK3066_PD_VIDEO { + power-domain@RK3066_PD_VIDEO { reg = ; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, @@ -791,7 +791,7 @@ pm_qos = <&qos_vpu>; }; - pd_gpu@RK3066_PD_GPU { + power-domain@RK3066_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; From d3bcbcd396175ac26aa54919c0b31c7d2878fc24 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:39 +0200 Subject: [PATCH 027/511] ARM: dts: rockchip: Fix power-controller node names for rk3188 Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 2c08ae60e4a137..b6bde9d12c2be7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -699,7 +699,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3188_PD_VIO { + power-domain@RK3188_PD_VIO { reg = ; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -721,7 +721,7 @@ <&qos_rga>; }; - pd_video@RK3188_PD_VIDEO { + power-domain@RK3188_PD_VIDEO { reg = ; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, @@ -730,7 +730,7 @@ pm_qos = <&qos_vpu>; }; - pd_gpu@RK3188_PD_GPU { + power-domain@RK3188_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; From 970cdc53cb1afa73602028c103dbfb6a230080be Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:40 +0200 Subject: [PATCH 028/511] ARM: dts: rockchip: Fix power-controller node names for rk3288 Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-4-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 1e6594f8a293df..d6dbfbd995684b 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -765,7 +765,7 @@ * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio@RK3288_PD_VIO { + power-domain@RK3288_PD_VIO { reg = ; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -807,7 +807,7 @@ * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc@RK3288_PD_HEVC { + power-domain@RK3288_PD_HEVC { reg = ; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, @@ -821,7 +821,7 @@ * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video@RK3288_PD_VIDEO { + power-domain@RK3288_PD_VIDEO { reg = ; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; @@ -832,7 +832,7 @@ * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu@RK3288_PD_GPU { + power-domain@RK3288_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu_r>, From a3ec2d38f6dd922007ee4d414cf76d1f55570844 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 17 Apr 2021 13:29:41 +0200 Subject: [PATCH 029/511] ARM: dts: rockchip: add #power-domain-cells to power domain nodes Add #power-domain-cells to power domain nodes, because they are required by power-domain.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 3 +++ arch/arm/boot/dts/rk3188.dtsi | 3 +++ arch/arm/boot/dts/rk3288.dtsi | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index bbc3bff508560e..8e087c34b881b8 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -780,6 +780,7 @@ <&qos_cif1>, <&qos_ipp>, <&qos_rga>; + #power-domain-cells = <0>; }; power-domain@RK3066_PD_VIDEO { @@ -789,12 +790,14 @@ <&cru HCLK_VDPU>, <&cru HCLK_VEPU>; pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; }; power-domain@RK3066_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index b6bde9d12c2be7..f1632b820717c8 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -719,6 +719,7 @@ <&qos_cif0>, <&qos_ipp>, <&qos_rga>; + #power-domain-cells = <0>; }; power-domain@RK3188_PD_VIDEO { @@ -728,12 +729,14 @@ <&cru HCLK_VDPU>, <&cru HCLK_VEPU>; pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; }; power-domain@RK3188_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index d6dbfbd995684b..9c5a7791a1aba0 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -801,6 +801,7 @@ <&qos_vio2_rga_r>, <&qos_vio2_rga_w>, <&qos_vio1_isp_r>; + #power-domain-cells = <0>; }; /* @@ -814,6 +815,7 @@ <&cru SCLK_HEVC_CORE>; pm_qos = <&qos_hevc_r>, <&qos_hevc_w>; + #power-domain-cells = <0>; }; /* @@ -826,6 +828,7 @@ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video>; + #power-domain-cells = <0>; }; /* @@ -837,6 +840,7 @@ clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu_r>, <&qos_gpu_w>; + #power-domain-cells = <0>; }; }; From d5de0d688ac6e0202674577b05d0726b8a6af401 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:42 +0200 Subject: [PATCH 030/511] arm64: dts: rockchip: Fix power-controller node names for px30 Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-6-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 86644e24aa5f23..bcbe35a0f0eb40 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -244,20 +244,20 @@ #size-cells = <0>; /* These power domains are grouped by VD_LOGIC */ - pd_usb@PX30_PD_USB { + power-domain@PX30_PD_USB { reg = ; clocks = <&cru HCLK_HOST>, <&cru HCLK_OTG>, <&cru SCLK_OTG_ADP>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>; }; - pd_sdcard@PX30_PD_SDCARD { + power-domain@PX30_PD_SDCARD { reg = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sdmmc>; }; - pd_gmac@PX30_PD_GMAC { + power-domain@PX30_PD_GMAC { reg = ; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, @@ -265,7 +265,7 @@ <&cru SCLK_GMAC_RX_TX>; pm_qos = <&qos_gmac>; }; - pd_mmc_nand@PX30_PD_MMC_NAND { + power-domain@PX30_PD_MMC_NAND { reg = ; clocks = <&cru HCLK_NANDC>, <&cru HCLK_EMMC>, @@ -278,14 +278,14 @@ pm_qos = <&qos_emmc>, <&qos_nand>, <&qos_sdio>, <&qos_sfc>; }; - pd_vpu@PX30_PD_VPU { + power-domain@PX30_PD_VPU { reg = ; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>; }; - pd_vo@PX30_PD_VO { + power-domain@PX30_PD_VO { reg = ; clocks = <&cru ACLK_RGA>, <&cru ACLK_VOPB>, @@ -301,7 +301,7 @@ pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop_m0>, <&qos_vop_m1>; }; - pd_vi@PX30_PD_VI { + power-domain@PX30_PD_VI { reg = ; clocks = <&cru ACLK_CIF>, <&cru ACLK_ISP>, @@ -312,7 +312,7 @@ <&qos_isp_wr>, <&qos_isp_m1>, <&qos_vip>; }; - pd_gpu@PX30_PD_GPU { + power-domain@PX30_PD_GPU { reg = ; clocks = <&cru SCLK_GPU>; pm_qos = <&qos_gpu>; From 6e6a282b49c6db408d27231e3c709fbdf25e3c1b Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:43 +0200 Subject: [PATCH 031/511] arm64: dts: rockchip: Fix power-controller node names for rk3328 Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-7-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 3ed69ecbcf3cea..d2d8b675c9e949 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -300,13 +300,13 @@ #address-cells = <1>; #size-cells = <0>; - pd_hevc@RK3328_PD_HEVC { + power-domain@RK3328_PD_HEVC { reg = ; }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = ; }; - pd_vpu@RK3328_PD_VPU { + power-domain@RK3328_PD_VPU { reg = ; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; }; From 148bbe29f9108812c6fedd8a228f9e1ed6b422f7 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:44 +0200 Subject: [PATCH 032/511] arm64: dts: rockchip: Fix power-controller node names for rk3399 Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang Reviewed-by: Enric Balletbo i Serra Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-8-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 7c1b69f3a4c11d..1703817c73542a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -968,26 +968,26 @@ #size-cells = <0>; /* These power domains are grouped by VD_CENTER */ - pd_iep@RK3399_PD_IEP { + power-domain@RK3399_PD_IEP { reg = ; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; pm_qos = <&qos_iep>; }; - pd_rga@RK3399_PD_RGA { + power-domain@RK3399_PD_RGA { reg = ; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; pm_qos = <&qos_rga_r>, <&qos_rga_w>; }; - pd_vcodec@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VCODEC { reg = ; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video_m0>; }; - pd_vdu@RK3399_PD_VDU { + power-domain@RK3399_PD_VDU { reg = ; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; @@ -996,94 +996,94 @@ }; /* These power domains are grouped by VD_GPU */ - pd_gpu@RK3399_PD_GPU { + power-domain@RK3399_PD_GPU { reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; }; /* These power domains are grouped by VD_LOGIC */ - pd_edp@RK3399_PD_EDP { + power-domain@RK3399_PD_EDP { reg = ; clocks = <&cru PCLK_EDP_CTRL>; }; - pd_emmc@RK3399_PD_EMMC { + power-domain@RK3399_PD_EMMC { reg = ; clocks = <&cru ACLK_EMMC>; pm_qos = <&qos_emmc>; }; - pd_gmac@RK3399_PD_GMAC { + power-domain@RK3399_PD_GMAC { reg = ; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; - pd_sd@RK3399_PD_SD { + power-domain@RK3399_PD_SD { reg = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sd>; }; - pd_sdioaudio@RK3399_PD_SDIOAUDIO { + power-domain@RK3399_PD_SDIOAUDIO { reg = ; clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; }; - pd_tcpc0@RK3399_PD_TCPD0 { + power-domain@RK3399_PD_TCPD0 { reg = ; clocks = <&cru SCLK_UPHY0_TCPDCORE>, <&cru SCLK_UPHY0_TCPDPHY_REF>; }; - pd_tcpc1@RK3399_PD_TCPD1 { + power-domain@RK3399_PD_TCPD1 { reg = ; clocks = <&cru SCLK_UPHY1_TCPDCORE>, <&cru SCLK_UPHY1_TCPDPHY_REF>; }; - pd_usb3@RK3399_PD_USB3 { + power-domain@RK3399_PD_USB3 { reg = ; clocks = <&cru ACLK_USB3>; pm_qos = <&qos_usb_otg0>, <&qos_usb_otg1>; }; - pd_vio@RK3399_PD_VIO { + power-domain@RK3399_PD_VIO { reg = ; #address-cells = <1>; #size-cells = <0>; - pd_hdcp@RK3399_PD_HDCP { + power-domain@RK3399_PD_HDCP { reg = ; clocks = <&cru ACLK_HDCP>, <&cru HCLK_HDCP>, <&cru PCLK_HDCP>; pm_qos = <&qos_hdcp>; }; - pd_isp0@RK3399_PD_ISP0 { + power-domain@RK3399_PD_ISP0 { reg = ; clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; pm_qos = <&qos_isp0_m0>, <&qos_isp0_m1>; }; - pd_isp1@RK3399_PD_ISP1 { + power-domain@RK3399_PD_ISP1 { reg = ; clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; - pd_vo@RK3399_PD_VO { + power-domain@RK3399_PD_VO { reg = ; #address-cells = <1>; #size-cells = <0>; - pd_vopb@RK3399_PD_VOPB { + power-domain@RK3399_PD_VOPB { reg = ; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; pm_qos = <&qos_vop_big_r>, <&qos_vop_big_w>; }; - pd_vopl@RK3399_PD_VOPL { + power-domain@RK3399_PD_VOPL { reg = ; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; From 837188d49823230f47afdbbec7556740e89a8557 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 17 Apr 2021 13:29:45 +0200 Subject: [PATCH 033/511] arm64: dts: rockchip: add #power-domain-cells to power domain nodes Add #power-domain-cells to power domain nodes, because they are required by power-domain.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-9-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 +++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index bcbe35a0f0eb40..4e243d72e16fa1 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -250,12 +250,14 @@ <&cru HCLK_OTG>, <&cru SCLK_OTG_ADP>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>; + #power-domain-cells = <0>; }; power-domain@PX30_PD_SDCARD { reg = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sdmmc>; + #power-domain-cells = <0>; }; power-domain@PX30_PD_GMAC { reg = ; @@ -264,6 +266,7 @@ <&cru SCLK_MAC_REF>, <&cru SCLK_GMAC_RX_TX>; pm_qos = <&qos_gmac>; + #power-domain-cells = <0>; }; power-domain@PX30_PD_MMC_NAND { reg = ; @@ -277,6 +280,7 @@ <&cru SCLK_SFC>; pm_qos = <&qos_emmc>, <&qos_nand>, <&qos_sdio>, <&qos_sfc>; + #power-domain-cells = <0>; }; power-domain@PX30_PD_VPU { reg = ; @@ -284,6 +288,7 @@ <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>; + #power-domain-cells = <0>; }; power-domain@PX30_PD_VO { reg = ; @@ -300,6 +305,7 @@ <&cru SCLK_VOPB_PWM>; pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop_m0>, <&qos_vop_m1>; + #power-domain-cells = <0>; }; power-domain@PX30_PD_VI { reg = ; @@ -311,11 +317,13 @@ pm_qos = <&qos_isp_128>, <&qos_isp_rd>, <&qos_isp_wr>, <&qos_isp_m1>, <&qos_vip>; + #power-domain-cells = <0>; }; power-domain@PX30_PD_GPU { reg = ; clocks = <&cru SCLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index d2d8b675c9e949..4b37071a584ce8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -302,13 +302,16 @@ power-domain@RK3328_PD_HEVC { reg = ; + #power-domain-cells = <0>; }; power-domain@RK3328_PD_VIDEO { reg = ; + #power-domain-cells = <0>; }; power-domain@RK3328_PD_VPU { reg = ; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + #power-domain-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 1703817c73542a..a2eba535769398 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -973,6 +973,7 @@ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; pm_qos = <&qos_iep>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_RGA { reg = ; @@ -980,12 +981,14 @@ <&cru HCLK_RGA>; pm_qos = <&qos_rga_r>, <&qos_rga_w>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_VCODEC { reg = ; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video_m0>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_VDU { reg = ; @@ -993,6 +996,7 @@ <&cru HCLK_VDU>; pm_qos = <&qos_video_m1_r>, <&qos_video_m1_w>; + #power-domain-cells = <0>; }; /* These power domains are grouped by VD_GPU */ @@ -1000,53 +1004,63 @@ reg = ; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; /* These power domains are grouped by VD_LOGIC */ power-domain@RK3399_PD_EDP { reg = ; clocks = <&cru PCLK_EDP_CTRL>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_EMMC { reg = ; clocks = <&cru ACLK_EMMC>; pm_qos = <&qos_emmc>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_GMAC { reg = ; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_SD { reg = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sd>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_SDIOAUDIO { reg = ; clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_TCPD0 { reg = ; clocks = <&cru SCLK_UPHY0_TCPDCORE>, <&cru SCLK_UPHY0_TCPDPHY_REF>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_TCPD1 { reg = ; clocks = <&cru SCLK_UPHY1_TCPDCORE>, <&cru SCLK_UPHY1_TCPDPHY_REF>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_USB3 { reg = ; clocks = <&cru ACLK_USB3>; pm_qos = <&qos_usb_otg0>, <&qos_usb_otg1>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_VIO { reg = ; + #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1056,6 +1070,7 @@ <&cru HCLK_HDCP>, <&cru PCLK_HDCP>; pm_qos = <&qos_hdcp>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_ISP0 { reg = ; @@ -1063,6 +1078,7 @@ <&cru HCLK_ISP0>; pm_qos = <&qos_isp0_m0>, <&qos_isp0_m1>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_ISP1 { reg = ; @@ -1070,9 +1086,11 @@ <&cru HCLK_ISP1>; pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_VO { reg = ; + #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1082,12 +1100,14 @@ <&cru HCLK_VOP0>; pm_qos = <&qos_vop_big_r>, <&qos_vop_big_w>; + #power-domain-cells = <0>; }; power-domain@RK3399_PD_VOPL { reg = ; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; pm_qos = <&qos_vop_little>; + #power-domain-cells = <0>; }; }; }; From b660269cba748dfd07eb5551a88ff34d5ea0b86e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 16 Apr 2021 15:37:48 +0200 Subject: [PATCH 034/511] ARM: dts: BCM5301X: Fix NAND nodes names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches nand-controller.yaml requirements. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 4 ++-- arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 4 ++-- arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi | 4 ++-- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- arch/arm/boot/dts/bcm953012k.dts | 4 ++-- arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 8636600385fd41..c81944cd6d0bb3 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -24,8 +24,8 @@ reg = <0x00000000 0x08000000>; }; - nand: nand@18028000 { - nandcs@0 { + nand_controller: nand-controller@18028000 { + nand@0 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index e635a15041dd8c..a6e2aeb286754c 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -25,8 +25,8 @@ <0x88000000 0x08000000>; }; - nand: nand@18028000 { - nandcs@0 { + nand_controller: nand-controller@18028000 { + nand@0 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi index 925a7c9ce5b7f4..be9a00ff752d9a 100644 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi @@ -6,8 +6,8 @@ */ / { - nand@18028000 { - nandcs: nandcs@0 { + nand-controller@18028000 { + nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 7db72a2f1020d9..092ec525c01c4b 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -501,7 +501,7 @@ reg = <0x18004000 0x14>; }; - nand: nand@18028000 { + nand_controller: nand-controller@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; reg-names = "nand", "iproc-idm", "iproc-ext"; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index 046c59fb484621..de40bd59a5faf3 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -49,8 +49,8 @@ }; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index 8060178b365d86..a5a64d17d9ea6d 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -306,7 +306,7 @@ interrupt-names = "nand"; status = "okay"; - nandcs: nandcs@0 { + nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; }; From 9a800ce1aada6e0f56b78e4713f4858c8990c1f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 16 Apr 2021 15:37:49 +0200 Subject: [PATCH 035/511] ARM: brcmstb: dts: fix NAND nodes names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches nand-controller.yaml requirements. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm7445-bcm97445svmb.dts | 4 ++-- arch/arm/boot/dts/bcm7445.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts index 8313b7cad54273..f92d2cf8597269 100644 --- a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts +++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts @@ -14,10 +14,10 @@ }; }; -&nand { +&nand_controller { status = "okay"; - nandcs@1 { + nand@1 { compatible = "brcm,nandcs"; reg = <1>; nand-ecc-step-size = <512>; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index 58f67c9b830b85..5ac2042515b8f5 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -148,7 +148,7 @@ reg-names = "aon-ctrl", "aon-sram"; }; - nand: nand@3e2800 { + nand_controller: nand-controller@3e2800 { status = "disabled"; #address-cells = <1>; #size-cells = <0>; From e256b48a3b07ee1ae4bfa60abbf509ba8e386862 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 16 Apr 2021 15:37:50 +0200 Subject: [PATCH 036/511] ARM: Cygnus: dts: fix NAND nodes names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches nand-controller.yaml requirements. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 2 +- arch/arm/boot/dts/bcm911360_entphn.dts | 4 ++-- arch/arm/boot/dts/bcm958300k.dts | 4 ++-- arch/arm/boot/dts/bcm958305k.dts | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 0025c88f660cd4..8ecb7861ce106f 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -460,7 +460,7 @@ status = "disabled"; }; - nand: nand@18046000 { + nand_controller: nand-controller@18046000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index b2d323f4a5aba3..a76c74b44bbaf7 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -82,8 +82,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts index b4a1392bd5a6c6..dda3e11b711f65 100644 --- a/arch/arm/boot/dts/bcm958300k.dts +++ b/arch/arm/boot/dts/bcm958300k.dts @@ -60,8 +60,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts index 3378683321d3c8..ea3c6b88b313b2 100644 --- a/arch/arm/boot/dts/bcm958305k.dts +++ b/arch/arm/boot/dts/bcm958305k.dts @@ -68,8 +68,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; From 0484594be733d5cdf976f55a2d4e8d887f351b69 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 16 Apr 2021 15:37:51 +0200 Subject: [PATCH 037/511] ARM: NSP: dts: fix NAND nodes names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches nand-controller.yaml requirements. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- arch/arm/boot/dts/bcm958522er.dts | 4 ++-- arch/arm/boot/dts/bcm958525er.dts | 4 ++-- arch/arm/boot/dts/bcm958525xmc.dts | 4 ++-- arch/arm/boot/dts/bcm958622hr.dts | 4 ++-- arch/arm/boot/dts/bcm958623hr.dts | 4 ++-- arch/arm/boot/dts/bcm958625hr.dts | 4 ++-- arch/arm/boot/dts/bcm958625k.dts | 4 ++-- arch/arm/boot/dts/bcm988312hr.dts | 4 ++-- 9 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index b4d2cc70afb193..748df7955ae67f 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -269,7 +269,7 @@ dma-coherent; }; - nand: nand@26000 { + nand_controller: nand-controller@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, <0x11b408 0x600>, diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 5443fc079e6e4f..1f73885ec274a3 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index e1e3c26cef1909..b6b9ca8b097264 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index f161ba2e7e5e11..ecf426f6ad5d55 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -90,8 +90,8 @@ }; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index 83cb877d63dbcc..8ca18da981adfe 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -78,8 +78,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index 4e106ce1384a3e..9747378db5314f 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -78,8 +78,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index cda6cc281e186b..0f92b773afb8d3 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -89,8 +89,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index ffbff0014c6527..9e984ca0e6df42 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -68,8 +68,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index 3fd39c479a3ce3..5475dab8181d2f 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; From 75e2f012f6e34b93124d1d86eaa8f27df48e9ea0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 16 Apr 2021 15:37:52 +0200 Subject: [PATCH 038/511] ARM: dts: BCM63xx: Fix NAND nodes names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches nand-controller.yaml requirements. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm63138.dtsi | 2 +- arch/arm/boot/dts/bcm963138dvt.dts | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index 9c0325cf9e22ee..cca49a2e2d623b 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -203,7 +203,7 @@ status = "disabled"; }; - nand: nand@2000 { + nand_controller: nand-controller@2000 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index 5b177274f1826f..df5c8ab906273d 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -31,10 +31,10 @@ status = "okay"; }; -&nand { +&nand_controller { status = "okay"; - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-strength = <4>; From a4528d9029e2eda16e4fc9b9da1de1fbec10ab26 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 16 Apr 2021 15:37:53 +0200 Subject: [PATCH 039/511] ARM: dts: Hurricane 2: Fix NAND nodes names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches nand-controller.yaml requirements. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-hr2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index e8df458aad392e..84cda16f68a23a 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -179,7 +179,7 @@ status = "disabled"; }; - nand: nand@26000 { + nand_controller: nand-controller@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x26000 0x600>, <0x11b408 0x600>, From bb95d7d440fefd104c593d9cb20da6d34a474e97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 21 Apr 2021 11:00:06 +0200 Subject: [PATCH 040/511] ARM: dts: BCM5301X: Fix pinmux subnodes names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches pinmux-node.yaml requirements. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094.dtsi | 2 +- arch/arm/boot/dts/bcm5301x.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index 2a8f7312d1be14..6282363313e185 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -11,7 +11,7 @@ &pinctrl { compatible = "brcm,bcm4709-pinmux"; - pinmux_mdio: mdio { + pinmux_mdio: mdio-pins { groups = "mdio_grp"; function = "mdio"; }; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 092ec525c01c4b..5b9723a10bd66d 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -458,18 +458,18 @@ function = "spi"; }; - pinmux_i2c: i2c { + pinmux_i2c: i2c-pins { groups = "i2c_grp"; function = "i2c"; }; - pinmux_pwm: pwm { + pinmux_pwm: pwm-pins { groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; function = "pwm"; }; - pinmux_uart1: uart1 { + pinmux_uart1: uart1-pins { groups = "uart1_grp"; function = "uart1"; }; From 8f711f68cffdacb86444cf1d86292a776bf17dc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Sat, 24 Apr 2021 22:23:41 +0200 Subject: [PATCH 041/511] dt-bindings: clock: brcm, iproc-clocks: convert to the json-schema MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This helps validating DTS files. Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring Signed-off-by: Florian Fainelli --- .../bindings/clock/brcm,iproc-clocks.txt | 313 -------------- .../bindings/clock/brcm,iproc-clocks.yaml | 395 ++++++++++++++++++ 2 files changed, 395 insertions(+), 313 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt create mode 100644 Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt deleted file mode 100644 index ab730ea0a560f3..00000000000000 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ /dev/null @@ -1,313 +0,0 @@ -Broadcom iProc Family Clocks - -This binding uses the common clock binding: - Documentation/devicetree/bindings/clock/clock-bindings.txt - -The iProc clock controller manages clocks that are common to the iProc family. -An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL, -LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL -comprises of several leaf clocks - -Required properties for a PLL and its leaf clocks: - -- compatible: - Should have a value of the form "brcm,-". For example, GENPLL on -Cygnus has a compatible string of "brcm,cygnus-genpll" - -- #clock-cells: - Have a value of <1> since there are more than 1 leaf clock of a given PLL - -- reg: - Define the base and range of the I/O address space that contain the iProc -clock control registers required for the PLL - -- clocks: - The input parent clock phandle for the PLL. For most iProc PLLs, this is an -onboard crystal with a fixed rate - -- clock-output-names: - An ordered list of strings defining the names of the clocks - -Example: - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - genpll: genpll { - #clock-cells = <1>; - compatible = "brcm,cygnus-genpll"; - reg = <0x0301d000 0x2c>, <0x0301c020 0x4>; - clocks = <&osc>; - clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", - "enet_sw", "audio_125", "can"; - }; - -Required properties for ASIU clocks: - -ASIU clocks are a special case. These clocks are derived directly from the -reference clock of the onboard crystal - -- compatible: - Should have a value of the form "brcm,-asiu-clk". For example, ASIU -clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk" - -- #clock-cells: - Have a value of <1> since there are more than 1 ASIU clocks - -- reg: - Define the base and range of the I/O address space that contain the iProc -clock control registers required for ASIU clocks - -- clocks: - The input parent clock phandle for the ASIU clock, i.e., the onboard -crystal - -- clock-output-names: - An ordered list of strings defining the names of the ASIU clocks - -Example: - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - asiu_clks: asiu_clks { - #clock-cells = <1>; - compatible = "brcm,cygnus-asiu-clk"; - reg = <0x0301d048 0xc>, <0x180aa024 0x4>; - clocks = <&osc>; - clock-output-names = "keypad", "adc/touch", "pwm"; - }; - -Cygnus ------- -PLL and leaf clock compatible strings for Cygnus are: - "brcm,cygnus-armpll" - "brcm,cygnus-genpll" - "brcm,cygnus-lcpll0" - "brcm,cygnus-mipipll" - "brcm,cygnus-asiu-clk" - "brcm,cygnus-audiopll" - -The following table defines the set of PLL/clock index and ID for Cygnus. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-cygnus.h" - - Clock Source (Parent) Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK - adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK - pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK - - genpll crystal 0 BCM_CYGNUS_GENPLL - axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK - 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK - ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK - enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK - audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK - can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK - - lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 - pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK - ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK - sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK - usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK - smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK - ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED - - mipipll crystal 0 BCM_CYGNUS_MIPIPLL - ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED - ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD - ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D - ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED - ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED - ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED - - audiopll crystal 0 BCM_CYGNUS_AUDIOPLL - ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 - ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 - ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 - -Hurricane 2 ------- -PLL and leaf clock compatible strings for Hurricane 2 are: - "brcm,hr2-armpll" - -The following table defines the set of PLL/clock for Hurricane 2: - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - -Northstar and Northstar Plus ------- -PLL and leaf clock compatible strings for Northstar and Northstar Plus are: - "brcm,nsp-armpll" - "brcm,nsp-genpll" - "brcm,nsp-lcpll0" - -The following table defines the set of PLL/clock index and ID for Northstar and -Northstar Plus. These clock IDs are defined in: - "include/dt-bindings/clock/bcm-nsp.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - armpll crystal N/A N/A - - genpll crystal 0 BCM_NSP_GENPLL - phy genpll 1 BCM_NSP_GENPLL_PHY_CLK - ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK - usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK - iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK - sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK - sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK - - lcpll0 crystal 0 BCM_NSP_LCPLL0 - pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK - sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK - ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK - -Northstar 2 ------------ -PLL and leaf clock compatible strings for Northstar 2 are: - "brcm,ns2-genpll-scr" - "brcm,ns2-genpll-sw" - "brcm,ns2-lcpll-ddr" - "brcm,ns2-lcpll-ports" - -The following table defines the set of PLL/clock index and ID for Northstar 2. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-ns2.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - - genpll_scr crystal 0 BCM_NS2_GENPLL_SCR - scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK - fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK - audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK - ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED - ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED - ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED - - genpll_sw crystal 0 BCM_NS2_GENPLL_SW - rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK - 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK - nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK - chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK - port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK - sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK - - lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR - pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK - ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK - ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED - ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED - ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED - ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED - - lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS - wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK - rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK - ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED - ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED - ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED - ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED - -BCM63138 --------- -PLL and leaf clock compatible strings for BCM63138 are: - "brcm,bcm63138-armpll" - -Stingray ------------ -PLL and leaf clock compatible strings for Stingray are: - "brcm,sr-genpll0" - "brcm,sr-genpll1" - "brcm,sr-genpll2" - "brcm,sr-genpll3" - "brcm,sr-genpll4" - "brcm,sr-genpll5" - "brcm,sr-genpll6" - - "brcm,sr-lcpll0" - "brcm,sr-lcpll1" - "brcm,sr-lcpll-pcie" - - -The following table defines the set of PLL/clock index and ID for Stingray. -These clock IDs are defined in: - "include/dt-bindings/clock/bcm-sr.h" - - Clock Source Index ID - --- ----- ----- --------- - crystal N/A N/A N/A - crmu_ref25m crystal N/A N/A - - genpll0 crystal 0 BCM_SR_GENPLL0 - clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK - clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK - clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK - clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK - clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK - clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK - - genpll1 crystal 0 BCM_SR_GENPLL1 - clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK - clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK - - genpll2 crystal 0 BCM_SR_GENPLL2 - clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK - clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK - clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK - clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK - clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK - clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK - - genpll3 crystal 0 BCM_SR_GENPLL3 - clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK - clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK - - genpll4 crystal 0 BCM_SR_GENPLL4 - clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK - clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK - clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK - clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK - clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK - - genpll5 crystal 0 BCM_SR_GENPLL5 - clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK - clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK - clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK - - genpll6 crystal 0 BCM_SR_GENPLL6 - clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK - - lcpll0 crystal 0 BCM_SR_LCPLL0 - clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK - clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK - clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK - clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK - - lcpll1 crystal 0 BCM_SR_LCPLL1 - clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK - clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK - clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK - - lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE - clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml new file mode 100644 index 00000000000000..8dc7b404ee12b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml @@ -0,0 +1,395 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc Family Clocks + +maintainers: + - Ray Jui + - Scott Branden + +description: | + The iProc clock controller manages clocks that are common to the iProc family. + An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL, + LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL + comprises of several leaf clocks + + ASIU clocks are a special case. These clocks are derived directly from the + reference clock of the onboard crystal. + +properties: + compatible: + enum: + - brcm,bcm63138-armpll + - brcm,cygnus-armpll + - brcm,cygnus-genpll + - brcm,cygnus-lcpll0 + - brcm,cygnus-mipipll + - brcm,cygnus-asiu-clk + - brcm,cygnus-audiopll + - brcm,hr2-armpll + - brcm,nsp-armpll + - brcm,nsp-genpll + - brcm,nsp-lcpll0 + - brcm,ns2-genpll-scr + - brcm,ns2-genpll-sw + - brcm,ns2-lcpll-ddr + - brcm,ns2-lcpll-ports + - brcm,sr-genpll0 + - brcm,sr-genpll1 + - brcm,sr-genpll2 + - brcm,sr-genpll3 + - brcm,sr-genpll4 + - brcm,sr-genpll5 + - brcm,sr-genpll6 + - brcm,sr-lcpll0 + - brcm,sr-lcpll1 + - brcm,sr-lcpll-pcie + + reg: + minItems: 1 + maxItems: 3 + items: + - description: base register + - description: power register + - description: ASIU or split status register + + clocks: + description: The input parent clock phandle for the PLL / ASIU clock. For + most iProc PLLs, this is an onboard crystal with a fixed rate. + maxItems: 1 + + '#clock-cells': + const: 1 + + clock-output-names: + minItems: 1 + maxItems: 45 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - brcm,cygnus-armpll + - brcm,cygnus-genpll + - brcm,cygnus-lcpll0 + - brcm,cygnus-mipipll + - brcm,cygnus-asiu-clk + - brcm,cygnus-audiopll + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Cygnus. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-cygnus.h" + + Clock Source (Parent) Index ID + ----- --------------- ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK + adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK + pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK + + genpll crystal 0 BCM_CYGNUS_GENPLL + axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK + 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK + ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK + enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK + audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK + can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK + + lcpll0 crystal 0 BCM_CYGNUS_LCPLL0 + pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK + ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK + sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK + usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK + smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK + ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED + + mipipll crystal 0 BCM_CYGNUS_MIPIPLL + ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED + ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD + ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D + ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED + ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED + ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED + + audiopll crystal 0 BCM_CYGNUS_AUDIOPLL + ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0 + ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1 + ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2 + - if: + properties: + compatible: + contains: + enum: + - brcm,hr2-armpll + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock for Hurricane 2: + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + - if: + properties: + compatible: + contains: + enum: + - brcm,nsp-armpll + - brcm,nsp-genpll + - brcm,nsp-lcpll0 + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Northstar and + Northstar Plus. These clock IDs are defined in: + "include/dt-bindings/clock/bcm-nsp.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + armpll crystal N/A N/A + + genpll crystal 0 BCM_NSP_GENPLL + phy genpll 1 BCM_NSP_GENPLL_PHY_CLK + ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK + usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK + iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK + sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK + sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK + + lcpll0 crystal 0 BCM_NSP_LCPLL0 + pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK + sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK + ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK + - if: + properties: + compatible: + contains: + enum: + - brcm,ns2-genpll-scr + - brcm,ns2-genpll-sw + - brcm,ns2-lcpll-ddr + - brcm,ns2-lcpll-ports + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Northstar 2. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-ns2.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + + genpll_scr crystal 0 BCM_NS2_GENPLL_SCR + scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK + fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK + audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK + ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED + ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED + ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED + + genpll_sw crystal 0 BCM_NS2_GENPLL_SW + rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK + 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK + nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK + chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK + port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK + sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK + + lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR + pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK + ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK + ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED + ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED + ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED + ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED + + lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS + wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK + rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK + ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED + ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED + ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED + ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED + - if: + properties: + compatible: + contains: + enum: + - brcm,sr-genpll0 + - brcm,sr-genpll1 + - brcm,sr-genpll2 + - brcm,sr-genpll3 + - brcm,sr-genpll4 + - brcm,sr-genpll5 + - brcm,sr-genpll6 + - brcm,sr-lcpll0 + - brcm,sr-lcpll1 + - brcm,sr-lcpll-pcie + then: + properties: + clock-output-names: + description: | + The following table defines the set of PLL/clock index and ID for Stingray. + These clock IDs are defined in: + "include/dt-bindings/clock/bcm-sr.h" + + Clock Source Index ID + ----- ------ ----- -- + crystal N/A N/A N/A + crmu_ref25m crystal N/A N/A + + genpll0 crystal 0 BCM_SR_GENPLL0 + clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK + clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK + clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK + clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK + clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK + clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK + + genpll1 crystal 0 BCM_SR_GENPLL1 + clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK + clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK + + genpll2 crystal 0 BCM_SR_GENPLL2 + clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK + clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK + clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK + clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK + clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK + clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK + + genpll3 crystal 0 BCM_SR_GENPLL3 + clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK + clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK + + genpll4 crystal 0 BCM_SR_GENPLL4 + clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK + clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK + clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK + clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK + clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK + + genpll5 crystal 0 BCM_SR_GENPLL5 + clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK + clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK + clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK + + genpll6 crystal 0 BCM_SR_GENPLL6 + clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK + + lcpll0 crystal 0 BCM_SR_LCPLL0 + clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK + clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK + clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK + clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK + + lcpll1 crystal 0 BCM_SR_LCPLL1 + clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK + clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK + clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK + + lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE + clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK + - if: + properties: + compatible: + contains: + const: brcm,cygnus-genpll + then: + properties: + clock-output-names: + items: + - const: genpll + - const: axi21 + - const: 250mhz + - const: ihost_sys + - const: enet_sw + - const: audio_125 + - const: can + - if: + properties: + compatible: + contains: + const: brcm,nsp-lcpll0 + then: + properties: + clock-output-names: + items: + - const: lcpll0 + - const: pcie_phy + - const: sdio + - const: ddr_phy + - if: + properties: + compatible: + contains: + const: brcm,nsp-genpll + then: + properties: + clock-output-names: + items: + - const: genpll + - const: phy + - const: ethernetclk + - const: usbclk + - const: iprocfast + - const: sata1 + - const: sata2 + +required: + - reg + - clocks + - '#clock-cells' + - clock-output-names + +additionalProperties: false + +examples: + - | + osc1: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + genpll@301d000 { + #clock-cells = <1>; + compatible = "brcm,cygnus-genpll"; + reg = <0x301d000 0x2c>, <0x301c020 0x4>; + clocks = <&os1c>; + clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys", + "enet_sw", "audio_125", "can"; + }; + - | + osc2: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + asiu_clks@301d048 { + #clock-cells = <1>; + compatible = "brcm,cygnus-asiu-clk"; + reg = <0x301d048 0xc>, <0x180aa024 0x4>; + clocks = <&osc2>; + clock-output-names = "keypad", "adc/touch", "pwm"; + }; From 4ce22ad645bc6327aa32a4bfe9c6300f8e7bd745 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 10 May 2021 12:49:06 +0200 Subject: [PATCH 042/511] ARM: dts: ixp4xx: Add ethernet This adds ethernet to the IXP4xx device trees. Cc: Zoltan HERPAI Cc: Raylynn Knight Signed-off-by: Linus Walleij --- .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 19 ++++++++ .../dts/intel-ixp43x-gateworks-gw2358.dts | 19 ++++++++ arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi | 44 +++++++++++++++++++ arch/arm/boot/dts/intel-ixp4xx.dtsi | 24 +++++++++- 4 files changed, 105 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts index 8fcd95805ff462..8cacf035dc324a 100644 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts @@ -106,4 +106,23 @@ fis-index-block = <0x3f>; }; }; + + soc { + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts index ba1163a1e1e71b..f89d41b496ab23 100644 --- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts @@ -91,4 +91,23 @@ fis-index-block = <0xff>; }; }; + + soc { + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi index f8cd506659dcea..ef3696e369b8c2 100644 --- a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi +++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi @@ -30,5 +30,49 @@ interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + + /* This is known as EthA */ + ethernet@c800c000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800c000 0x1000>; + status = "disabled"; + intel,npe = <0>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + + /* This is known as EthB1 */ + ethernet@c800d000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800d000 0x1000>; + status = "disabled"; + intel,npe = <1>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + + /* This is known as EthB2 */ + ethernet@c800e000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800e000 0x1000>; + status = "disabled"; + intel,npe = <2>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + + /* This is known as EthB3 */ + ethernet@c800f000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800f000 0x1000>; + status = "disabled"; + intel,npe = <3>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; }; }; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index d4a09584f417cd..b3de0501cf6fc8 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -61,9 +61,31 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; }; - npe@c8006000 { + npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; }; + + /* This is known as EthB */ + ethernet@c8009000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc8009000 0x1000>; + status = "disabled"; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + intel,npe-handle = <&npe 1>; + }; + + /* This is known as EthC */ + ethernet@c800a000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800a000 0x1000>; + status = "disabled"; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + intel,npe-handle = <&npe 2>; + }; }; }; From fd268e371c5e7b96e20325694ffd1f99baa01118 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 29 Mar 2021 09:09:54 -0300 Subject: [PATCH 043/511] ARM: dts: imx6qdl-wandboard-revd1: Remove PAD_EIM_D22 from hog group The MX6QDL_PAD_EIM_D22 pad is already handled in the common imx6qdl-wandboard.dtsi file. Remove it from the local hog group to avoid the following runtime error: [ 0.117763] imx6q-pinctrl 20e0000.pinctrl: pin MX6Q_PAD_EIM_D22 already requested by 20e0000.pinctrl; cannot claim for regulator-usbotgvbus [ 0.117785] imx6q-pinctrl 20e0000.pinctrl: pin-42 (regulator-usbotgvbus) status -22 [ 0.117802] imx6q-pinctrl 20e0000.pinctrl: could not request pin 42 (MX6Q_PAD_EIM_D22) from group usbotgvbusgrp on device 20e0000.pinctrl [ 0.117822] reg-fixed-voltage regulator-usbotgvbus: Error applying setting, reverse things back [ 0.117844] reg-fixed-voltage: probe of regulator-usbotgvbus failed with error -22 Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi index b9b698f72b2615..bf86b639fdac3c 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi @@ -142,7 +142,6 @@ imx6qdl-wandboard { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ From bf3605187530d82ece4f22bb1f2ac53d231f41d4 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 30 Mar 2021 08:19:43 -0700 Subject: [PATCH 044/511] dt-bindings: arm: imx: add imx8mm gw7901 support The Gateworks GW7901 is an ARM based single board computer (SBC) featuring: - i.MX8M Mini SoC - LPDDR4 DRAM - eMMC FLASH - SPI FRAM - Gateworks System Controller (GSC) - Atmel ATECC Crypto Authentication - USB 2.0 - Microchip GbE Switch - Multiple multi-protocol RS232/RS485/RS422 Serial ports - onboard 802.11ac WiFi / BT - microSD socket - miniPCIe socket with PCIe, USB 2.0 and dual SIM sockets - Wide range DC power input - 802.3at PoE Acked-by: Rob Herring Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index e3c50f231d71c0..eacbc1f8d4669d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -685,6 +685,7 @@ properties: - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit + - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - const: fsl,imx8mm From 5497bc2a2bff777ce6d176650377362c0269b5eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 29 Mar 2021 14:34:09 +0200 Subject: [PATCH 045/511] arm64: dts: imx8mp-evk: Add PMIC device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The imx8mp-evk uses an PCA9450C as PMIC that supplies various regulators. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 99 ++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 2c28e589677ea1..9d777bc726aef4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -104,6 +104,92 @@ }; }; +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -229,6 +315,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 @@ -236,6 +329,12 @@ >; }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 From c67b761aac6cb4d035ac64e463628a996d98f950 Mon Sep 17 00:00:00 2001 From: Sahil Malhotra Date: Tue, 30 Mar 2021 20:20:27 +0530 Subject: [PATCH 046/511] arm64: dts: ls1028a-rdb: enable optee node optee node was disabled by default, enabling it for ls1028a-rdb. Signed-off-by: Michael Walle Signed-off-by: Sahil Malhotra Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 9322c6ad8e4aee..d7b5272725000a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -275,6 +275,10 @@ status = "okay"; }; +&optee { + status = "okay"; +}; + &sai4 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index eca06a0c3cf876..feecc49b7f8cb0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -88,7 +88,7 @@ }; firmware { - optee { + optee: optee { compatible = "linaro,optee-tz"; method = "smc"; status = "disabled"; From 2b1649a83afc917b66731a4ccaec64eca5f9861d Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 30 Mar 2021 08:19:44 -0700 Subject: [PATCH 047/511] arm64: dts: imx: Add i.mx8mm Gateworks gw7901 dts support The Gateworks GW7901 is an ARM based single board computer (SBC) featuring: - i.MX8M Mini SoC - LPDDR4 DRAM - eMMC FLASH - SPI FRAM - Gateworks System Controller (GSC) - Atmel ATECC Crypto Authentication - USB 2.0 - Microchip GbE Switch - Multiple multi-protocol RS232/RS485/RS422 Serial ports - onboard 802.11ac WiFi / BT - microSD socket - miniPCIe socket with PCIe, USB 2.0 and dual SIM sockets - Wide range DC power input - 802.3at PoE Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-venice-gw7901.dts | 1019 +++++++++++++++++ 2 files changed, 1020 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 44890d56c194d2..25806c4924cb2e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts new file mode 100644 index 00000000000000..5a1e9df39bec21 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -0,0 +1,1019 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +/dts-v1/; + +#include +#include +#include + +#include "imx8mm.dtsi" + +/ { + model = "Gateworks Venice GW7901 i.MX8MM board"; + compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; + + aliases { + ethernet0 = &fec1; + ethernet1 = &lan1; + ethernet2 = &lan2; + ethernet3 = &lan3; + ethernet4 = &lan4; + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led01_red"; + gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led01_grn"; + gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led02_red"; + gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led02_grn"; + gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-4 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led03_red"; + gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-5 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led03_grn"; + gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-6 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led04_red"; + gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-7 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led04_grn"; + gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-8 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led05_red"; + gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-9 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led05_grn"; + gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-a { + function = LED_FUNCTION_STATUS; + color = ; + label = "led06_red"; + gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-b { + function = LED_FUNCTION_STATUS; + color = ; + label = "led06_grn"; + gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator-ioexp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_ioexp>; + compatible = "regulator-fixed"; + regulator-name = "ioexp"; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator-isouart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_isouart>; + compatible = "regulator-fixed"; + regulator-name = "iso_uart"; + gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + startup-delay-us = <100>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb2_vbus: regulator-usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2>; + compatible = "regulator-fixed"; + regulator-name = "usb_usb2_vbus"; + gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_wifi: regulator-wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl>; + compatible = "regulator-fixed"; + regulator-name = "wifi"; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vin_aux1"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vin_aux2"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_0p95"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_arm"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p2"; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_dram"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + /* vdd_soc: 0.805-0.900V (typ=0.8V) */ + BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + /* vdd_arm: 0.805-1.0V (typ=0.9V) */ + BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ + BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_3p3 */ + BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_1p8 */ + BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_dram */ + BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + /* nvcc_snvs_1p8 */ + LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_snvs_0p8 */ + LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdda_1p8 */ + LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + leds_gpio: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + switch: switch@5f { + compatible = "microchip,ksz9897"; + reg = <0x5f>; + pinctrl-0 = <&pinctrl_ksz>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + phy-mode = "rgmii-id"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + reg = <0>; + label = "lan1"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan2: port@1 { + reg = <1>; + label = "lan2"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan3: port@2 { + reg = <2>; + label = "lan3"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan4: port@3 { + reg = <3>; + label = "lan4"; + local-mac-address = [00 00 00 00 00 00]; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + crypto@60 { + compatible = "atmel,atecc508a"; + reg = <0x60>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; + rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; + cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; + cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wifi>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_ksz: kszgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 + >; + }; + + pinctrl_reg_isouart: regisouartgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 + >; + }; + + pinctrl_reg_ioexp: regioexpgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 + >; + }; + + pinctrl_reg_wl: regwlgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 + >; + }; + + pinctrl_reg_usb2: regusb1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x41 + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x41 + >; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 + >; + }; + + pinctrl_uart1_gpio: uart1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 + >; + }; + + pinctrl_uart3_gpio: uart3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000041 /* RS232# */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* RS422# */ + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000041 /* RS485# */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 + MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 + >; + }; + + pinctrl_uart4_gpio: uart4gpiogrp { + fsl,pins = < + + MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&cpu_alert0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; +}; + +&cpu_crit0 { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; +}; From e0cdd26af8eb9001689a4cde4f72c61c1c4b06be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 10 Aug 2020 10:47:25 +0200 Subject: [PATCH 048/511] ARM: dts: imx25-pinfunc: Fix gpio function name for pads GPIO_[A-F] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pinfunc definitions used GPIO_A as function instead of GPIO_1_0 as done for all the other pins with GPIO functionality. Fix for consistency. There are no mainline users that needs adaption. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pinfunc.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index f984b702efc5f2..908caf81035197 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -563,15 +563,15 @@ #define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 #define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 -#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000 +#define MX25_PAD_GPIO_A__GPIO_1_0 0x1f4 0x3f0 0x000 0x00 0x000 #define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 #define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 -#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000 +#define MX25_PAD_GPIO_B__GPIO_1_1 0x1f8 0x3f4 0x000 0x00 0x000 #define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 #define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 -#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000 +#define MX25_PAD_GPIO_C__GPIO_1_2 0x1fc 0x3f8 0x000 0x00 0x000 #define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 #define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 #define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 @@ -580,18 +580,18 @@ #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 #define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 -#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 +#define MX25_PAD_GPIO_D__GPIO_1_3 0x200 0x3fc 0x000 0x00 0x000 #define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 #define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 -#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 +#define MX25_PAD_GPIO_E__GPIO_1_4 0x204 0x400 0x000 0x00 0x000 #define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 #define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 #define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 #define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 -#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000 +#define MX25_PAD_GPIO_F__GPIO_1_5 0x208 0x404 0x000 0x00 0x000 #define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 #define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 #define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 From 6914d1ba4d0acecd012ad4d4047be18434a9ab76 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 9 Mar 2021 06:31:15 +0100 Subject: [PATCH 049/511] arm64: dts: imx8mp: add flexspi node add node for the flexspi modul on imx8mp. Signed-off-by: Heiko Schocher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c2d51a46cb3cb2..dea608c8b31e9c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -37,6 +37,7 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; + spi0 = &flexspi; }; cpus { @@ -761,6 +762,21 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + compatible = "nxp,imx8mp-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, + <&clk IMX8MP_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; From 5bd15031337f544891185361899db40961d9044e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 21 Mar 2021 23:47:03 -0500 Subject: [PATCH 050/511] dt-bindings: timer: Simplify conditional expressions The sun4i timer IP block has a variable number of interrupts based on the compatible. Use enums to combine the two sections for the existing 3-interrupt variants, and to simplify adding new compatible strings. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland Reviewed-by: Rob Herring Acked-by: Daniel Lezcano Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210322044707.19479-2-samuel@sholland.org --- .../timer/allwinner,sun4i-a10-timer.yaml | 25 ++++++------------- 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml index 1c7cf32e7ac2a9..3462598e609db9 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -34,8 +34,8 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun4i-a10-timer + enum: + - allwinner,sun4i-a10-timer then: properties: @@ -46,8 +46,8 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun8i-a23-timer + enum: + - allwinner,sun8i-a23-timer then: properties: @@ -58,20 +58,9 @@ allOf: - if: properties: compatible: - items: - const: allwinner,sun8i-v3s-timer - - then: - properties: - interrupts: - minItems: 3 - maxItems: 3 - - - if: - properties: - compatible: - items: - const: allwinner,suniv-f1c100s-timer + enum: + - allwinner,sun8i-v3s-timer + - allwinner,suniv-f1c100s-timer then: properties: From bffdc0f3c26c7d9b5006326e0f7b7871d4eaaf13 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 21 Mar 2021 23:47:04 -0500 Subject: [PATCH 051/511] dt-bindings: timer: Add compatibles for sun50i timers The sun50i SoCs contain timer blocks which are useful as broadcast clockevent sources. They each have 2 interrupts, matching the A23 variant, so add the new compatible strings with the A23 compatible as a fallback. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland Reviewed-by: Rob Herring Acked-by: Daniel Lezcano Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210322044707.19479-3-samuel@sholland.org --- .../timer/allwinner,sun4i-a10-timer.yaml | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml index 3462598e609db9..53fd24bdc34e3c 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -12,11 +12,18 @@ maintainers: properties: compatible: - enum: - - allwinner,sun4i-a10-timer - - allwinner,sun8i-a23-timer - - allwinner,sun8i-v3s-timer - - allwinner,suniv-f1c100s-timer + oneOf: + - enum: + - allwinner,sun4i-a10-timer + - allwinner,sun8i-a23-timer + - allwinner,sun8i-v3s-timer + - allwinner,suniv-f1c100s-timer + - items: + - enum: + - allwinner,sun50i-a64-timer + - allwinner,sun50i-h6-timer + - allwinner,sun50i-h616-timer + - const: allwinner,sun8i-a23-timer reg: maxItems: 1 From af97dd5559c59050f452997a4328b1a794f6fd6a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 21 Mar 2021 23:47:05 -0500 Subject: [PATCH 052/511] arm64: dts: allwinner: a64: Sort watchdog node Nodes should be sorted by unit address. Move the watchdog node to the correct place, so it will be next to the timer node when that is added. Signed-off-by: Samuel Holland Acked-by: Daniel Lezcano Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210322044707.19479-4-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 5b30e6c1fa05d0..96525e3b5f9b34 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -799,6 +799,14 @@ }; }; + wdt0: watchdog@1c20ca0 { + compatible = "allwinner,sun50i-a64-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-spdif", @@ -1325,13 +1333,5 @@ #address-cells = <1>; #size-cells = <0>; }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun50i-a64-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; }; }; From 12bcaacaff49fc18612a7df21b76235ca8eb5c7f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 21 Mar 2021 23:47:06 -0500 Subject: [PATCH 053/511] arm64: dts: allwinner: Add sun4i MMIO timer nodes For a CPU to enter an idle state, some timer must be available to trigger an IRQ and wake it back up. The local ARM architectural timer is not sufficient, because that timer stops when the CPU is powered down. The ARM architectural timer from some other CPU can be used, but doing so prevents that other CPU from entering an idle state. For all CPUs to power down at the same time, Linux needs a timer which is not tied to any CPU. Hook up the "sun4i" timer so it can be used for this purpose. It runs at 24 MHz, which balances resolution and power consumption. Signed-off-by: Samuel Holland Acked-by: Daniel Lezcano Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210322044707.19479-5-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 96525e3b5f9b34..08b37d0af52999 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -799,6 +799,15 @@ }; }; + timer@1c20c00 { + compatible = "allwinner,sun50i-a64-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + wdt0: watchdog@1c20ca0 { compatible = "allwinner,sun50i-a64-wdt", "allwinner,sun6i-a31-wdt"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 50815867ce7b18..30d396e8c7629e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -271,6 +271,15 @@ }; }; + timer@3009000 { + compatible = "allwinner,sun50i-h6-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x03009000 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h6-wdt", "allwinner,sun6i-a31-wdt"; From d88834bfefdeb8f2456934b662613dbe3bae58df Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:53 -0500 Subject: [PATCH 054/511] ASoC: dt-bindings: sun8i-codec: Increase #sound-dai-cells Increase sound-dai-cells to 1 to allow using the DAIs in the codec corresponding to AIF2 and AIF3. The generic ASoC OF code supports a #sound-dai-cells value of 0 or 1 with no impact to the driver, so this is a backward-compatible change. Signed-off-by: Samuel Holland Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-2-samuel@sholland.org --- .../bindings/sound/allwinner,sun8i-a33-codec.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml index 67405e6d816857..19f111f4022572 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -12,7 +12,11 @@ maintainers: properties: "#sound-dai-cells": - const: 0 + minimum: 0 + maximum: 1 + description: + A value of 0 is deprecated. When used, it only allows access to + the ADC/DAC and AIF1 (the CPU DAI), not the other two AIFs/DAIs. compatible: oneOf: @@ -50,7 +54,7 @@ additionalProperties: false examples: - | audio-codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = <0 29 4>; From a691acabac36ea9966c41780d60ee2689c1cead7 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:54 -0500 Subject: [PATCH 055/511] ARM: dts: sun8i-a33: Allow using multiple codec DAIs Increase #sound-dai-cells on the digital codec to allow using the other DAIs provided by the codec for AIF2 and AIF3. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-3-samuel@sholland.org --- arch/arm/boot/dts/sun8i-a33.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 7344c37107c6d3..2beddbb3c51833 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -198,7 +198,7 @@ }; link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&codec 0>; }; }; @@ -238,7 +238,7 @@ }; codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = ; From e0cd8e0118157b0e2ae970dd9141722225fbd9a4 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:55 -0500 Subject: [PATCH 056/511] arm64: dts: allwinner: a64: Allow using multiple codec DAIs Increase #sound-dai-cells on the digital codec to allow using the other DAIs provided by the codec for AIF2 and AIF3. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-4-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 08b37d0af52999..8d549b7b28c8aa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -150,7 +150,7 @@ }; link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&codec 0>; }; }; @@ -897,7 +897,7 @@ }; codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun50i-a64-codec", "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x600>; From 09e0a7ea75e0dcde8db975be52a690663d67c256 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:56 -0500 Subject: [PATCH 057/511] arm64: dts: allwinner: a64: Add pinmux nodes for AIF2/AIF3 Now that the sun8i-codec driver supports AIF2 and AIF3, boards can use them in DAI links. Add the necessary pinmux nodes. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-5-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8d549b7b28c8aa..34bb455c0f07d6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -659,6 +659,18 @@ interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + aif2_pins: aif2-pins { + pins = "PB4", "PB5", "PB6", "PB7"; + function = "aif2"; + }; + + /omit-if-no-ref/ + aif3_pins: aif3-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "aif3"; + }; + csi_pins: csi-pins { pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; From 984a51c5308c907ee934e9521cc7a0b3835a1f6e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:57 -0500 Subject: [PATCH 058/511] arm64: dts: allwinner: a64: Allow multiple DAI links simple-audio-card supports either a single DAI link at the top level, or subnodes with one or more DAI links. To use the secondary AIFs on the codec, we need to add additional DAI links to the same sound card, so we need to use the other binding. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-6-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23 +++++++++++-------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 34bb455c0f07d6..6ddb717f2f9805 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -131,12 +131,10 @@ }; sound: sound { + #address-cells = <1>; + #size-cells = <0>; compatible = "simple-audio-card"; simple-audio-card,name = "sun50i-a64-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = "Left DAC", "DACL", @@ -145,12 +143,19 @@ "ADCR", "Right ADC"; status = "disabled"; - cpudai: simple-audio-card,cpu { - sound-dai = <&dai>; - }; + simple-audio-card,dai-link@0 { + format = "i2s"; + frame-master = <&link0_cpu>; + bitclock-master = <&link0_cpu>; + mclk-fs = <128>; - link_codec: simple-audio-card,codec { - sound-dai = <&codec 0>; + link0_cpu: cpu { + sound-dai = <&dai>; + }; + + link0_codec: codec { + sound-dai = <&codec 0>; + }; }; }; From 36777d962082bdfd2f8e45d5cd748b21838d76cc Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Apr 2021 22:58:58 -0500 Subject: [PATCH 059/511] arm64: dts: allwinner: pinephone: Add support for Bluetooth audio The PinePhone has a Bluetooth chip with its PCM interface connected to AIF3. Add the DAI link so headeset audio can be routed in hardware. Even though the link is 16 bit PCM, configuring the link a 32-bit slot is required for compatibility with AIF2, which also uses a 32-bit slot, and which shares clock dividers with AIF3. Using equal clock frequencies allows the modem and headset to be used at the same time. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-7-samuel@sholland.org --- .../dts/allwinner/sun50i-a64-pinephone.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 79adea3f8cc16a..4759cd97684389 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -25,6 +25,11 @@ /* Backlight configuration differs per PinePhone revision. */ }; + bt_sco_codec: bt-sco-codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -91,6 +96,8 @@ }; &codec { + pinctrl-names = "default"; + pinctrl-0 = <&aif3_pins>; status = "okay"; }; @@ -447,6 +454,23 @@ "MIC1", "Internal Microphone", "Headset Microphone", "HBIAS", "MIC2", "Headset Microphone"; + + simple-audio-card,dai-link@2 { + format = "dsp_a"; + frame-master = <&link2_codec>; + bitclock-master = <&link2_codec>; + bitclock-inversion; + + link2_cpu: cpu { + sound-dai = <&bt_sco_codec 0>; + }; + + link2_codec: codec { + sound-dai = <&codec 2>; + dai-tdm-slot-num = <1>; + dai-tdm-slot-width = <32>; + }; + }; }; &uart0 { From cc29e39412b9a78b43f7dfa09d739f8ba9fa7984 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 May 2021 09:59:37 -0400 Subject: [PATCH 060/511] ARM: dts: exynos: align Broadcom WiFi with dtschema The Broadcom BCM4329 family dtschema expects devices to be compatible also with brcm,bcm4329-fmac: arch/arm/boot/dts/exynos3250-rinato.dt.yaml: wifi@1: compatible: 'oneOf' conditional failed, one must be fixed: ['brcm,bcm4334-fmac'] is too short 'brcm,bcm4329-fmac' was expected Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210505135941.59898-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos3250-rinato.dts | 2 +- arch/arm/boot/dts/exynos4210-i9100.dts | 2 +- arch/arm/boot/dts/exynos4210-trats.dts | 2 +- arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index c52b9cf4f74c2b..f6ba5e42604043 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -653,7 +653,7 @@ mmc-pwrseq = <&wlan_pwrseq>; brcmf: wifi@1 { - compatible = "brcm,bcm4334-fmac"; + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx1>; diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 525ff3d2fac342..db70f62cc08fcc 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -806,7 +806,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index d2406c9146b807..3eb8df319246c9 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -521,7 +521,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index dd44ad2c6ad646..f052853244a4c2 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -614,7 +614,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; From 8bceb2a490bb8e1048e9c73520f49a65823108a4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 May 2021 09:59:38 -0400 Subject: [PATCH 061/511] ARM: dts: exynos: replace legacy MMS114 touchscreen x/y properties in GT-N7100 Replace legacy MMS114 touchscreen properties to fix dtschema warnings: arch/arm/boot/dts/exynos4412-n710x.dt.yaml: touchscreen@48: 'x-size', 'y-size' do not match any of the regexes: 'pinctrl-[0-9]+' arch/arm/boot/dts/exynos4412-n710x.dt.yaml: touchscreen@48: 'touchscreen-size-x' is a required property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210505135941.59898-2-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos4412-n710x.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index c49dbb7847b8da..2c792142605c28 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -50,8 +50,8 @@ reg = <0x48>; interrupt-parent = <&gpm2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - x-size = <720>; - y-size = <1280>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; avdd-supply = <&ldo23_reg>; vdd-supply = <&ldo24_reg>; }; From 75121e1dc9fe4def41e63d57f6a53749b88006ed Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 May 2021 09:59:39 -0400 Subject: [PATCH 062/511] ARM: dts: exynos: fix PWM LED max brightness on Odroid XU/XU3 There is no "max_brightness" property. This brings the intentional brightness reduce of green LED and dtschema checks as well: arch/arm/boot/dts/exynos5410-odroidxu.dt.yaml: led-controller-1: led-1: 'max-brightness' is a required property Fixes: 719f39fec586 ("ARM: dts: exynos5422-odroidxu3: Hook up PWM and use it for LEDs") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210505135941.59898-3-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi index 2fc3e86dc5f704..982752e1df24a5 100644 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -22,7 +22,7 @@ * Green LED is much brighter than the others * so limit its max brightness */ - max_brightness = <127>; + max-brightness = <127>; linux,default-trigger = "mmc0"; }; @@ -30,7 +30,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; From a7e59c84cf2055a1894f45855c8319191f2fa59e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 May 2021 09:59:40 -0400 Subject: [PATCH 063/511] ARM: dts: exynos: fix PWM LED max brightness on Odroid HC1 There is no "max_brightness" property as pointed out by dtschema: arch/arm/boot/dts/exynos5422-odroidhc1.dt.yaml: led-controller: led-1: 'max-brightness' is a required property Fixes: 1ac49427b566 ("ARM: dts: exynos: Add support for Hardkernel's Odroid HC1 board") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210505135941.59898-4-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5422-odroidhc1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index 20c222b33f98ee..d91f7fa2cf8088 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -22,7 +22,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; From fd2f1717966535b7d0b6fe45cf0d79e94330da5f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 May 2021 09:59:41 -0400 Subject: [PATCH 064/511] ARM: dts: exynos: fix PWM LED max brightness on Odroid XU4 There is no "max_brightness" property as pointed out by dtschema: arch/arm/boot/dts/exynos5422-odroidxu4.dt.yaml: led-controller: led-1: 'max-brightness' is a required property Fixes: 6658356014cb ("ARM: dts: Add support Odroid XU4 board for exynos5422-odroidxu4") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210505135941.59898-5-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index ede7822576436d..1c24f9b35973f7 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -24,7 +24,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; From 8b7e0f72ef7123460b31fbe0652e1871603d2b70 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 6 May 2021 11:20:44 -0400 Subject: [PATCH 065/511] ARM: dts: s5pv210: remove unused Atmel touchscreen properties in Goni The Atmel bindings and driver do not use custom properties like x/y-size, burst length, threshold and so on. The driver gets necessary data from the device directly. Remove unused properties to fix dtbs_check warning: arch/arm/boot/dts/s5pv210-goni.dt.yaml: touchscreen@4a: 'atmel,burst-length', 'atmel,orientation', 'atmel,threshold', 'atmel,x-line', 'atmel,x-size', 'atmel,y-line', 'atmel,y-size' do not match any of the regexes Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210506152044.37579-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/s5pv210-goni.dts | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index 5c1e12d39747bf..c6f39147cb9600 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -358,15 +358,6 @@ reg = <0x4a>; interrupt-parent = <&gpj0>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - - atmel,x-line = <17>; - atmel,y-line = <11>; - atmel,x-size = <800>; - atmel,y-size = <480>; - atmel,burst-length = <0x21>; - atmel,threshold = <0x28>; - atmel,orientation = <1>; - vdd-supply = <&tsp_reg>; }; }; From a1972739c01612adee6bb0a0306ea29be0bb4955 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:33 +0200 Subject: [PATCH 066/511] ARM: dts: exynos: enable PMIC wakeup from suspend on Itop Core The RTC on S5M8767 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-1-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index 4583d342af399f..b3726d4d7d9385 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -163,6 +163,7 @@ <1025000>, <950000>, <918750>, <900000>, <875000>, <831250>; + wakeup-source; regulators { ldo1_reg: LDO1 { From 765210e19859fcd83dad26441a5c499c0fe27e28 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:34 +0200 Subject: [PATCH 067/511] ARM: dts: exynos: enable PMIC wakeup from suspend on Origen4412 The RTC on S5M8767 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-2-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos4412-origen.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e1f6de53e20e15..5479ef09f9f360 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -144,6 +144,7 @@ <1200000>, <1200000>, <1200000>, <1200000>, <1200000>, <1200000>; + wakeup-source; s5m8767_osc: clocks { compatible = "samsung,s5m8767-clk"; From 0272619bde229386edf9f1358470e265628d1653 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:35 +0200 Subject: [PATCH 068/511] ARM: dts: exynos: enable PMIC wakeup from suspend on Arndale The RTC on S5M8767 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-3-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5250-arndale.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index a161f6237c7f61..a771542e28b8a1 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -218,6 +218,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s5m8767_irq>; + wakeup-source; vinb1-supply = <&main_dc_reg>; vinb2-supply = <&main_dc_reg>; From 760ebb8a2529f92f772424c7ddc385a07a9e90a0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:36 +0200 Subject: [PATCH 069/511] ARM: dts: exynos: enable PMIC wakeup from suspend on Odroid XU The RTC on Maxim max77802 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-4-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 949c0721cdb419..884fef55836cff 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -190,6 +190,7 @@ pinctrl-names = "default"; pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + wakeup-source; #clock-cells = <1>; inl1-supply = <&buck5_reg>; From 7f23ea1265c3dc2cd5824f67498078fa23ede782 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:37 +0200 Subject: [PATCH 070/511] ARM: dts: exynos: enable PMIC wakeup from suspend on Midas The RTC on Maxim max77686 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-5-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos4412-midas.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index fc77c1bfd844e6..968c7943653e24 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -668,6 +668,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&max77686_irq>; pinctrl-names = "default"; + wakeup-source; reg = <0x09>; #clock-cells = <1>; From 1178f7127a4679db9b70eb16737627f764d7a9c5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:38 +0200 Subject: [PATCH 071/511] ARM: dts: exynos: enable PMIC wakeup from suspend on Odroid X/U3 The RTC on Maxim max77686 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-6-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 5bd05866d7a348..5b1d4591b35c23 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -282,6 +282,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; + wakeup-source; reg = <0x09>; #clock-cells = <1>; From 9614ae53753003e7a4ecf800db3da189c0f0acd5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:39 +0200 Subject: [PATCH 072/511] ARM: dts: exynos: enable PMIC wakeup from suspend on P4 Note The RTC on Maxim max77686 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-7-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos4412-p4note.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 9e750890edb87b..22c3086e00769d 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -325,6 +325,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&max77686_irq>; pinctrl-names = "default"; + wakeup-source; reg = <0x09>; #clock-cells = <1>; From 1d4203b1fa02fca97ca97484f2a43da187112ad1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:40 +0200 Subject: [PATCH 073/511] ARM: dts: exynos: enable PMIC wakeup from suspend on Arndale Octa The RTC on S2MPS11 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-8-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 1aad4859c5f146..dfc7f14f5772ff 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -352,6 +352,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s2mps11_irq>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; From a145cc05cb2ccbdde2621c91c7d56c3435d3a125 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:41 +0200 Subject: [PATCH 074/511] ARM: dts: exynos: enable PMIC wakeup from suspend on SMDK5420 The RTC on S2MPS11 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-9-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5420-smdk5420.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index d506da9fa66156..a4f0e3ffedbd30 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -132,6 +132,7 @@ pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; From e4c9b60b271ce428d97577502be9393bdc46dd94 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 20 Apr 2021 18:49:42 +0200 Subject: [PATCH 075/511] ARM: dts: exynos: enable PMIC wakeup from suspend on Odroid XU3/XU4 family The RTC on S2MPS11 PMIC on Odroid XU3/XU4 family of boards can wakeup the system from suspend to RAM. Add a generic property for this. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-10-krzysztof.kozlowski@canonical.com --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 6d690b1db09944..e7958dbecfd27f 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -512,6 +512,7 @@ interrupts = <4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s2mps11_irq>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; From 152b7a599674d27f26bec1a4fdbac63564d0fc93 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 3 May 2021 00:09:52 +0200 Subject: [PATCH 076/511] ARM: dts: ixp4xx: Add PCI hosts This adds a basic PCI host definition to the base device tree for IXP4xx and then further details it in the 42x and 43x device tree include, also the specific target devices NSLU2 and GW2358 get proper PCI swizzling defined. Cc: Zoltan HERPAI Cc: Raylynn Knight Signed-off-by: Linus Walleij --- .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 25 +++++++++++ arch/arm/boot/dts/intel-ixp42x.dtsi | 4 ++ .../dts/intel-ixp43x-gateworks-gw2358.dts | 44 +++++++++++++++++++ arch/arm/boot/dts/intel-ixp43x.dtsi | 4 ++ arch/arm/boot/dts/intel-ixp4xx.dtsi | 36 +++++++++++++++ 5 files changed, 113 insertions(+) diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts index 8cacf035dc324a..af9a2b0fe53990 100644 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts @@ -108,6 +108,31 @@ }; soc { + pci@c0000000 { + status = "ok"; + + /* + * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant + * We have slots (IDSEL) 1, 2 and 3. + */ + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */ + <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */ + <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */ + <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */ + }; + ethernet@c8009000 { status = "ok"; queue-rx = <&qmgr 3>; diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi index a9622ca850ccc0..5fa063ed396cfe 100644 --- a/arch/arm/boot/dts/intel-ixp42x.dtsi +++ b/arch/arm/boot/dts/intel-ixp42x.dtsi @@ -7,6 +7,10 @@ / { soc { + pci@c0000000 { + compatible = "intel,ixp42x-pci"; + }; + interrupt-controller@c8003000 { compatible = "intel,ixp42x-interrupt"; }; diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts index f89d41b496ab23..130a245a77e689 100644 --- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts @@ -93,6 +93,50 @@ }; soc { + pci@c0000000 { + status = "ok"; + + /* + * In the boardfile for the Cambria from OpenWRT the interrupts + * are assigned one per IDSEL, so all 4 interrupts from IDSEL + * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2 + * connected to IRQ 10 etc. I find this highly unlikely so I + * have instead assumed that they are rotated (swizzled) like + * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc. + */ + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */ + <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */ + <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */ + <0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */ + /* IDSEL 4 */ + <0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */ + <0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */ + <0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */ + <0x2000 0 0 4 &gpio0 9 3>, /* INT D on slot 3 is irq 9 */ + /* IDSEL 6 */ + <0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */ + <0x3000 0 0 2 &gpio0 9 3>, /* INT B on slot 3 is irq 9 */ + <0x3000 0 0 3 &gpio0 8 3>, /* INT C on slot 3 is irq 8 */ + <0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */ + /* IDSEL 15 */ + <0x7800 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */ + <0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */ + <0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */ + <0x7800 0 0 4 &gpio0 9 3>; /* INT D on slot 3 is irq 9 */ + }; + ethernet@c800a000 { status = "ok"; queue-rx = <&qmgr 4>; diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel-ixp43x.dtsi index 494fb2ff57a007..1d0817c6e3f93b 100644 --- a/arch/arm/boot/dts/intel-ixp43x.dtsi +++ b/arch/arm/boot/dts/intel-ixp43x.dtsi @@ -8,6 +8,10 @@ / { soc { + pci@c0000000 { + compatible = "intel,ixp43x-pci"; + }; + interrupt-controller@c8003000 { compatible = "intel,ixp43x-interrupt"; }; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index b3de0501cf6fc8..edfd81d9f3dab0 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -20,6 +20,42 @@ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; }; + pci@c0000000 { + /* compatible filled in by per-soc device tree */ + reg = <0xc0000000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>, + <10 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + status = "disabled"; + + ranges = + /* + * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff + * done in 4 chunks of 16MB each. + */ + <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, + /* 64KB I/O space at 0x4c000000 */ + <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; + + /* + * This needs to map to the start of physical memory so + * PCI devices can see all (hopefully) memory. This is done + * using 4 1:1 16MB windows, so the RAM should not be more than + * 64 MB for this to work. If your memory is anywhere else + * than at 0x0 you need to alter this. + */ + dma-ranges = + <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + /* Each unique DTS using PCI must specify the swizzling */ + }; + uart0: serial@c8000000 { compatible = "intel,xscale-uart"; reg = <0xc8000000 0x1000>; From 3babb604a8545a2551772c656cbebd6f40321861 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 11 May 2021 09:44:58 +0200 Subject: [PATCH 077/511] ARM: dts: ixp4xx: Create a proper expansion bus The IXP4xx expansion bus is 24 bits (256 MB) that is memory mapped between 0x50000000-0x5fffffff usin a set of chip selects. The size of the windows is 16 or 32MB defined by the boot loader system configuration at runtime. Create a rudimentary simple-bus and move the flash memories to the expansion bus, inside the SoC. Cc: Zoltan HERPAI Cc: Raylynn Knight Signed-off-by: Linus Walleij --- .../boot/dts/intel-ixp42x-linksys-nslu2.dts | 34 ++++++++++--------- .../dts/intel-ixp43x-gateworks-gw2358.dts | 32 +++++++++-------- arch/arm/boot/dts/intel-ixp4xx.dtsi | 13 +++++++ 3 files changed, 48 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts index af9a2b0fe53990..46dda0a895e747 100644 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts @@ -90,24 +90,26 @@ timeout-ms = <5000>; }; - /* The first 16MB region on the expansion bus */ - flash@50000000 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 8 MB of Flash in 0x20000 byte blocks - * mapped in at 0x50000000 - */ - reg = <0x50000000 0x800000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; + soc { + bus@50000000 { + /* The first 16MB region at CS0 on the expansion bus */ + flash@0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of Flash in 0x20000 byte blocks + * mapped in at CS0. + */ + reg = <0x00000000 0x800000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; }; - }; - soc { pci@c0000000 { status = "ok"; diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts index 130a245a77e689..581ff18a2310be 100644 --- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts @@ -76,23 +76,25 @@ }; }; - flash@50000000 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 32 MB of Flash in 0x20000 byte blocks - * mapped in at 0x50000000 - */ - reg = <0x50000000 0x2000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x1fe0000 */ - fis-index-block = <0xff>; + soc { + bus@50000000 { + flash@0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 32 MB of Flash in 0x20000 byte blocks + * mapped in at CS0. + */ + reg = <0x00000000 0x2000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x1fe0000 */ + fis-index-block = <0xff>; + }; + }; }; - }; - soc { pci@c0000000 { status = "ok"; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index edfd81d9f3dab0..31371c65ad6d8b 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -14,6 +14,19 @@ compatible = "simple-bus"; interrupt-parent = <&intcon>; + /* + * The IXP4xx expansion bus is a set of 16 or 32MB + * windows in the 256MB space from 0x50000000 to + * 0x5fffffff. + */ + bus@50000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x50000000 0x10000000>; + dma-ranges = <0x00000000 0x50000000 0x10000000>; + }; + qmgr: queue-manager@60000000 { compatible = "intel,ixp4xx-ahb-queue-manager"; reg = <0x60000000 0x4000>; From e6f73028db511ec6e093e2b79210ca5b19c7e6c5 Mon Sep 17 00:00:00 2001 From: Irui Wang Date: Thu, 25 Mar 2021 20:26:24 +0800 Subject: [PATCH 078/511] arm64: dts: mt8173: Separating mtk-vcodec-enc device node There are two separate hardware encoder blocks inside MT8173. Split the current mtk-vcodec-enc node to match the hardware architecture. Signed-off-by: Hsin-Yi Wang Signed-off-by: Maoguang Meng Signed-off-by: Irui Wang Acked-by: Tiffany Lin Link: https://lore.kernel.org/r/20210325122625.15100-2-irui.wang@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60 ++++++++++++------------ 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 003a5653c505d6..22f271b1f5b02d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1459,14 +1459,11 @@ clock-names = "apb", "smi"; }; - vcodec_enc: vcodec@18002000 { + vcodec_enc_avc: vcodec@18002000 { compatible = "mediatek,mt8173-vcodec-enc"; - reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ - interrupts = , - ; - mediatek,larb = <&larb3>, - <&larb5>; + reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ + interrupts = ; + mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_VENC_RCPU>, <&iommu M4U_PORT_VENC_REC>, <&iommu M4U_PORT_VENC_BSDMA>, @@ -1477,29 +1474,12 @@ <&iommu M4U_PORT_VENC_REF_LUMA>, <&iommu M4U_PORT_VENC_REF_CHROMA>, <&iommu M4U_PORT_VENC_NBM_RDMA>, - <&iommu M4U_PORT_VENC_NBM_WDMA>, - <&iommu M4U_PORT_VENC_RCPU_SET2>, - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, - <&iommu M4U_PORT_VENC_BSDMA_SET2>, - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + <&iommu M4U_PORT_VENC_NBM_WDMA>; mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_UNIVPLL1_D2>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "venc_sel_src", - "venc_sel", - "venc_lt_sel_src", - "venc_lt_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>, - <&topckgen CLK_TOP_VCODECPLL_370P5>; + clocks = <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; }; jpegdec: jpegdec@18004000 { @@ -1531,5 +1511,27 @@ <&vencltsys CLK_VENCLT_CKE0>; clock-names = "apb", "smi"; }; + + vcodec_enc_vp8: vcodec@19002000 { + compatible = "mediatek,mt8173-vcodec-enc-vp8"; + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = ; + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + mediatek,larb = <&larb5>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = + <&topckgen CLK_TOP_VCODECPLL_370P5>; + }; }; }; From 763e13f26894e3693ed9a72fbc796ed1e23c1e5b Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 5 Apr 2021 19:28:36 +0200 Subject: [PATCH 079/511] arm64: dts: mediatek: mt8167: add power domains Add support for the MT8167 power domains. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210405172836.2038526-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 1c5639ead622ce..156fbdad01fbdc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include "mt8167-pinfunc.h" @@ -34,6 +35,73 @@ #clock-cells = <1>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + spm: power-controller { + compatible = "mediatek,mt8167-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8167_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_SMI_MM>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8167_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_SMI_MM>, + <&topckgen CLK_TOP_RG_VDEC>; + clock-names = "mm", "vdec"; + #power-domain-cells = <0>; + }; + + power-domain@MT8167_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_SMI_MM>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, + <&topckgen CLK_TOP_RG_SLOW_MFG>; + clock-names = "axi_mfg", "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,infracfg = <&infracfg>; + + power-domain@MT8167_POWER_DOMAIN_MFG_2D { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8167_POWER_DOMAIN_MFG { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + + power-domain@MT8167_POWER_DOMAIN_CONN { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8167-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; From 97e37d44d35e14a74f989ec13d8587c37f3f0c75 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 5 Apr 2021 22:08:17 +0200 Subject: [PATCH 080/511] arm64: dts: mediatek: mt8167: add mmsys node Add node for MMSYS. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210405200821.2203458-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 156fbdad01fbdc..9d765034dfb01f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -125,5 +125,11 @@ #interrupt-cells = <2>; interrupts = ; }; + + mmsys: mmsys@14000000 { + compatible = "mediatek,mt8167-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; }; }; From e7ead62e2a1e574bf14b90dfcd2a74ba314a0c4d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 5 Apr 2021 22:08:18 +0200 Subject: [PATCH 081/511] arm64: dts: mediatek: mt8167: add smi_common node Add the smi_common node. Reported-by: kernel test robot Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210405200821.2203458-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 9d765034dfb01f..4b951f81db9e1e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -131,5 +131,14 @@ reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; + + smi_common: smi@14017000 { + compatible = "mediatek,mt8167-smi-common"; + reg = <0 0x14017000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; }; }; From 1a191c97abef9b8afcec95a9ede253df184e84bc Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 6 Apr 2021 13:36:28 +0200 Subject: [PATCH 082/511] arm64: dts: mediatek: mt8167: add larb nodes Add larb nodes for MT8167: * larb0 is used for display (dsi and hdmi) * larb1 is used for camera (csi) * larb2 is used for the video hardware decoder Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210406113631.2675029-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 4b951f81db9e1e..bbddd4b22d3e3b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -140,5 +140,35 @@ clock-names = "apb", "smi"; power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; + + larb0: larb@14016000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x14016000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + larb1: larb@15001000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB1_SMI>, + <&imgsys CLK_IMG_LARB1_SMI>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; + }; + + larb2: larb@16010000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; + }; }; }; From d9fb91fdfdda2c30c94f66cd55d39a693505b185 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 6 Apr 2021 13:36:29 +0200 Subject: [PATCH 083/511] arm64: dts: mediatek: mt8167: add iommu node Add node for the MT8167's IOMMU. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210406113631.2675029-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index bbddd4b22d3e3b..9029051624a678 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -170,5 +170,13 @@ clock-names = "apb", "smi"; power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; }; + + iommu: m4u@10203000 { + compatible = "mediatek,mt8167-m4u"; + reg = <0 0x10203000 0 0x1000>; + mediatek,larbs = <&larb0 &larb1 &larb2>; + interrupts = ; + #iommu-cells = <1>; + }; }; }; From 4eab77fc8ae77316417b987ad16e67d2bc739cc5 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:05:52 +0800 Subject: [PATCH 084/511] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kappa Kappa is known as HP Chromebook 11a. Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210421090601.730744-2-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index aff57a8c8c30bf..81b86b189a8d18 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -144,6 +144,10 @@ properties: - const: google,kakadu-rev2 - const: google,kakadu - const: mediatek,mt8183 + - description: Google Kappa (HP Chromebook 11a) + items: + - const: google,kappa + - const: mediatek,mt8183 - description: Google Kodama (Lenovo 10e Chromebook Tablet) items: - enum: From 82665ef7dd65ce3b0c2e579df08f17708b728f2e Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:05:53 +0800 Subject: [PATCH 085/511] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-willow Willow is known as Acer Chromebook 311 (C722/C722T). Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210421090601.730744-3-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 81b86b189a8d18..96c401597bd8d3 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -157,6 +157,13 @@ properties: - google,kodama-sku32 - const: google,kodama - const: mediatek,mt8183 + - description: Google Willow (Acer Chromebook 311 C722/C722T) + items: + - enum: + - google,willow-sku0 + - google,willow-sku1 + - const: google,willow + - const: mediatek,mt8183 - items: - enum: - mediatek,mt8183-pumpkin From 204c134818498985c1d235a294af5803d5cce1da Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:05:54 +0800 Subject: [PATCH 086/511] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-burnet Burnet is known as HP Chromebook x360 11MK G3 EE. Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210421090601.730744-4-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 96c401597bd8d3..0870490aa35028 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -122,6 +122,10 @@ properties: - enum: - mediatek,mt8195-evb - const: mediatek,mt8195 + - description: Google Burnet (HP Chromebook x360 11MK G3 EE) + items: + - const: google,burnet + - const: mediatek,mt8183 - description: Google Krane (Lenovo IdeaPad Duet, 10e,...) items: - enum: From ffea8b5b89f1d2ed14d84289aa48cbaef7f31a52 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:05:55 +0800 Subject: [PATCH 087/511] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kenzo Kenzo is known as Acer Chromebook 311. Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210421090601.730744-5-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 0870490aa35028..7afd01aad9647b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -137,9 +137,11 @@ properties: items: - const: google,damu - const: mediatek,mt8183 - - description: Google Juniper (Acer Chromebook Spin 311) + - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311) items: - - const: google,juniper-sku16 + - enum: + - google,juniper-sku16 + - google,juniper-sku17 - const: google,juniper - const: mediatek,mt8183 - description: Google Kakadu (ASUS Chromebook Detachable CM3) From 009add139c2e1942e49cc576ed1655f5313b5fe4 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:05:56 +0800 Subject: [PATCH 088/511] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-fennel Fennel is known as Lenovo IdeaPad Flex 3 Chromebook. Signed-off-by: Hsin-Yi Wang Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210421090601.730744-6-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 7afd01aad9647b..80a05f6fee85bc 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -137,6 +137,14 @@ properties: items: - const: google,damu - const: mediatek,mt8183 + - description: Google Fennel (Lenovo IdeaPad 3 Chromebook) + items: + - enum: + - google,fennel-sku0 + - google,fennel-sku1 + - google,fennel-sku6 + - const: google,fennel + - const: mediatek,mt8183 - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311) items: - enum: From f11f44be2427a601595be1c2f8d6e3a77d3a0f98 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:05:57 +0800 Subject: [PATCH 089/511] arm64: dts: mt8183: Add kukui-jacuzzi-kappa board Kappa is known as HP Chromebook 11a Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210421090601.730744-7-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index a1c50adc98fa71..df70674949ce72 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts new file mode 100644 index 00000000000000..b3f46c16e5d7b6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +/ { + model = "Google kappa board"; + compatible = "google,kappa", "mediatek,mt8183"; +}; + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; From f006bcf1c97200a41c1923ae045fbc153bf49ebe Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:05:58 +0800 Subject: [PATCH 090/511] arm64: dts: mt8183: Add kukui-jacuzzi-willow board Willow is known as Acer Chromebook 311 (C722/C722T) Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210421090601.730744-8-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 2 ++ .../mt8183-kukui-jacuzzi-willow-sku0.dts | 13 ++++++++++ .../mt8183-kukui-jacuzzi-willow-sku1.dts | 12 +++++++++ .../mediatek/mt8183-kukui-jacuzzi-willow.dtsi | 26 +++++++++++++++++++ 4 files changed, 53 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index df70674949ce72..5f43bbc2ea72b1 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -16,6 +16,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts new file mode 100644 index 00000000000000..281265f082dbba --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-willow.dtsi" + +/ { + model = "Google willow board sku0"; + compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts new file mode 100644 index 00000000000000..22e56bdc1ee37f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-willow.dtsi" + +/ { + model = "Google willow board sku1"; + compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi new file mode 100644 index 00000000000000..76d33540166f90 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_JUNIPER"; +}; From dd6e3b06214f39cce1aae7698e69706cc038a0ed Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:05:59 +0800 Subject: [PATCH 091/511] arm64: dts: mt8183: Add kukui-jacuzzi-burnet board Burnet is known as HP Chromebook x360 11MK G3 EE Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210421090601.730744-9-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8183-kukui-jacuzzi-burnet.dts | 30 +++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 5f43bbc2ea72b1..b33d0bc58021bb 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts new file mode 100644 index 00000000000000..a8d6f32ade8d98 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +/ { + model = "Google burnet board"; + compatible = "google,burnet", "mediatek,mt8183"; +}; + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; + +&i2c0 { + touchscreen@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <200>; + hid-descr-addr = <0x0020>; + }; +}; + From 0a9cefe21aec60d58cd1bf68a784c7116d76ef97 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:06:00 +0800 Subject: [PATCH 092/511] arm64: dts: mt8183: Add kukui-jacuzzi-kenzo board Kenzo is known as Acer Chromebook 311. Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210421090601.730744-10-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index b33d0bc58021bb..25770d83059d28 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts new file mode 100644 index 00000000000000..6f1aa692753ad6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-juniper.dtsi" + +/ { + model = "Google kenzo sku17 board"; + compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183"; +}; From 6cd7fdc8c53007b9ccf37c86b031552fff5aaa1d Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 21 Apr 2021 17:06:01 +0800 Subject: [PATCH 093/511] arm64: dts: mt8183: Add kukui-jacuzzi-fennel board Fennel is known as Lenovo IdeaPad Flex 3 Chromebook. Fennel14 is known as Lenovo IdeaPad 3 Chromebook. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210421090601.730744-11-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 3 ++ .../mt8183-kukui-jacuzzi-fennel-sku1.dts | 44 +++++++++++++++++++ .../mt8183-kukui-jacuzzi-fennel-sku6.dts | 32 ++++++++++++++ .../mediatek/mt8183-kukui-jacuzzi-fennel.dtsi | 27 ++++++++++++ .../mt8183-kukui-jacuzzi-fennel14.dts | 16 +++++++ .../dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 8 ++++ 6 files changed, 130 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 25770d83059d28..4f68ebed2e3188 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -15,6 +15,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts new file mode 100644 index 00000000000000..ef6257c9a2d2ff --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" + +/ { + model = "Google fennel sku1 board"; + compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183"; + + pwmleds { + compatible = "pwm-leds"; + keyboard_backlight: keyboard-backlight { + label = "cros_ec::kbd_backlight"; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&cros_ec_pwm { + status = "okay"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts new file mode 100644 index 00000000000000..899c2e42385c27 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" + +/ { + model = "Google fennel sku6 board"; + compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi new file mode 100644 index 00000000000000..bbe6c338f465ee --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts new file mode 100644 index 00000000000000..e8c41f6b4b0d4e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" + +/ { + model = "Google fennel14 sku0 board"; + compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183"; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL14"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 4049dff8464bb5..d8826c82bcda29 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,6 +92,14 @@ }; }; +&cros_ec { + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + status = "disabled"; + }; +}; + &dsi0 { status = "okay"; /delete-node/panel@0; From 14cdc1f243d79e0b46be150502b7dba9c5a6bdfd Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Mon, 12 Apr 2021 08:24:50 +0200 Subject: [PATCH 094/511] ARM: dts: imx6: phyFLEX: Fix UART hardware flow control Serial interface uart3 on phyFLEX board is capable of 5-wire connection including signals RTS and CTS for hardware flow control. Fix signals UART3_CTS_B and UART3_RTS_B padmux assignments and add missing property "uart-has-rtscts" to allow serial interface to be configured and used with the hardware flow control. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 7bd658b7bdda0f..f3236204cb5a9f 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -322,8 +322,8 @@ fsl,pins = < MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 >; }; @@ -410,6 +410,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; status = "disabled"; }; From 340364b8b10a537644d2beb20e79b7fe9cbb1ebf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Tue, 13 Apr 2021 17:01:16 +0200 Subject: [PATCH 095/511] ARM: dts: imx6dl-yapp4: Configure the OLED display segment offset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The imx6dl-yapp4 platform uses a GE-LX012864FWPP3N0000 OLED display. The display consist of a 128x64 OLED panel and a SSD1305 controller. The OLED panel resolution is 128x64 but the built-in controller default resolution is 132x64. To display properly a segment offset needs to be configured. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 7d2c72562c7355..f2c7298aead1f1 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -341,6 +341,7 @@ solomon,height = <64>; solomon,width = <128>; solomon,page-offset = <0>; + solomon,col-offset = <4>; solomon,prechargep2 = <15>; reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; vbat-supply = <&sw2_reg>; From b82f8e2992534aab0fa762a37376be30df263701 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 10 May 2021 23:58:40 +0200 Subject: [PATCH 096/511] arm64: dts: rockchip: fix regulator-gpio states array A test with the command below gives this error: /arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml: sdmmcio-regulator: states:0: [1800000, 1, 3300000, 0] is too long dtbs_check expects regulator-gpio states in a format of 2 per item, so fix them all. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/ regulator/gpio-regulator.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210510215840.16270-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts index 3dddd4742c3a0e..665b2e69455dd1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts @@ -84,8 +84,8 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; + states = <1800000 0x0>, + <3300000 0x1>; vin-supply = <&vcc5v0_sys>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts index 64cf07ee3d10cb..3857d487ab84cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts @@ -77,8 +77,8 @@ regulator-settling-time-us = <5000>; regulator-type = "voltage"; startup-delay-us = <2000>; - states = <1800000 0x1 - 3300000 0x0>; + states = <1800000 0x1>, + <3300000 0x0>; vin-supply = <&vcc_io_33>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index bdf0ca07eae9da..aa22a0c222655f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -50,8 +50,8 @@ vcc_sdio: sdmmcio-regulator { compatible = "regulator-gpio"; gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; + states = <1800000 0x1>, + <3300000 0x0>; regulator-name = "vcc_sdio"; regulator-type = "voltage"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index beee5fbb344377..5d7a9d96d1633f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -245,7 +245,7 @@ pp1800_pcie: &pp1800_s0 { }; &ppvar_sd_card_io { - states = <1800000 0x0 3300000 0x1>; + states = <1800000 0x0>, <3300000 0x1>; regulator-max-microvolt = <3300000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 4002742fed4c13..c1bcc8ca3769d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -252,8 +252,8 @@ enable-active-high; enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3000000 0x0>; + states = <1800000 0x1>, + <3000000 0x0>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; From 271b66414df0b172c936b3cfd1894b7939f84165 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 10 May 2021 11:06:07 +0200 Subject: [PATCH 097/511] arm64: dts: rockchip: Add support for two PWM fans on helios64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the helios64 board the two connectors P6 and P7 are supposed to power two fans. Add the corresponding pwm-fan devices. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20210510090607.970145-1-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-kobol-helios64.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 19485b552bc4b8..9d4a0885fd1218 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -40,6 +40,20 @@ #clock-cells = <0>; }; + fan1 { + /* fan connected to P7 */ + compatible = "pwm-fan"; + pwms = <&pwm0 0 40000 0>; + cooling-levels = <0 80 170 255>; + }; + + fan2 { + /* fan connected to P6 */ + compatible = "pwm-fan"; + pwms = <&pwm1 0 40000 0>; + cooling-levels = <0 80 170 255>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -352,6 +366,16 @@ status = "okay"; }; +&pwm0 { + /* pwm-fan on P7 */ + status = "okay"; +}; + +&pwm1 { + /* pwm-fan on P6 */ + status = "okay"; +}; + &sdhci { bus-width = <8>; mmc-hs200-1_8v; From 5a65adfa2ad1542f856fc7de3999d51f3a35d2e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 10 May 2021 11:09:32 +0200 Subject: [PATCH 098/511] arm64: dts: rockchip: Add support for PCIe on helios64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is enough to make the SATA controller visible: # lspci 00:00.0 PCI bridge: Fuzhou Rockchip Electronics Co., Ltd RK3399 PCI Express Root Port 01:00.0 SATA controller: JMicron Technology Corp. JMB58x AHCI SATA controller Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20210510090932.970447-1-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-kobol-helios64.dts | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 9d4a0885fd1218..037dc5cdc3f358 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -23,6 +23,16 @@ mmc1 = &sdhci; }; + avdd_0v9_s0: avdd-0v9-s0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_0v9_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc1v8_sys_s3>; + }; + avdd_1v8_s0: avdd-1v8-s0 { compatible = "regulator-fixed"; regulator-name = "avdd_1v8_s0"; @@ -72,6 +82,18 @@ }; }; + pcie_power: pcie-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie_pwr>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-name = "pcie_power"; + startup-delay-us = <10000>; + vin-supply = <&vcc5v0_perdev>; + }; + vcc1v8_sys_s0: vcc1v8-sys-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_sys_s0"; @@ -109,6 +131,16 @@ }; }; + vcc5v0_perdev: vcc5v0-perdev { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_perdev"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin_bkup>; + }; + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -331,6 +363,20 @@ status = "okay"; }; +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + num-lanes = <2>; + status = "okay"; + + vpcie12v-supply = <&vcc12v_dcin>; + vpcie3v3-supply = <&pcie_power>; + vpcie1v8-supply = <&avdd_1v8_s0>; + vpcie0v9-supply = <&avdd_0v9_s0>; +}; + &pinctrl { gmac { gphy_reset: gphy-reset { @@ -348,6 +394,13 @@ }; }; + pcie { + pcie_pwr: pcie-pwr { + rockchip,pins = + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; From dc71c5ca34f408030b979d894c0459ef059445a1 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 10 May 2021 19:29:11 +0200 Subject: [PATCH 099/511] ARM: dts: rockchip: Remove more clock-names from PWM nodes A test with the command below gives this error: /arch/arm/boot/dts/rk3228-evb.dt.yaml: pwm@110b0020: clock-names: ['pwm'] is too short Devices with only one PWM clock use it to both to derive the functional clock for the device and as the bus clock. The driver does not need "clock-names" to get a handle, so remove them all. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210510172911.6763-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 25f83f2f5618e0..5774bc309eb747 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -379,7 +379,6 @@ reg = <0x110b0000 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; status = "disabled"; @@ -390,7 +389,6 @@ reg = <0x110b0010 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; status = "disabled"; @@ -401,7 +399,6 @@ reg = <0x110b0020 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; status = "disabled"; @@ -412,7 +409,6 @@ reg = <0x110b0030 0x10>; #pwm-cells = <2>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; status = "disabled"; From 87cf20ccecb3e3c00605980ef0dba61398499bf6 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 10 May 2021 21:20:54 +0200 Subject: [PATCH 100/511] ARM: dts: rockchip: rename vcc_stdby node name for rk3066a-rayeager.dts A test with the command below gives this error: /arch/arm/boot/dts/rk3066a-rayeager.dt.yaml: /: '5v-stdby-regulator' does not match any of the regexes: '.*-names$', '.*-supply$', '^#.*-cells$', '^#[a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}$', '^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+(,[0-9a-fA-F]+)*$', '^__.*__$', 'pinctrl-[0-9]+' A node name shouldn't start with a number, so change it to 'stdby-regulator'. make ARCH=arm dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema /schemas/dt-core.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210510192054.8876-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-rayeager.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 309518403d86ab..a73e8900c92410 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -58,7 +58,7 @@ }; /* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */ - vcc_stdby: 5v-stdby-regulator { + vcc_stdby: stdby-regulator { compatible = "regulator-fixed"; regulator-name = "5v_stdby"; regulator-min-microvolt = <5000000>; From 19486fe587b8ed17daf87a6419b51e3a65ce565c Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 12 May 2021 14:23:46 +0200 Subject: [PATCH 101/511] arm64: dts: rename grf-gpio nodename in rk3328.dtsi A test with the command below gives this error: /arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml: syscon@ff100000: grf-gpio: {'compatible': ['rockchip,rk3328-grf-gpio'], 'gpio-controller': True, '#gpio-cells': [[2]], 'phandle': [[68]]} is not of type 'array' Due to the regex "(? Link: https://lore.kernel.org/r/20210512122346.9463-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 4b37071a584ce8..bc0bdc3d86ff8f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -288,7 +288,7 @@ status = "disabled"; }; - grf_gpio: grf-gpio { + grf_gpio: gpio { compatible = "rockchip,rk3328-grf-gpio"; gpio-controller; #gpio-cells = <2>; From 2b3aa53ebf46031944d0edeab878ab9ba6c415d2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 12 May 2021 00:53:29 +0200 Subject: [PATCH 102/511] ARM: dts: ixp4xx: Add beeper to the NSLU2 This adds the beeper GPIO to the NSLU2 completing the board support. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts index 46dda0a895e747..5b8dcc19deeef6 100644 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts @@ -90,6 +90,11 @@ timeout-ms = <5000>; }; + gpio-beeper { + compatible = "gpio-beeper"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + }; + soc { bus@50000000 { /* The first 16MB region at CS0 on the expansion bus */ From 6e4e4e2a255849758b8d3240671060d355d71edf Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Wed, 12 May 2021 14:23:45 +0200 Subject: [PATCH 103/511] ARM: dts: rockchip: move and restyle grf nodes rk3066/rk3188 With grf.txt converted to YAML a lot of compatibles did not have 'simple-mfd' added in the old binding. That implies that if you have child nodes they need to be documented. Make the new layout fit for rk3066/rk3188, move and restyle the grf nodes. Remove rockchip,grf from usbphy node. Add "#phy-cells", because it is a required property by phy-provider.yaml With the conversion of syscon.yaml minItems for compatibles was set to 2. Current Rockchip rk3xxx.dtsi file only uses "syscon" for the grf registers. Add "syscon", "simple-mfd" compatible for rk3066/rk3188 to reduce notifications produced with: make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml Changed compatibles: "rockchip,rk3066-grf", "syscon", "simple-mfd" "rockchip,rk3188-grf", "syscon", "simple-mfd" Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210512122346.9463-4-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 53 +++++++++++++++++++--------------- arch/arm/boot/dts/rk3188.dtsi | 53 +++++++++++++++++++--------------- arch/arm/boot/dts/rk3xxx.dtsi | 2 +- 3 files changed, 59 insertions(+), 49 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 8e087c34b881b8..30dcf557ec33fd 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -266,30 +266,6 @@ status = "disabled"; }; - usbphy: phy { - compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@17c { - #phy-cells = <0>; - reg = <0x17c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@188 { - #phy-cells = <0>; - reg = <0x188>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; @@ -702,6 +678,35 @@ power-domains = <&power RK3066_PD_GPU>; }; +&grf { + compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3066a-usb-phy", + "rockchip,rk3288-usb-phy"; + #phy-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@17c { + reg = <0x17c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@188 { + reg = <0x188>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index f1632b820717c8..3a0c50026b074a 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -214,30 +214,6 @@ }; }; - usbphy: phy { - compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - #phy-cells = <0>; - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@11c { - #phy-cells = <0>; - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; @@ -662,6 +638,35 @@ power-domains = <&power RK3188_PD_GPU>; }; +&grf{ + compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3188-usb-phy", + "rockchip,rk3288-usb-phy"; + #phy-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@10c { + reg = <0x10c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@11c { + reg = <0x11c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; +}; + &i2c0 { compatible = "rockchip,rk3188-i2c"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 755c946f11de63..d473552e854747 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -256,7 +256,7 @@ }; grf: grf@20008000 { - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x20008000 0x200>; }; From e4ff0112a03c2e353c8457cd33c88feb89dfec41 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Apr 2021 01:03:16 +0200 Subject: [PATCH 104/511] ARM: dts: ux500: Fix interrupt cells Fix interrupt cells in DT AB8500/AB8505 source files. The compiled DTB files will stay the same. Signed-off-by: Sebastian Reichel Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ab8500.dtsi | 26 +++++++++++++------------- arch/arm/boot/dts/ste-ab8505.dtsi | 22 +++++++++++----------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index a16a00fb5fa5d8..f78b410024903a 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -42,15 +42,15 @@ ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; gpadc: ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, + <39 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "HW_CONV_END", "SW_CONV_END"; vddadc-supply = <&ab8500_ldo_tvout_reg>; #address-cells = <1>; @@ -219,13 +219,13 @@ ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -242,8 +242,8 @@ ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi index cc045b2fc217df..3380afa74c146a 100644 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-ab8505.dtsi @@ -39,8 +39,8 @@ ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; @@ -182,13 +182,13 @@ ab8500_usb: ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -205,8 +205,8 @@ ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; From 4917b702818872fdf2a9973705af3aa7d3d1f19e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 13 Apr 2021 01:03:17 +0200 Subject: [PATCH 105/511] ARM: dts: ux500: Rename gpio-controller node Rename the AB8500 gpio controller node from ab8500-gpio to ab8500-gpiocontroller, since -gpio is a common suffix for gpio consumers. Signed-off-by: Sebastian Reichel Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ab8500.dtsi | 2 +- arch/arm/boot/dts/ste-ab8505.dtsi | 2 +- arch/arm/boot/dts/ste-href-ab8500.dtsi | 2 +- arch/arm/boot/dts/ste-href.dtsi | 2 +- arch/arm/boot/dts/ste-snowball.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index f78b410024903a..d0fe3f9aa183a8 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -34,7 +34,7 @@ #clock-cells = <1>; }; - ab8500_gpio: ab8500-gpio { + ab8500_gpio: ab8500-gpiocontroller { compatible = "stericsson,ab8500-gpio"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi index 3380afa74c146a..0defc15b9bbc6c 100644 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-ab8505.dtsi @@ -31,7 +31,7 @@ #clock-cells = <1>; }; - ab8505_gpio: ab8505-gpio { + ab8505_gpio: ab8505-gpiocontroller { compatible = "stericsson,ab8505-gpio"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index 4946743de7b9b8..3ccb7b5c71625c 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -9,7 +9,7 @@ soc { prcmu@80157000 { ab8500 { - ab8500-gpio { + ab8500-gpiocontroller { /* Hog a few default settings */ pinctrl-names = "default"; pinctrl-0 = <&gpio2_default_mode>, diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 83b179692dff7b..7566b4963ef688 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -202,7 +202,7 @@ prcmu@80157000 { ab8500 { - ab8500-gpio { + ab8500-gpiocontroller { }; ab8500_usb { diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index b344b3748143a8..40f1d7c9c1d4cd 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -376,7 +376,7 @@ prcmu@80157000 { ab8500 { - ab8500-gpio { + ab8500-gpiocontroller { /* * AB8500 GPIOs are numbered starting from 1, so the first * index 0 is what in the datasheet is called "GPIO1", and From 4beba4011995a2c44ee27e1d358dc32e6b9211b3 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 15 May 2021 02:02:34 +0200 Subject: [PATCH 106/511] ARM: dts: ux500: Fix orientation of accelerometer This adds a mounting matrix to the accelerometer on the TVK1281618 R3. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi index 70f058352efcae..511e097cc33e04 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi @@ -89,6 +89,9 @@ <19 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&accel_tvk_mode>; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; }; magnetometer@1e { compatible = "st,lsm303dlm-magn"; From 7153218aef73928dae49c55831cb8b1c12b08ca7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 12 Apr 2021 14:25:34 +0200 Subject: [PATCH 107/511] ARM: dts: ux500: Drop drdy pin assignment from magnetometer This magnetometer can not select which line provided the outgoing IRQ so drop it, the DT bindings will complain too. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi index 511e097cc33e04..00ce9d79f5404c 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi @@ -95,7 +95,6 @@ }; magnetometer@1e { compatible = "st,lsm303dlm-magn"; - st,drdy-int-pin = <1>; reg = <0x1e>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; From 59ba546d1662c4beb738725965041f350afe24b4 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 18 Mar 2021 09:27:58 +0100 Subject: [PATCH 108/511] ARM: dts: ux500: Fix some compatible strings The Golden and Skomer phones have BCM4334 WLAN+BT chips, so make the compatible strings reflect the new available bindings for these. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 3 ++- arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 4 ++-- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 3 ++- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 0d43ee6583cf89..40df7c61bf69e6 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -121,7 +121,7 @@ #size-cells = <0>; wifi@1 { - compatible = "brcm,bcm4329-fmac"; + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; reg = <1>; /* GPIO216 (WLAN_HOST_WAKE) */ @@ -162,6 +162,7 @@ pinctrl-1 = <&u0_a_1_sleep>; bluetooth { + /* BCM4334B0 actually */ compatible = "brcm,bcm4330-bt"; /* GPIO222 (BT_VREG_ON) */ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index f24369873ce2ce..eaf8039d10ad63 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -401,8 +401,7 @@ status = "okay"; wifi@1 { - /* Actually BRCM4330 */ - compatible = "brcm,bcm4329-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; /* GPIO216 WL_HOST_WAKE */ interrupt-parent = <&gpio6>; @@ -436,6 +435,7 @@ status = "okay"; bluetooth { + /* BCM4330B1 actually */ compatible = "brcm,bcm4330-bt"; /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index d28a00757d0b9e..94afd7a0fe1f00 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -211,7 +211,7 @@ #size-cells = <0>; wifi@1 { - compatible = "brcm,bcm4329-fmac"; + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; reg = <1>; /* GPIO216 WL_HOST_WAKE */ interrupt-parent = <&gpio6>; @@ -247,6 +247,7 @@ /* FIXME: not quite working yet, probably needs regulators */ bluetooth { + /* BCM4334B0 actually */ compatible = "brcm,bcm4330-bt"; shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; From 4b6847e507c719a5ee89918b23be7ecd702df1d5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 18 May 2021 16:16:57 +0200 Subject: [PATCH 109/511] ARM: dts: href: Mount matrices for TVK R2 This adds the proper mounting matrices for the TVK R2 board. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi index 8d59202cebd6fa..37e59403c01ffd 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi @@ -104,6 +104,9 @@ * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; */ + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; }; magnetometer@1e { /* Magnetometer */ @@ -136,6 +139,9 @@ /* INT2 would need to be open drain */ interrupts = <18 IRQ_TYPE_EDGE_RISING>, <19 IRQ_TYPE_EDGE_RISING>; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; }; magnetometer@f { /* Magnetometer */ From 92ed3675574723a963152abbbe527b47f659340f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 17 May 2021 00:35:23 +0800 Subject: [PATCH 110/511] dt-bindings: arm: Add NanoPi R1S H5 Add the bindings for NanoPi R1S H5 board. Signed-off-by: Chukun Pan Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210516163523.9484-3-amadeus@jmu.edu.cn --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ec8108483b49a7..889128acf49a60 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -275,6 +275,11 @@ properties: - const: friendlyarm,nanopi-r1 - const: allwinner,sun8i-h3 + - description: FriendlyARM NanoPi R1S H5 + items: + - const: friendlyarm,nanopi-r1s-h5 + - const: allwinner,sun50i-h5 + - description: FriendlyARM ZeroPi items: - const: friendlyarm,zeropi From 9962cb9be2db877c232aaf00db40125c0d7bf4bc Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 17 May 2021 00:35:22 +0800 Subject: [PATCH 111/511] arm64: dts: allwinner: h5: Add NanoPi R1S H5 support The NanoPi R1S H5 is a open source board made by FriendlyElec. It has the following features: - Allwinner H5, Quad-core Cortex-A53 - 512MB DDR3 RAM - 10/100/1000M Ethernet x 2 - RTL8189ETV WiFi 802.11b/g/n - USB 2.0 host port (A) - MicroSD Slot - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Chukun Pan Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210516163523.9484-2-amadeus@jmu.edu.cn --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 195 ++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 41ce680e5f8d1c..a96d9d2d8dd873 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts new file mode 100644 index 00000000000000..55bcdf8d1a0718 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Chukun Pan + * + * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: + * Copyright (C) 2017 Antony Antony + * Copyright (C) 2016 ARM Ltd. + */ + +/dts-v1/; +#include "sun50i-h5.dtsi" +#include "sun50i-h5-cpu-opp.dtsi" + +#include +#include +#include + +/ { + model = "FriendlyARM NanoPi R1S H5"; + compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; + + aliases { + ethernet0 = &emac; + ethernet1 = &rtl8189etv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; + }; + }; + + r-gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; + }; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <1100000 0x0>, <1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + post-power-on-delay-ms = <200>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpux>; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "microchip,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8189etv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; From cd8d60399ac5634513199b76c7dbd43092e29b1b Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Thu, 13 May 2021 22:35:26 +0200 Subject: [PATCH 112/511] dt-bindings: pwm: allwinner: add v3s pwm compatible The Allwinner V3s pwm peripheral is compatible with the pwm peripheral inside the Allwinner A20. This patch adds a compatible string for it. Signed-off-by: Tobias Schramm Reviewed-by: Andre Przywara Acked-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210513203527.2072090-2-t.schramm@manjaro.org --- .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 7dcab2bf812806..04ff708fdc8686 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -24,6 +24,9 @@ properties: - items: - const: allwinner,sun8i-a83t-pwm - const: allwinner,sun8i-h3-pwm + - items: + - const: allwinner,sun8i-v3s-pwm + - const: allwinner,sun7i-a20-pwm - items: - const: allwinner,sun50i-a64-pwm - const: allwinner,sun5i-a13-pwm From 1d34350cdb6ba23b9b627aec09a14dfc6db046ee Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Thu, 13 May 2021 22:35:27 +0200 Subject: [PATCH 113/511] ARM: dts: sun8i: v3s: add pwm controller to v3s dts The Allwinner V3s and V3 SoCs feature a pwm controller identical to the one used in the Allwinner A20. This commit adds it to the V3s dtsi. Signed-off-by: Tobias Schramm Reviewed-by: Andre Przywara Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210513203527.2072090-3-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index eb4cb63fef13c5..456dee9de87fc5 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -422,6 +422,15 @@ clocks = <&osc24M>; }; + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-v3s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21400 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x400>; From 49b9e240b84d90511f581c3384582c615b1fd586 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:43:59 +0200 Subject: [PATCH 114/511] ARM: dts: sun8i: v3s: add DMA controller to v3s dts The Allwinner V3s and V3 feature a DMA controller. This commit adds it to the V3s dtsi. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-2-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 456dee9de87fc5..1ba078cc70ac95 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Icenowy Zheng + * Copyright (C) 2021 Tobias Schramm * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -172,6 +173,15 @@ interrupts = ; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-v3s-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-v3s-tcon"; reg = <0x01c0c000 0x1000>; From 93bc32b0397ee94ae0a5db92b6d9dd3ff6f9d4fe Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:00 +0200 Subject: [PATCH 115/511] ARM: dts: sun8i: v3s: add DMA properties to peripherals supporting DMA This commit adds DMA properties to all peripherals supporting DMA on the Allwinner V3s, enabling accelerated data transfer to them. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-3-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 1ba078cc70ac95..d027f34e68ebe0 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -285,6 +285,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; clock-names = "ahb", "mod"; + dmas = <&dma 16>, <&dma 16>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_CE>; reset-names = "ahb"; }; @@ -455,6 +457,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -466,6 +470,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -477,6 +483,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART2>; pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; @@ -556,6 +564,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; resets = <&ccu RST_BUS_SPI0>; From 5348915db9b878084ae67f159063550fe0500847 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:01 +0200 Subject: [PATCH 116/511] ARM: dts: sun8i: v3s: add analog codec and frontend to v3s dts The Allwinner V3s and V3 SoCs feature an integrated analog audio codec. Additionally both have an analog frontend with mixers and amplifiers for the codec. This commit adds both, the analog codec and its frontend to the V3s dtsi. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-4-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index d027f34e68ebe0..b30bc1a25ebb93 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -450,6 +450,25 @@ status = "disabled"; }; + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-v3s-codec"; + reg = <0x01c22c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "codec"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,codec-analog-controls = <&codec_analog>; + status = "disabled"; + }; + + codec_analog: codec-analog@1c23000 { + compatible = "allwinner,sun8i-v3s-codec-analog"; + reg = <0x01c23000 0x4>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; From 78e8db071b684f4b3975653fd31ffabc8c204501 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:02 +0200 Subject: [PATCH 117/511] ASoC: dt-bindings: sun8i-a23-codec-analog: add compatible for Allwinner V3 The analog codec frontend of the Allwinner V3 is compatible with the analog codec frontend used on the Allwinner H3. This patch adds a compatible string for the analog codec frontend on the Allwinner V3 SoC. Signed-off-by: Tobias Schramm Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-5-t.schramm@manjaro.org --- .../bindings/sound/allwinner,sun8i-a23-codec-analog.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml index 9718358826abda..26eca21e1f0f5d 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml @@ -12,12 +12,15 @@ maintainers: properties: compatible: - enum: + oneOf: # FIXME: This is documented in the PRCM binding, but needs to be # migrated here at some point # - allwinner,sun8i-a23-codec-analog - - allwinner,sun8i-h3-codec-analog - - allwinner,sun8i-v3s-codec-analog + - const: allwinner,sun8i-h3-codec-analog + - items: + - const: allwinner,sun8i-v3-codec-analog + - const: allwinner,sun8i-h3-codec-analog + - const: allwinner,sun8i-v3s-codec-analog reg: maxItems: 1 From 8575276c1fe3c003c4a31b1c4ec6d47ea50843d0 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:03 +0200 Subject: [PATCH 118/511] ARM: dts: sun8i: V3: add codec analog frontend to V3 dts The Allwinner V3 SoC has a different analog codec frontend than the V3s SoC. The frontend used on the V3 SoC is compatible with the on used in the Allwinner H3 SoC. This patch adds the corresponding node to the Allwinner V3 dtsi. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-6-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index c279e13583ba4d..8af790d286b9c2 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -9,6 +9,11 @@ compatible = "allwinner,sun8i-v3-ccu"; }; +&codec_analog { + compatible = "allwinner,sun8i-v3-codec-analog", + "allwinner,sun8i-h3-codec-analog"; +}; + &emac { /delete-property/ phy-handle; /delete-property/ phy-mode; From ce09d1a6800df7ce0f73ae4d4b3ad4975cb31498 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:04 +0200 Subject: [PATCH 119/511] dt-bindings: sound: sun4i-i2s: add Allwinner V3 I2S compatible The I2S peripheral of the Allwinner V3 SoC is compatible with the one found in the Allwinner H3 SoC. This patch adds a compatible string for it. Signed-off-by: Tobias Schramm Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-7-t.schramm@manjaro.org --- .../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml index a16e37b01e1d78..39b66e9ce3e3a2 100644 --- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -20,6 +20,9 @@ properties: - const: allwinner,sun6i-a31-i2s - const: allwinner,sun8i-a83t-i2s - const: allwinner,sun8i-h3-i2s + - items: + - const: allwinner,sun8i-v3-i2s + - const: allwinner,sun8i-h3-i2s - const: allwinner,sun50i-a64-codec-i2s - items: - const: allwinner,sun50i-a64-i2s From 65a50bca77177210c2333789ee7cf7191d3b99ae Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 May 2021 15:44:05 +0200 Subject: [PATCH 120/511] ARM: dts: sun8i: V3: add I2S interface to V3 dts The Allwinner V3 SoC features an I2S interface. The I2S peripheral is identical to that in the Allwinner H3 SoC. This commit adds it to the Allwinner V3 dts. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210514134405.2097464-8-t.schramm@manjaro.org --- arch/arm/boot/dts/sun8i-v3.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index 8af790d286b9c2..186c30cbe6ee8b 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -1,10 +1,31 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2019 Icenowy Zheng + * Copyright (C) 2021 Tobias Schramm */ #include "sun8i-v3s.dtsi" +/ { + soc { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-v3-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_pins>; + resets = <&ccu RST_BUS_I2S0>; + status = "disabled"; + }; + }; +}; + &ccu { compatible = "allwinner,sun8i-v3-ccu"; }; @@ -30,6 +51,11 @@ &pio { compatible = "allwinner,sun8i-v3-pinctrl"; + i2s0_pins: i2s0-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "i2s"; + }; + uart1_pg_pins: uart1-pg-pins { pins = "PG6", "PG7"; function = "uart1"; From 086a4302380931ca627b51b4ef5ba3bfeca21276 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 10 May 2021 18:36:47 +0200 Subject: [PATCH 121/511] ARM: dts: sun8i: r40: Add timer node Allwinner R40 has a timer. Add a node for it. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210510163647.2731675-1-jernej.skrabec@gmail.com --- arch/arm/boot/dts/sun8i-r40.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 03e054c0bac40c..291f4784e86c2e 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -691,6 +691,18 @@ }; }; + timer@1c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = , + , + , + , + , + ; + clocks = <&osc24M>; + }; + wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; From 7d6c9ee5e0eff464771678b32867d5244b84920a Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 18 May 2021 18:53:53 +0000 Subject: [PATCH 122/511] ARM: dts: gemini: convert obsolete SPI properties gpio-xxx are obsoletes properties, convert them to xxx-gpios. Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 6 +++--- arch/arm/boot/dts/gemini-sl93512r.dts | 6 +++--- arch/arm/boot/dts/gemini-sq201.dts | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index cc39289e99dd13..b2a0f3b1441e3c 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -61,9 +61,9 @@ #size-cells = <0>; /* Collides with IDE pins, that's cool (we do not use them) */ - gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; num-chipselects = <1>; diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts index a0916d3c105965..c78e55fd256295 100644 --- a/arch/arm/boot/dts/gemini-sl93512r.dts +++ b/arch/arm/boot/dts/gemini-sl93512r.dts @@ -87,9 +87,9 @@ #address-cells = <1>; #size-cells = <0>; /* Check pin collisions */ - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index 0c6e6d35bfaa46..1b64cc80b55a9e 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -72,9 +72,9 @@ #address-cells = <1>; #size-cells = <0>; /* Check pin collisions */ - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; From cd49f71cff8de325c7602bb2d072bc6d2807387f Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Wed, 19 May 2021 22:19:12 +0800 Subject: [PATCH 123/511] arm64: dts: broadcom: normalize the node name of the UART devices Change the node name of the UART devices to match "^serial(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 2ffb2c92182abe..7b04dfe67bef63 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -470,7 +470,7 @@ status = "disabled"; }; - uart0: uart@100000 { + uart0: serial@100000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00100000 0x1000>; @@ -481,7 +481,7 @@ status = "disabled"; }; - uart1: uart@110000 { + uart1: serial@110000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00110000 0x1000>; @@ -492,7 +492,7 @@ status = "disabled"; }; - uart2: uart@120000 { + uart2: serial@120000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00120000 0x1000>; @@ -503,7 +503,7 @@ status = "disabled"; }; - uart3: uart@130000 { + uart3: serial@130000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00130000 0x1000>; From 6bb0ad80c52ddf57c54a478cecf94c27c328ca46 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 23 Apr 2021 11:37:12 +0300 Subject: [PATCH 124/511] ARM: dts: dra76-evm: remove ov5640 DRA76 EVM boards are not shipped with OV5640 sensor module, it is a separate purchase. OV5640 module is also just one of the possible sensors or capture boards you can connect. However, for some reason, OV5640 has been added to the board dts file, making it cumbersome to use other sensors. Remove the OV5640 from the dts file so that it is easy to use other sensors via DT overlays. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra76-evm.dts | 35 --------------------------------- 1 file changed, 35 deletions(-) diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 9bd01ae40b1d1f..4508f7ffde0dc6 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -158,12 +158,6 @@ regulator-max-microvolt = <1800000>; }; - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; @@ -406,27 +400,6 @@ }; }; -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - &cpu0 { vdd-supply = <&buck10_reg>; }; @@ -573,14 +546,6 @@ }; }; -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; - &ipu2 { status = "okay"; memory-region = <&ipu2_cma_pool>; From 3d7bf58546ba858ea0a15eb10195a397b9704b51 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 28 Apr 2021 18:40:25 +0200 Subject: [PATCH 125/511] ARM: dts: osd3358-sm-red: group in the same phandle all its properties Having a single phandle reference for rtc0, mmc0 and am335x_pinmux makes the DTS well-ordered and therefore more readable. Signed-off-by: Dario Binacchi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 132 +++++++++----------- 1 file changed, 62 insertions(+), 70 deletions(-) diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index f841afb27844c8..5403e47c07e260 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -25,10 +25,6 @@ regulator-always-on; }; -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - &mmc2 { vmmc-supply = <&vmmcsd_fixed>; pinctrl-names = "default"; @@ -37,68 +33,6 @@ status = "okay"; }; -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; - - flash_enable: flash-enable { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ - >; - }; - - imu_interrupt: imu-interrupt { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ - >; - }; - - ethernet_interrupt: ethernet-interrupt{ - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ - >; - }; -}; - &lcdc { status = "okay"; @@ -167,10 +101,6 @@ }; }; -&rtc { - system-power-controller; -}; - &mcasp0 { #sound-dai-cells = <0>; pinctrl-names = "default"; @@ -267,6 +197,66 @@ pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; + + flash_enable: flash-enable { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ + >; + }; + + imu_interrupt: imu-interrupt { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ + >; + }; + + ethernet_interrupt: ethernet-interrupt{ + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; + user_leds_s0: user-leds-s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ @@ -427,6 +417,7 @@ &mmc1 { status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; @@ -434,6 +425,7 @@ }; &rtc { + system-power-controller; clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; From e33f8fd9fda9730f5a0f27d1a56c69e1228ed907 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 21 May 2021 11:48:16 +0200 Subject: [PATCH 126/511] ARM: dts: Fix up the IXP4xx ethernet nodes All of IXP4xx SoCs has an EthA at 0xc800c000 so move this from the IXP[56]x to the IXP4xx DTSI. Then add the second ethernet port on the Cambria GW2358-4 on EthA. Reported-by: Zoltan HERPAI Signed-off-by: Linus Walleij --- arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts | 13 +++++++++++++ arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi | 11 ----------- arch/arm/boot/dts/intel-ixp4xx.dtsi | 11 +++++++++++ 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts index 581ff18a2310be..60a1228a970fc9 100644 --- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts @@ -153,7 +153,20 @@ phy1: ethernet-phy@1 { reg = <1>; }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; }; }; + + ethernet@c800c000 { + status = "ok"; + queue-rx = <&qmgr 2>; + queue-txready = <&qmgr 19>; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + intel,npe-handle = <&npe 0>; + }; }; }; diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi index ef3696e369b8c2..cce49e80904359 100644 --- a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi +++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi @@ -31,17 +31,6 @@ status = "disabled"; }; - /* This is known as EthA */ - ethernet@c800c000 { - compatible = "intel,ixp4xx-ethernet"; - reg = <0xc800c000 0x1000>; - status = "disabled"; - intel,npe = <0>; - /* Dummy values that depend on firmware */ - queue-rx = <&qmgr 0>; - queue-txready = <&qmgr 0>; - }; - /* This is known as EthB1 */ ethernet@c800d000 { compatible = "intel,ixp4xx-ethernet"; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index 31371c65ad6d8b..528d5dc09cfca3 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -136,5 +136,16 @@ queue-txready = <&qmgr 0>; intel,npe-handle = <&npe 2>; }; + + /* This is known as EthA */ + ethernet@c800c000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800c000 0x1000>; + status = "disabled"; + intel,npe = <0>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; }; }; From 3b976b541823b4754ccf9ceede2d24efd79ef74b Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Fri, 21 May 2021 19:35:39 +0000 Subject: [PATCH 127/511] ARM: dts: gemini-dlink-dns-313: rename gpio-i2c to i2c This fixes dtcheck warning: arch/arm/boot/dts/gemini-dlink-dns-313.dt.yaml: gpio-i2c: $nodename:0: 'gpio-i2c' does not match '^i2c(@.*)?' Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dns-313.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts index b8acc6eaaa6d72..eba1c94ed7f774 100644 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -82,7 +82,7 @@ /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ - gpio-i2c { + i2c { compatible = "i2c-gpio"; sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; From 30639b8ed6c8e7bcbeb92c4261819bed68463215 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Fri, 21 May 2021 19:35:40 +0000 Subject: [PATCH 128/511] ARM: dts: gemini-dlink-dir-685: rename gpio-i2c to i2c gemini-dlink-dir-685.dt.yaml: gpio-i2c: $nodename:0: 'gpio-i2c' does not match '^i2c(@.*)?' >From schema: /usr/src/linux-next/Documentation/devicetree/bindings/i2c/i2c-gpio.yaml Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index b2a0f3b1441e3c..06216c662d2cee 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -169,7 +169,7 @@ * The touchpad input is connected to a GPIO bit-banged * I2C bus. */ - gpio-i2c { + i2c { compatible = "i2c-gpio"; /* Collides with ICE */ sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; From 4bad54aeb6d684fa40403f7d2d782205b785c731 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 19 May 2021 20:35:46 +0000 Subject: [PATCH 129/511] ARM: dts: gemini-dlink-dir-685: Remove address from display port The address and reg adds no value to the port node, remove them. Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index 06216c662d2cee..c79a2a02dd6bf6 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -492,8 +492,7 @@ display-controller@6a000000 { status = "okay"; - port@0 { - reg = <0>; + port { display_out: endpoint { remote-endpoint = <&panel_in>; }; From 78924664af92fabc203a946eac09c69592fa12c4 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Wed, 19 May 2021 20:35:47 +0000 Subject: [PATCH 130/511] ARM: dts: gemini: remove xxx-cells from display dtb_check complains about #address-cells and #size-cells, so lets remove them. Signed-off-by: Corentin Labbe Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 23271d537ae5b6..e5c15fe71a3560 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -410,8 +410,6 @@ clock-names = "PCLK", "TVE"; pinctrl-names = "default"; pinctrl-0 = <&tvc_default_pins>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; From 547be9a05dc825fbbaeb970ec9e2313a49bf586f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 14 May 2021 16:20:16 -0500 Subject: [PATCH 131/511] arm64: dts: ti: k3-am65-iot2050-common: Disable mailbox nodes There are no sub-mailbox devices defined currently for both the IOT2050 boards. These are usually dictated by the firmwares running on the R5F remote processors and the applications they provide. Defining the actual sub-mailboxes will also dictate the interrupts the clusters will use for interrupts on the Cortex-A53 cores. Disable all of the Mailbox clusters until the sub-mailboxes are defined and used. This fixes the warnings around the missing interrupts with the upcoming conversion of the OMAP Mailbox binding to YAML format. Signed-off-by: Suman Anna Acked-by: Jan Kiszka Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210514212016.3153-1-s-anna@ti.com --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index de763ca9251c71..f4ec9ed5293954 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -653,3 +653,51 @@ &pcie1_ep { status = "disabled"; }; + +&mailbox0_cluster0 { + status = "disabled"; +}; + +&mailbox0_cluster1 { + status = "disabled"; +}; + +&mailbox0_cluster2 { + status = "disabled"; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + status = "disabled"; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; From 445ae16ac1c580a388d0249cac715e83b7c1d5cb Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 18 May 2021 16:28:57 +0200 Subject: [PATCH 132/511] ARM: dts: imx28: Add DTS description of imx28 based XEA board This patch adds DTS definition of the imx278 based XEA board. Signed-off-by: Lukasz Majewski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx28-lwe.dtsi | 170 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx28-xea.dts | 99 ++++++++++++++++++ 3 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx28-lwe.dtsi create mode 100644 arch/arm/boot/dts/imx28-xea.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e750..4d05ad1bf5609c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -725,7 +725,8 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-ts4600.dtb \ - imx28-tx28.dtb + imx28-tx28.dtb \ + imx28-xea.dtb dtb-$(CONFIG_ARCH_NOMADIK) += \ ste-nomadik-s8815.dtb \ ste-nomadik-nhk15.dtb diff --git a/arch/arm/boot/dts/imx28-lwe.dtsi b/arch/arm/boot/dts/imx28-lwe.dtsi new file mode 100644 index 00000000000000..bb971e660db8e3 --- /dev/null +++ b/arch/arm/boot/dts/imx28-lwe.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + aliases { + spi2 = &ssp3; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1"; + }; + + memory@40000000 { + reg = <0x40000000 0x08000000>; + }; + + reg_3v3: regulator-reg-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_5v: regulator-reg-usb-5v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_fec_3v3: regulator-reg-fec-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + #sound-dai-cells = <0>; + assigned-clocks = <&clks 53>; + assigned-clock-rates = <12000000>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&spi3_pins_a { + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__SSP3_D4 + MX28_PAD_AUART2_TX__SSP3_D5 + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + MX28_PAD_AUART2_TX__GPIO_3_9 + >; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a>; + bus-width = <8>; + vmmc-supply = <®_3v3>; + non-removable; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&ssp3 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_a>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x80000>; + read-only; + }; + + partition@80000 { + label = "env0"; + reg = <0x80000 0x10000>; + }; + + partition@90000 { + label = "env1"; + reg = <0x90000 0x10000>; + }; + + partition@100000 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "swupdate"; + reg = <0x500000 0x800000>; + }; + }; + }; +}; + +&usb0 { + vbus-supply = <®_usb_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_b>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-xea.dts b/arch/arm/boot/dts/imx28-xea.dts new file mode 100644 index 00000000000000..a400c108f66a2d --- /dev/null +++ b/arch/arm/boot/dts/imx28-xea.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-lwe.dtsi" + +/ { + compatible = "lwn,imx28-xea", "fsl,imx28"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a &hog_pins_tiva>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_GPMI_D02__GPIO_0_2 + MX28_PAD_GPMI_D05__GPIO_0_5 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_RDY0__GPIO_0_20 + MX28_PAD_GPMI_RDY1__GPIO_0_21 + MX28_PAD_GPMI_RDY2__GPIO_0_22 + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_GPMI_CLE__GPIO_0_27 + MX28_PAD_LCD_VSYNC__GPIO_1_28 + MX28_PAD_SSP1_SCK__GPIO_2_12 + MX28_PAD_SSP1_CMD__GPIO_2_13 + MX28_PAD_SSP2_SS1__GPIO_2_20 + MX28_PAD_SSP2_SS2__GPIO_2_21 + MX28_PAD_LCD_D00__GPIO_1_0 + MX28_PAD_LCD_D01__GPIO_1_1 + MX28_PAD_LCD_D02__GPIO_1_2 + MX28_PAD_LCD_D03__GPIO_1_3 + MX28_PAD_LCD_D04__GPIO_1_4 + MX28_PAD_LCD_D05__GPIO_1_5 + MX28_PAD_LCD_D06__GPIO_1_6 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + hog_pins_tiva: hog@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY3__GPIO_0_23 + MX28_PAD_GPMI_WRN__GPIO_0_25 + >; + fsl,voltage = ; + fsl,pull-up = ; + }; + + hog_pins_coding: hog@2 { + reg = <2>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D01__GPIO_0_1 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D04__GPIO_0_4 + MX28_PAD_GPMI_D06__GPIO_0_6 + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +®_fec_3v3 { + gpio = <&gpio0 0 0>; +}; + +®_usb_5v { + gpio = <&gpio0 2 0>; +}; + +&spi2_pins_a { + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__GPIO_2_19 + >; +}; From 14954ee82262f7a13accd12af18139e2ea8c3dcb Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 29 Apr 2021 10:52:19 +0800 Subject: [PATCH 133/511] ARM: dts: imx6ul-14x14-evk: Switch to fsl-asoc-card sound card There is issue with simple sound card, the simple sound card can't configure the pll of codec. [ 115.352669] wm8960 1-001a: failed to configure clock [ 115.358843] wm8960 1-001a: ASoC: error at snd_soc_dai_hw_params on wm8960-hifi: -22 So Switch to fsl-asoc-card and the fsl-asoc-card can support asrc module as front-end component. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 50 +++++++++++-------------- 1 file changed, 21 insertions(+), 29 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 5a1e10def6ef63..779cc536566d61 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -60,38 +60,26 @@ gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "mx6ul-wm8960"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai2>; + audio-codec = <&codec>; + audio-asrc = <&asrc>; + hp-det-gpio = <&gpio5 4 0>; + audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", - "Speaker", "SPK_LP", - "Speaker", "SPK_LN", - "Speaker", "SPK_RP", - "Speaker", "SPK_RN", - "LINPUT1", "Mic Jack", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", "LINPUT3", "Mic Jack", - "RINPUT1", "Mic Jack", - "RINPUT2", "Mic Jack"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; + "RINPUT1", "AMIC", + "RINPUT2", "AMIC", + "Mic Jack", "MICB", + "AMIC", "MICB"; }; spi4 { @@ -145,6 +133,10 @@ compatible = "wlf,wm8960"; reg = <0x1a>; wlf,shared-lrclk; + wlf,hp-cfg = <3 2 3>; + wlf,gpio-cfg = <1 3>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; }; camera@3c { From 034ebde3b8c7897fba4148bb8b59b856d34fcee9 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 29 Apr 2021 10:52:35 +0800 Subject: [PATCH 134/511] ARM: dts: imx7d-sdb: Add HDMI audio sound card Add HDMI audio sound card, the interface is sii902x. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index ac0751bc1177e1..4a0d83784d7d1d 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -164,6 +164,13 @@ "LINPUT1", "AMIC", "AMIC", "MICB"; }; + + sound-hdmi { + compatible = "fsl,imx-audio-sii902x"; + model = "sii902x-audio"; + audio-cpu = <&sai3>; + hdmi-out; + }; }; &adc1 { From d178918891a1ed09711ac33ff93f7710be137826 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Fri, 30 Apr 2021 15:53:15 +0200 Subject: [PATCH 135/511] ARM: dts: imx6dl-yapp4: Use aliases to set custom MMC device indexes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Until commit fa2d0aa96941 ("mmc: core: Allow setting slot index via device tree alias") was introduced, our usdhc3 and usdhc4 devices were enumerated as mmc0 and mmc1. The mmc1 device is used to boot/update the board and its name must be fixed. With the referenced commit, aliases from imx6qdl.dtsi took effect. Override the aliases to get back the original device indexes. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index f2c7298aead1f1..d3921f297445dc 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -11,6 +11,8 @@ aliases: aliases { ethernet1 = ð1; ethernet2 = ð2; + mmc0 = &usdhc3; + mmc1 = &usdhc4; }; backlight: backlight { From 7486d6df6179a28c0dc7baf74b122e50d95bab61 Mon Sep 17 00:00:00 2001 From: Dillon Min Date: Tue, 4 May 2021 13:09:50 +0800 Subject: [PATCH 136/511] dt-bindings: add dasheng vendor prefix Add vendor prefix for DaSheng, Inc. Signed-off-by: Dillon Min Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b868cefc7c5500..71ca69ca91426c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -315,6 +315,8 @@ patternProperties: description: DPTechnics "^dragino,.*": description: Dragino Technology Co., Limited + "^ds,.*": + description: DaSheng, Inc. "^dserve,.*": description: dServe Technology B.V. "^dynaimage,.*": From db34eb5cc488457a02f74370f128362d34cf7a8b Mon Sep 17 00:00:00 2001 From: Dillon Min Date: Tue, 4 May 2021 13:09:51 +0800 Subject: [PATCH 137/511] dt-bindings: arm: imx: Add i.mx6q DaSheng COM-9XX SBC The DaSheng Com-9xx is and ARM based signle board computer (SBC) featuring: - i.MX6Q - 2GiB LPDDR3 DRAM - 8GiB eMMC 5.0 FLASH - 4MiB SPI Flash - USB 2.0 Host/Device - Multiple multi-protocol RS232/RS485 Serial ports - microSD socket - 5V DC power input - HDMI1.4a,1080p@60 - RGMIIx1 Gigabit Ethernet - CSI0x1, connect with ov2659 Signed-off-by: Dillon Min Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index eacbc1f8d4669d..fce2a8670b4925 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -197,6 +197,7 @@ properties: - boundary,imx6q-nitrogen6x - compulab,cm-fx6 # CompuLab CM-FX6 - dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board + - ds,imx6q-sbc # Da Sheng COM-9XX Modules - embest,imx6q-marsboard # Embest MarS Board i.MX6Dual - emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM - emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base From 4b7f6f3b251aaf455b45a8d4904bad0b59da0c8f Mon Sep 17 00:00:00 2001 From: Dillon Min Date: Tue, 4 May 2021 13:09:52 +0800 Subject: [PATCH 138/511] ARM: dts: imx: Add i.mx6q DaSheng COM-9XX SBC board support The DaSheng Com-9xx is and ARM based signle board computer (SBC) featuring: - i.MX6Q - 2GiB LPDDR3 DRAM - 8GiB eMMC 5.0 FLASH - 4MiB SPI Flash - USB 2.0 Host/Device - Multiple multi-protocol RS232/RS485 Serial ports - microSD socket - 5V DC power input - HDMI1.4a,1080p@60 - RGMIIx1 Gigabit Ethernet - CSI0x1, connect with ov2659 Signed-off-by: Dillon Min Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-ds.dts | 17 ++ arch/arm/boot/dts/imx6qdl-ds.dtsi | 458 ++++++++++++++++++++++++++++++ 3 files changed, 476 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-ds.dts create mode 100644 arch/arm/boot/dts/imx6qdl-ds.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4d05ad1bf5609c..c17cb7e36b5c93 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -513,6 +513,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ + imx6q-ds.dtb \ imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ diff --git a/arch/arm/boot/dts/imx6q-ds.dts b/arch/arm/boot/dts/imx6q-ds.dts new file mode 100644 index 00000000000000..b0a63a1339778e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ds.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2021 Dillon Min +// +// Based on imx6qdl-sabresd.dtsi which is: +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-ds.dtsi" + +/ { + model = "DaSheng i.MX6 Quad Com-9xx Board"; + compatible = "ds,imx6q-sbc", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ds.dtsi b/arch/arm/boot/dts/imx6qdl-ds.dtsi new file mode 100644 index 00000000000000..f7e51755569770 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ds.dtsi @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2021 Dillon Min +// +// Based on imx6qdl-sabresd.dtsi which is: +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vsync-active = <1>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&ov2659_to_ipu1_csi0_mux>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>; + status = "okay"; + + m25p80: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&phy>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov2659: camera@30 { + compatible = "ovti,ov2659"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov2659>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xvclk"; + reg = <0x30>; + powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov2659_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + link-frequencies = /bits/ 64 <70000000>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + >; + }; + + pinctrl_ecspi1_gpio: ecspi1grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_ov2659: ov2659grp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 + >; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; From 861920974aa5ce0c68899c575bbf1163520204e9 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 6 May 2021 11:41:18 +0800 Subject: [PATCH 139/511] ARM: dts: imx6qdl-sabresd: Add asrc support for wm8962 sound card Add asrc support for wm8962 sound card. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index f824c9abd11a36..d20eaac6c5d67b 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -99,6 +99,7 @@ model = "wm8962-audio"; ssi-controller = <&ssi2>; audio-codec = <&codec>; + audio-asrc = <&asrc>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", From 37f5929012581d113c30b97d2cb0f68b152b73b3 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 6 May 2021 11:41:19 +0800 Subject: [PATCH 140/511] ARM: dts: imx6qdl-sabresd: Configure the gpio for hp detect Configure the gpio for hp detect for wm8962 sound card Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index d20eaac6c5d67b..0c0105468a2fe6 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -97,6 +97,8 @@ compatible = "fsl,imx6q-sabresd-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; ssi-controller = <&ssi2>; audio-codec = <&codec>; audio-asrc = <&asrc>; @@ -546,6 +548,13 @@ >; }; + pinctrl_hp: hpgrp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 From 7ba861fff0cd3c34ca3401067a95eb12a6a581a6 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:40 +0800 Subject: [PATCH 141/511] dt-bindings: imx: gpcv2: add support for optional resets For some domains the resets of the devices in the domain are not automatically triggered. Add an optional resets property to allow the GPC driver to trigger those resets explicitly. The resets belong to devices located inside the power domain, which need to be held in reset across the power-up sequence. So we have no means to specify what each reset is in a generic power-domain binding. Same situation as with the clocks in this binding actually. Tested-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/power/fsl,imx-gpcv2.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index a96e6dbf185884..eb248f24dce622 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -66,6 +66,16 @@ properties: power-supply: true + resets: + description: | + A number of phandles to resets that need to be asserted during + power-up sequencing of the domain. The resets belong to devices + located inside the power domain, which need to be held in reset + across the power-up sequence. So no means to specify what each + reset is in a generic power-domain binding. + minItems: 1 + maxItems: 4 + required: - '#power-domain-cells' - reg From d943728fc7f258fb9a9414274d5eb60fdd15e853 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 11 May 2021 06:30:38 +0200 Subject: [PATCH 142/511] ARM: dts: imx6: edmqmx6: set phy-mode to RGMII-ID Latest kernel is actually using phy-mode property, so set proper value to make fec interface work again. Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index fa2307d8ce8610..c713ac03b3b92d 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -112,7 +112,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; phy-supply = <&vgen2_1v2_eth>; status = "okay"; From 723de6a4126b2474a8106e943749e1554012dad6 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 11 May 2021 06:30:39 +0200 Subject: [PATCH 143/511] ARM: dts: imx6dl-riotboard: configure PHY clock and set proper EEE value Without SoC specific PHY fixups the network interface on this board will fail to work. Provide missing DT properties to make it work again. Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 065d3ab0f50a7f..e7d9bfbfd0e4d5 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -106,6 +106,8 @@ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <1000>; + qca,smarteee-tw-us-1g = <24>; + qca,clk-out-frequency = <125000000>; }; }; }; From 77e6025c2416c3c7d98f8c07befc722ada4429ea Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 May 2021 15:58:35 +0200 Subject: [PATCH 144/511] ARM: dts: i.MX51: digi-connectcore-som: Correct Ethernet node name make dtbs_check: lan9221@5,0: $nodename:0: 'lan9221@5,0' does not match '^ethernet(@.*)?$' Signed-off-by: Geert Uytterhoeven Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 16addb3a2a1b4e..7d4970417dce8f 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -206,7 +206,7 @@ pinctrl-0 = <&pinctrl_weim>; status = "okay"; - lan9221: lan9221@5,0 { + lan9221: ethernet@5,0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lan9221>; compatible = "smsc,lan9221", "smsc,lan9115"; From 1c147690231b65a1e56840453cc8e2f92950e076 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 20 May 2021 15:58:36 +0200 Subject: [PATCH 145/511] ARM: dts: imx53-ard: Correct Ethernet node name make dtbs_check: lan9220@f4000000: $nodename:0: 'lan9220@f4000000' does not match '^ethernet(@.*)?$' Signed-off-by: Geert Uytterhoeven Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ard.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 9a2e1fde712879..6208fbb2e74104 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -24,7 +24,7 @@ reg = <0xf4000000 0x3ff0000>; ranges; - lan9220@f4000000 { + ethernet@f4000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0xf4000000 0x2000000>; phy-mode = "mii"; From e409c1e1d5cb164361229e3a3f084e4a32544fb6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 24 May 2021 01:14:29 +0200 Subject: [PATCH 146/511] ARM: dts: ux500: Fix orientation of Janice accelerometer This fixes up the axis on the Janice accelerometer to give the right orientation according to tests. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index eaf8039d10ad63..25af066f6f3ae3 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -583,10 +583,9 @@ accelerometer@08 { compatible = "bosch,bma222"; reg = <0x08>; - /* FIXME: no idea about this */ - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "1"; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "-1"; vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V }; From 091d5db0abd6d2530c6c942067ac5c78e64d4d08 Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Thu, 29 Apr 2021 22:58:59 -0500 Subject: [PATCH 147/511] arm64: dts: allwinner: pinephone: Set audio card name Add the "PinePhone" name to the sound card: this will make upstreaming an ALSA UCM config easier as we can use a unique name. It also avoids an issue where the default card name is truncated. Signed-off-by: Arnaud Ferraris [Samuel: Split out change, updated commit message] Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210430035859.3487-8-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 4759cd97684389..5b44a979f2503d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -433,6 +433,7 @@ &sound { status = "okay"; + simple-audio-card,name = "PinePhone"; simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; simple-audio-card,widgets = "Microphone", "Headset Microphone", "Microphone", "Internal Microphone", From 47b99d02bd8705a93671723a957b50d3875afb56 Mon Sep 17 00:00:00 2001 From: Steven Lee Date: Mon, 24 May 2021 15:32:53 +0800 Subject: [PATCH 148/511] ARM: dts: aspeed: ast2600evb: Add sdhci node and gpio regulator for A2 evb. AST2600 A2 (or newer) EVB has gpio regulators for toggling signal voltage between 3.3v and 1.8v, the patch adds sdhci node and gpio regulator in the dts file and adds comment for describing the reference design. Signed-off-by: Steven Lee Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210524073308.9328-2-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 2772796e215e70..401034da6dccb6 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "aspeed-g6.dtsi" +#include / { model = "AST2600 EVB"; @@ -21,6 +22,46 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + vcc_sdhci0: regulator-vcc-sdhci0 { + compatible = "regulator-fixed"; + regulator-name = "SDHCI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhci0: regulator-vccq-sdhci0 { + compatible = "regulator-gpio"; + regulator-name = "SDHCI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, + <1800000 0>; + }; + + vcc_sdhci1: regulator-vcc-sdhci1 { + compatible = "regulator-fixed"; + regulator-name = "SDHCI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhci1: regulator-vccq-sdhci1 { + compatible = "regulator-gpio"; + regulator-name = "SDHCI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, + <1800000 0>; + }; }; &mdio0 { @@ -245,3 +286,46 @@ &uhci { status = "okay"; }; + +&sdc { + status = "okay"; +}; + +/* + * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be + * toggled by GPIO pins. + * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the + * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to + * a 1.8v and a 3.3v power load switch that provides signal voltage to + * sdhci0 bus. + * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled. + * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal + * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled, + * sdhci0 signal voltage becomes 1.8v. + * AST2600-A2 EVB also supports toggling signal voltage for sdhci1. + * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3 + * as power-switch-gpio. + */ +&sdhci0 { + status = "okay"; + bus-width = <4>; + max-frequency = <100000000>; + sdhci-drive-type = /bits/ 8 <3>; + sdhci-caps-mask = <0x7 0x0>; + sdhci,wp-inverted; + vmmc-supply = <&vcc_sdhci0>; + vqmmc-supply = <&vccq_sdhci0>; + clk-phase-sd-hs = <7>, <200>; +}; + +&sdhci1 { + status = "okay"; + bus-width = <4>; + max-frequency = <100000000>; + sdhci-drive-type = /bits/ 8 <3>; + sdhci-caps-mask = <0x7 0x0>; + sdhci,wp-inverted; + vmmc-supply = <&vcc_sdhci1>; + vqmmc-supply = <&vccq_sdhci1>; + clk-phase-sd-hs = <7>, <200>; +}; From 2c042ff716f11996a11935cdb7744a4290d726cd Mon Sep 17 00:00:00 2001 From: Steven Lee Date: Mon, 24 May 2021 15:32:54 +0800 Subject: [PATCH 149/511] ARM: dts: aspeed: ast2600evb: Add phase correction for emmc controller. Set MMC timing-phase register by adding the phase correction binding in the device tree. Signed-off-by: Steven Lee Acked-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20210524073308.9328-3-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 401034da6dccb6..c670f3a45fbb36 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -148,7 +148,8 @@ &emmc { non-removable; bus-width = <4>; - max-frequency = <52000000>; + max-frequency = <100000000>; + clk-phase-mmc-hs200 = <9>, <225>; }; &rtc { From a7295518037289cb3e6a8aba85e38720e040b6c3 Mon Sep 17 00:00:00 2001 From: Steven Lee Date: Mon, 24 May 2021 15:32:55 +0800 Subject: [PATCH 150/511] ARM: dts: aspeed: ast2600evb: Add dts file for A1 and A0 aspeed-ast2600-evb.dts was modified for supporting A2 evb. Since A1/A0 evbs don't have GPIO regulators and SD clock frequency (SCU210) is different to A2 as well. Adding a new dts that removes new nodes created in aspeed-ast2600-evb.dts is necessary. Signed-off-by: Steven Lee Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210524073308.9328-4-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e750..f28a8dfba14244 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1415,6 +1415,7 @@ dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ + aspeed-ast2600-evb-a1.dtb \ aspeed-ast2600-evb.dtb \ aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-ampere-mtjade.dtb \ diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts new file mode 100644 index 00000000000000..dd7148060c4a33 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2021 IBM Corp. + +#include "aspeed-ast2600-evb.dts" + +/ { + model = "AST2600 A1 EVB"; + + /delete-node/regulator-vcc-sdhci0; + /delete-node/regulator-vcc-sdhci1; + /delete-node/regulator-vccq-sdhci0; + /delete-node/regulator-vccq-sdhci1; +}; + +/delete-node/ &sdc; From ab2711b3afdb04e0257cd7f1c8cd2c186348bdef Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 24 Feb 2021 05:51:42 -0600 Subject: [PATCH 151/511] ARM: dts: renesas: Add fck to etheravb-rcar-gen2 clock-names list The bindings have been updated to support two clocks. Add a clock-names list in the device tree with fck in it. Signed-off-by: Adam Ford Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20210224115146.9131-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 1 + arch/arm/boot/dts/r8a7743.dtsi | 1 + arch/arm/boot/dts/r8a7744.dtsi | 1 + arch/arm/boot/dts/r8a7745.dtsi | 1 + arch/arm/boot/dts/r8a77470.dtsi | 1 + arch/arm/boot/dts/r8a7790.dtsi | 1 + arch/arm/boot/dts/r8a7791.dtsi | 1 + arch/arm/boot/dts/r8a7792.dtsi | 1 + arch/arm/boot/dts/r8a7794.dtsi | 1 + 9 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index dd1b976d2a6c81..8e989063d7027d 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -750,6 +750,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 6e37b8da278b91..16e3bf01fc88f0 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -702,6 +702,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index ace20861c0c496..4865e39164fafa 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -702,6 +702,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index be33bdabe45281..36892ea87d7df9 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -645,6 +645,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index a1d7f6e7a2e34b..5d1f3570d5c7ed 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -537,6 +537,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index de29394eed6360..f7c4b52b8c26a5 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -768,6 +768,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 9d8320f71a6a83..f05d7541f87ec5 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -728,6 +728,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 253e8bf643d182..bd7ff205433e8e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -537,6 +537,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 330dc516ecd151..0035770e74de80 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -598,6 +598,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; From 56ed0b3b10fd2814cb8225c420000a51bb202e31 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 24 Feb 2021 05:51:43 -0600 Subject: [PATCH 152/511] arm64: dts: renesas: Add fck to etheravb-rcar-gen3 clock-names list The bindings have been updated to support two clocks. Add a clock-names list in the device tree with fck in it. Signed-off-by: Adam Ford Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20210224115146.9131-3-aford173@gmail.com [geert: Update new r8a779a0.dtsi] Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77951.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77960.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77961.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 6 ++++++ 13 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 46f8dbf6890482..c3d312af6fe95f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1127,6 +1127,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index d16a4be5ef77a2..28c612ce49c0ff 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1001,6 +1001,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 1aef34447abd1b..a5d4dce8476d7e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -957,6 +957,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 1f51237ab0a648..379a1300272ba3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1230,6 +1230,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 85d66d15465ab2..2e4c18b8eee49f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1312,6 +1312,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 12476e354d746d..d21be2f195b3be 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1188,6 +1188,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index d9804768425a76..941f18e5f5d29c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1144,6 +1144,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index dcb9df861d7496..ad69da362a72ef 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1050,6 +1050,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index e8f6352c3665f4..517892cf6294a9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -612,6 +612,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 7b51d464de0eac..6347d15e66b64f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -664,6 +664,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 0eaea58f4210d8..4d0304bc9745a4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1000,6 +1000,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 2319271c881b69..84dba37193818a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -760,6 +760,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 70b3604e56cd7c..a023e094e7670e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -618,6 +618,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 211>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 211>; phy-mode = "rgmii"; @@ -665,6 +666,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 212>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 212>; phy-mode = "rgmii"; @@ -712,6 +714,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 213>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 213>; phy-mode = "rgmii"; @@ -759,6 +762,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 214>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 214>; phy-mode = "rgmii"; @@ -806,6 +810,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 215>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 215>; phy-mode = "rgmii"; @@ -853,6 +858,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 216>; phy-mode = "rgmii"; From 0decd50b6b2ef085f3f6c018b5e7eb8ba627b11e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 24 Feb 2021 05:51:45 -0600 Subject: [PATCH 153/511] arm64: dts: renesas: beacon kit: Setup AVB refclk The AVB reference clock assumes an external clock that runs automatically. Because the Versaclock is wired to provide the AVB refclock, the device tree needs to reference it in order for the driver to start the clock. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20210224115146.9131-5-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 8d3a4d6ee88539..75355c354c38f7 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -53,6 +53,8 @@ phy-handle = <&phy0>; rx-internal-delay-ps = <1800>; tx-internal-delay-ps = <2000>; + clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>; + clock-names = "fck", "refclk"; status = "okay"; phy0: ethernet-phy@0 { From 706f5cb338ff9d7ce68deb1d5a349e5797affa8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 13 Apr 2021 20:14:47 +0200 Subject: [PATCH 154/511] arm64: dts: renesas: falcon-csi-dsi: Add GPIO extenders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to configure their GPIOs to power on the MAX96712s. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20210413181447.2588084-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779a0-falcon-csi-dsi.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi index 14d3db5d6c1648..f791c76f1bcff9 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -6,6 +6,27 @@ */ &i2c0 { + pca9654_a: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9654_b: gpio@22 { + compatible = "onnn,pca9654"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9654_c: gpio@23 { + compatible = "onnn,pca9654"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + eeprom@52 { compatible = "rohm,br24g01", "atmel,24c01"; label = "csi-dsi-sub-board-id"; From b6810bafc34f9c91e1404cee87ed69a911f1e428 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 19 Apr 2021 16:38:58 +0200 Subject: [PATCH 155/511] arm64: dts: renesas: condor: Switch eMMC bus to 1V8 The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND array and the VCCQ supplies the bus. On Condor, the VCC is connected to 3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust the pinmux to match the bus, which is always operating in 1.8V mode. While at it, deduplicate the pinmux entries, which are now the same for both default and UHS modes. We still need the two pinctrl entries to match the bindings though. Thanks to Marek Vasut for this description from commit 5f65328df3f5cd25 ("arm64: dts: renesas: Switch eMMC bus to 1V8 on Salvator-X and ULCB"). Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20210419143858.39401-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 04d47c0c9bb993..7bde0a549c0988 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -210,7 +210,7 @@ &mmc0 { pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins_uhs>; + pinctrl-1 = <&mmc_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <&d3_3v>; @@ -253,12 +253,6 @@ }; mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <3300>; - }; - - mmc_pins_uhs: mmc_uhs { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc"; power-source = <1800>; From a422ec20caef6a50cf3c1efa93538888ebd576a6 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Fri, 26 Mar 2021 13:10:50 +0100 Subject: [PATCH 156/511] arm64: dts: renesas: v3msk: Fix memory size The V3MSK board has 2 GiB RAM according to the datasheet and schematics. Signed-off-by: Valentine Barshak [geert: Verified schematics] Fixes: cc3e267e9bb0ce7f ("arm64: dts: renesas: initial V3MSK board device tree") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20210326121050.1578460-1-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 7417cf5fea0f0a..2426e533128ceb 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -59,7 +59,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; + reg = <0x0 0x48000000 0x0 0x78000000>; }; osc5_clk: osc5-clock { From 6ab8c23096a29b69044209a5925758a6f88bd450 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 29 Apr 2021 14:41:15 +0200 Subject: [PATCH 157/511] ARM: dts: r8a7779, marzen: Fix DU clock names "make dtbs_check" complains: arch/arm/boot/dts/r8a7779-marzen.dt.yaml: display@fff80000: clock-names:0: 'du.0' was expected Change the first clock name to match the DT bindings. This has no effect on actual operation, as the Display Unit driver in Linux does not use the first clock name on R-Car H1, but just grabs the first clock. Fixes: 665d79aa47cb3983 ("ARM: shmobile: marzen: Add DU external pixel clock to DT") Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/9d5e1b371121883b3b3e10a3df43802a29c6a9da.1619699965.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7779-marzen.dts | 2 +- arch/arm/boot/dts/r8a7779.dtsi | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index d2240b89ee5292..46584532349590 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -145,7 +145,7 @@ status = "okay"; clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; - clock-names = "du", "dclkin.0"; + clock-names = "du.0", "dclkin.0"; ports { port@0 { diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 74d7e9084eabe1..3c5fcdfe16b871 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -463,6 +463,7 @@ reg = <0xfff80000 0x40000>; interrupts = ; clocks = <&mstp1_clks R8A7779_CLK_DU>; + clock-names = "du.0"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; status = "disabled"; From 8c10e004dfb94e93f1ac76da47c27b96c9de94ef Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 15:10:51 +0200 Subject: [PATCH 158/511] ARM: dts: koelsch: Rename sw2 to keyboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename "sw2_pins" and "sw2" to "keyboard_pins" resp. "keyboard", to comply with generic name recommendations. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/3d718cf69e21b1ceea0c29c0e841b9bdda44533d.1619785905.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7791-koelsch.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 61e881bbbf6ee5..2a8b6fd9095cce 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -81,7 +81,7 @@ keyboard { compatible = "gpio-keys"; - pinctrl-0 = <&sw2_pins>; + pinctrl-0 = <&keyboard_pins>; pinctrl-names = "default"; key-1 { @@ -622,7 +622,7 @@ function = "audio_clk"; }; - sw2_pins: sw2 { + keyboard_pins: keyboard { pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; bias-pull-up; }; From e9550a536e3edd23b88926a6fb27fa200b56dfa9 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 4 May 2021 11:14:34 +0200 Subject: [PATCH 159/511] arm64: dts: renesas: eagle: Add x1 clock This adds X1 clock which supplies a frequency of 148.5 MHz. This clock is connected to the external dot clock input signal. Signed-off-by: Valentine Barshak [geert: Verified schematics] Signed-off-by: Geert Uytterhoeven Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart Tested-by: Kieran Bingham Link: https://lore.kernel.org/r/75a66bae21937da1c69e8024ce61b35aad4ac9b8.1620119570.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 874a7fc2730b00..5c84681703edad 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -73,6 +73,12 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + x1_clk: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; }; &avb { @@ -104,6 +110,8 @@ }; &du { + clocks = <&cpg CPG_MOD 724>, <&x1_clk>; + clock-names = "du.0", "dclkin.0"; status = "okay"; }; From d4ea5c61e15adb3995a9944b96e842ce7faaa450 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 May 2021 16:41:24 +0200 Subject: [PATCH 160/511] ARM: dts: rcar-gen1: Correct internal delay for i2c[123] According to the R-Car M1A and H1 Hardware User's Manuals Rev. 1.00, the LSI internal delay for I2C instances 1 to 3 is 5 ns (typ.), which differs from the default 50 ns as specified for instance 0. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/1eac63f15a776e492ff8a2d8447c5e1019982dd1.1620138979.git.geert+renesas@glider.be Link: https://lore.kernel.org/r/73c96fd455df82ef04fd1db6d7dd79b4679f6c56.1620138979.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7778.dtsi | 3 +++ arch/arm/boot/dts/r8a7779.dtsi | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index c9f8735860bf82..95efbafb0b7077 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -166,6 +166,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7778_CLK_I2C1>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -177,6 +178,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7778_CLK_I2C2>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -188,6 +190,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7778_CLK_I2C3>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 3c5fcdfe16b871..39fc58f32df61b 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -198,6 +198,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7779_CLK_I2C1>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -209,6 +210,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7779_CLK_I2C2>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -220,6 +222,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7779_CLK_I2C3>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; From 56bc54496f5d6bc638127bfc9df3742cbf0039e7 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 13 May 2021 06:46:15 -0500 Subject: [PATCH 161/511] arm64: dts: renesas: beacon: Fix USB extal reference The USB extal clock reference isn't associated to a crystal, it's associated to a programmable clock, so remove the extal reference, add the usb2_clksel. Since usb_extal is referenced by the versaclock, reference it here so the usb2_clksel can get the proper clock speed of 50MHz. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20210513114617.30191-1-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 75355c354c38f7..090dc9c4f57b5b 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -321,8 +321,10 @@ status = "okay"; }; -&usb_extal_clk { - clock-frequency = <50000000>; +&usb2_clksel { + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&versaclock5 3>, <&usb3s0_clk>; + status = "okay"; }; &usb3s0_clk { From ebc666f39ff67a01e748c34d670ddf05a9e45220 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 13 May 2021 06:46:16 -0500 Subject: [PATCH 162/511] arm64: dts: renesas: beacon: Fix USB ref clock references The RZ/G2 boards expect there to be an external clock reference for USB2 EHCI controllers. For the Beacon boards, this reference clock is controlled by a programmable versaclock. Because the RZ/G2 family has a special clock driver when using an external clock, the third clock reference in the EHCI node needs to point to this special clock, called usb2_clksel. Since the usb2_clksel does not keep the usb_extal clock enabled, the 4th clock entry for the EHCI nodes needs to reference it to keep the clock running and make USB functional. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20210513114617.30191-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index d8046fedf9c129..e3c8b2fe143ea4 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -271,12 +271,12 @@ &ehci0 { dr_mode = "otg"; status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; }; &ehci1 { status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; }; &hdmi0 { From a499e40a397c17a40af8a5f8ef408fe63be4c257 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 19 May 2021 14:31:37 +0200 Subject: [PATCH 163/511] ARM: dts: renesas: Move enable-method to CPU nodes According to Documentation/devicetree/bindings/arm/cpus.yaml, the "enable-method" property should be a property of the individual CPU nodes, and not of the parent "cpus" container node. However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the "cpus" node instead. Secondary CPU bringup and CPU hot (un)plug work regardless, as arm_dt_init_cpu_maps() falls back to looking in the "cpus" node. The cpuidle code does not have such a fallback, so it does not detect the enable-method. Note that cpuidle does not support the "renesas,apmu" enable-method yet, so for now this does not make any difference. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7742.dtsi | 5 ++++- arch/arm/boot/dts/r8a7743.dtsi | 3 ++- arch/arm/boot/dts/r8a7744.dtsi | 3 ++- arch/arm/boot/dts/r8a7745.dtsi | 3 ++- arch/arm/boot/dts/r8a77470.dtsi | 3 ++- arch/arm/boot/dts/r8a7790.dtsi | 9 ++++++++- arch/arm/boot/dts/r8a7791.dtsi | 3 ++- arch/arm/boot/dts/r8a7792.dtsi | 3 ++- arch/arm/boot/dts/r8a7793.dtsi | 3 ++- arch/arm/boot/dts/r8a7794.dtsi | 3 ++- 10 files changed, 28 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 8e989063d7027d..a2279686ffcccb 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -47,7 +47,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -56,6 +55,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -77,6 +77,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -98,6 +99,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU2>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -119,6 +121,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU3>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 16e3bf01fc88f0..7e5e09d210ec5a 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -49,7 +49,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -59,6 +58,7 @@ clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -78,6 +78,7 @@ clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 4865e39164fafa..8419683a9d8391 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -49,7 +49,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -59,6 +58,7 @@ clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7744_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -78,6 +78,7 @@ clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7744_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 36892ea87d7df9..f877c51f769cb7 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -64,7 +64,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -73,6 +72,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; power-domains = <&sysc R8A7745_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -83,6 +83,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; power-domains = <&sysc R8A7745_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 5d1f3570d5c7ed..13ef1e9bf4d5e2 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -25,7 +25,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -34,6 +33,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; power-domains = <&sysc R8A77470_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -44,6 +44,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; power-domains = <&sysc R8A77470_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index f7c4b52b8c26a5..ed6dd4fcc503cb 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -69,7 +69,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -78,6 +77,7 @@ clock-frequency = <1300000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -99,6 +99,7 @@ clock-frequency = <1300000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -120,6 +121,7 @@ clock-frequency = <1300000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -141,6 +143,7 @@ clock-frequency = <1300000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -162,6 +165,7 @@ clock-frequency = <780000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; }; @@ -173,6 +177,7 @@ clock-frequency = <780000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; }; @@ -184,6 +189,7 @@ clock-frequency = <780000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; }; @@ -195,6 +201,7 @@ clock-frequency = <780000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f05d7541f87ec5..0ccc162d3c2c98 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -68,7 +68,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -77,6 +76,7 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; voltage-tolerance = <1>; /* 1% */ clock-latency = <300000>; /* 300 us */ @@ -97,6 +97,7 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; voltage-tolerance = <1>; /* 1% */ clock-latency = <300000>; /* 300 us */ diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index bd7ff205433e8e..9cdb73894ac23a 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -45,7 +45,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -54,6 +53,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; }; @@ -64,6 +64,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; }; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 6d74475030edfe..dea4b1e108af0a 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -60,7 +60,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -69,6 +68,7 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; voltage-tolerance = <1>; /* 1% */ clock-latency = <300000>; /* 300 us */ @@ -89,6 +89,7 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; voltage-tolerance = <1>; /* 1% */ clock-latency = <300000>; /* 300 us */ diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 0035770e74de80..eac9ed8df0befb 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -62,7 +62,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -71,6 +70,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -81,6 +81,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; From f11d3e7da32e5f3f063f0ee0ed83295c303462c2 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Tue, 13 Apr 2021 12:05:52 -0500 Subject: [PATCH 164/511] arm64: dts: qcom: sm8350: add IPA information Add IPA-related nodes and definitions to "sm8350.dtsi", which uses IPA v4.9. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210413170553.1778792-2-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ed0b51bc03ea7a..2fc23f3d2c75c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -391,6 +392,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; smp2p-slpi { @@ -629,6 +641,45 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ipa: ipa@1e40000 { + compatible = "qcom,sm8350-ipa"; + + iommus = <&apps_smmu 0x5c0 0x0>, + <&apps_smmu 0x5c2 0x0>; + reg = <0 0x1e40000 0 0x8000>, + <0 0x1e50000 0 0x4b20>, + <0 0x1e04000 0 0x23000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_llcc", + "llcc_to_ebi1", + "appss_to_ipa"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; From adfea97e49297f376b7481041e7ec022b358fa66 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Tue, 13 Apr 2021 12:05:53 -0500 Subject: [PATCH 165/511] arm64: dts: qcom: sm8350-mtp: enable IPA Enable IPA for the SM8350 MTP. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210413170553.1778792-3-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 6ca638b4e32131..93740444dd1eaf 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -364,3 +364,9 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l5b_0p88>; }; + +&ipa { + status = "okay"; + + memory-region = <&pil_ipa_fw_mem>; +}; From 5eabd602d2ff5c9b3fbd250ab09e355336691d8e Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Mon, 29 Jun 2020 19:21:44 +0530 Subject: [PATCH 166/511] arm64: dts: qcom: sc7180: add nodes for idp display Add nodes for IDP display. The display is Visionox RM69299. Signed-off-by: Harigovindan P Link: https://lore.kernel.org/r/20200629135144.8265-1-harigovi@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 65 +++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index e77a7926034a72..d2a867ca493291 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -9,6 +9,7 @@ #include #include +#include #include "sc7180.dtsi" #include "pm6150.dtsi" #include "pm6150l.dtsi" @@ -288,6 +289,57 @@ }; }; +&dsi0 { + status = "okay"; + + vdda-supply = <&vreg_l3c_1p2>; + + panel@0 { + compatible = "visionox,rm69299-1080p-display"; + reg = <0>; + + vdda-supply = <&vreg_l8c_1p8>; + vdd3p3-supply = <&vreg_l18a_2p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&disp_pins>; + + reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi_phy { + status = "okay"; +}; + +&mdp { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + &qfprom { vcc-supply = <&vreg_l11a_1p8>; }; @@ -414,6 +466,19 @@ /* PINCTRL - additions to nodes defined in sc7180.dtsi */ +&pm6150l_gpio { + disp_pins: disp-pins { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_FUNC1; + qcom,drive-strength = ; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; + &qspi_clk { pinconf { pins = "gpio63"; From e60fd5ac1f6851be5b2c042b39584bfcf8a66f57 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Sun, 2 May 2021 01:42:57 +0000 Subject: [PATCH 167/511] arm64: dts: qcom: sdm845-oneplus-common: guard rmtfs-mem The rmtfs_mem region is a weird one, downstream allocates it dynamically, and supports a "qcom,guard-memory" property which when set will reserve 4k above and below the rmtfs memory. A common from qcom 4.9 kernel msm_sharedmem driver: /* * If guard_memory is set, then the shared memory region * will be guarded by SZ_4K at the start and at the end. * This is needed to overcome the XPU limitation on few * MSM HW, so as to make this memory not contiguous with * other allocations that may possibly happen from other * clients in the system. */ When the kernel tries to touch memory that is too close the rmtfs region it may cause an XPU violation. Such is the case on the OnePlus 6 where random crashes would occur usually after boot. Reserve 4k above and below the rmtfs_mem to avoid hitting these XPU Violations. This doesn't entirely solve the random crashes on the OnePlus 6/6T but it does seem to prevent the ones which happen shortly after modem bringup. Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices") Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20210502014146.85642-4-caleb@connolly.tech Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 8f617f7b6d34e7..f712771df0c77a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -46,6 +46,14 @@ }; reserved-memory { + /* The rmtfs_mem needs to be guarded due to "XPU limitations" + * it is otherwise possible for an allocation adjacent to the + * rmtfs_mem region to trigger an XPU violation, causing a crash. + */ + rmtfs_lower_guard: memory@f5b00000 { + no-map; + reg = <0 0xf5b00000 0 0x1000>; + }; /* * The rmtfs memory region in downstream is 'dynamically allocated' * but given the same address every time. Hard code it as this address is @@ -59,6 +67,10 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; + rmtfs_upper_guard: memory@f5d01000 { + no-map; + reg = <0 0xf5d01000 0 0x2000>; + }; /* * It seems like reserving the old rmtfs_mem region is also needed to prevent From c572729b57b4a635fd655b481fb96c5065ad300b Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Sun, 2 May 2021 01:43:09 +0000 Subject: [PATCH 168/511] arm64: dts: qcom: sdm845-oneplus-common: enable ipa Enable the ipa node so that we can bring up mobile data. Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20210502014146.85642-5-caleb@connolly.tech Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index f712771df0c77a..4d052e39b34891 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -399,6 +399,12 @@ }; }; +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; +}; + &mdss { status = "okay"; }; From ab7f9be0e4f0f211dcb2281fe0fb09f91e26c3c0 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Mon, 3 May 2021 07:47:31 +0530 Subject: [PATCH 169/511] arm64: dts: qcom: sdm845-xiaomi-beryllium: Add audio support This patch adds audio support for Xiaomi Poco F1 phone. Phone's primary Mic and 3.5mm Headphone jack are handled through the SDM845 sound card and WCD9340 codec. Tested-by: Amit Pundir Reviewed-by: Srinivas Kandagatla Signed-off-by: Joel Selvaraj Link: https://lore.kernel.org/r/BN6PR2001MB17966ED1D787FA3F4B90A1A7D95B9@BN6PR2001MB1796.namprd20.prod.outlook.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 7d029425336e40..c60c8c640e17fc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -5,6 +5,8 @@ #include #include #include +#include +#include #include "sdm845.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" @@ -311,6 +313,28 @@ }; }; +/* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ +&q6afedai { + qi2s@22 { + reg = <22>; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -328,6 +352,70 @@ cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; }; +&sound { + compatible = "qcom,db845c-sndcard"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active>; + pinctrl-names = "default"; + model = "Xiaomi Poco F1"; + audio-routing = + "RX_BIAS", "MCLK", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 0>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 1>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; @@ -356,6 +444,15 @@ function = "gpio"; bias-pull-up; }; + + wcd_intr_default: wcd_intr_default { + pins = <54>; + function = "gpio"; + + input-enable; + bias-pull-down; + drive-strength = <2>; + }; }; &uart6 { @@ -416,6 +513,23 @@ vdda-pll-supply = <&vreg_l1a_0p875>; }; +&wcd9340{ + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + reset-gpios = <&tlmm 64 0>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + qcom,micbias1-microvolt = <2700000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <2700000>; + qcom,micbias4-microvolt = <2700000>; +}; + &wifi { status = "okay"; From 59312ab139810229fd76603e4e8e49ecb2f3dfc2 Mon Sep 17 00:00:00 2001 From: Sergey Senozhatsky Date: Tue, 25 May 2021 22:32:42 +0900 Subject: [PATCH 170/511] arm64: dts: qcom: remove camera_mem region qcom camera driver allocates the ICP firmware memory dynamically, so the carveout region is unnecessary. Reviewed-by: Stephen Boyd Signed-off-by: Sergey Senozhatsky Link: https://lore.kernel.org/r/20210525133242.188603-1-senozhatsky@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 24d293ef56d7b4..b89e6f78fd20f9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -64,11 +64,6 @@ no-map; }; - camera_mem: memory@8ec00000 { - reg = <0x0 0x8ec00000 0x0 0x500000>; - no-map; - }; - venus_mem: memory@8f600000 { reg = <0 0x8f600000 0 0x500000>; no-map; From 6215d3f07bd713eec627aa92d0b2bd9d3262da53 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 6 May 2021 21:18:52 +0000 Subject: [PATCH 171/511] arm64: dts: qcom: msm8996: Disable ADSP and add power domains Disable ADSP by default and enable it in devices that use it. Also add CX power domain. Signed-off-by: Yassine Oudjana Link: https://lore.kernel.org/r/Epn1vFjJb0oQhqMYxspzL6X1N6MPcDT1f9oVVOjXc@cp3-web-020.plabs.ch Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index defcbd15edf910..409a5dec26159f 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -162,6 +162,10 @@ }; }; +&adsp_pil { + status = "okay"; +}; + &blsp2_i2c0 { /* On High speed expansion */ label = "HS-I2C2"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ce430ba9c1183a..7e647843f7c79d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include / { @@ -2067,6 +2068,11 @@ qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; + power-domains = <&rpmpd MSM8996_VDDCX>; + power-domain-names = "cx"; + + status = "disabled"; + smd-edge { interrupts = ; From 1ed34da63a37f773f957174d4b6122f9e08d158c Mon Sep 17 00:00:00 2001 From: Gokul Sriram Palanisamy Date: Fri, 26 Feb 2021 13:58:30 +0530 Subject: [PATCH 172/511] arm64: dts: qcom: Add board support for HK10 Add initial support for IPQ8074 SoC based HK10-C1 and HK10-C2 evaluation boards. Signed-off-by: Gokul Sriram Palanisamy Link: https://lore.kernel.org/r/1614328110-28866-2-git-send-email-gokulsri@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 11 +++ arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 10 +++ arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 76 ++++++++++++++++++++ 4 files changed, 99 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 456502aeee49b6..d452b26d531d3e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts new file mode 100644 index 00000000000000..2bfcf42aeabc92 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ +/dts-v1/; + +#include "ipq8074-hk10.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C1"; + compatible = "qcom,ipq8074-hk10-c1", "qcom,ipq8074"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts new file mode 100644 index 00000000000000..7da39f1d979b99 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; +/* Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ +#include "ipq8074-hk10.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2"; + compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi new file mode 100644 index 00000000000000..07e67082967672 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +/dts-v1/; + +#include "ipq8074.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x20000000>; + }; +}; + +&blsp1_spi1 { + status = "ok"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart5 { + status = "ok"; +}; + +&pcie0 { + status = "ok"; + perst-gpio = <&tlmm 58 0x1>; +}; + +&pcie1 { + status = "ok"; + perst-gpio = <&tlmm 61 0x1>; +}; + +&pcie_phy0 { + status = "ok"; +}; + +&pcie_phy1 { + status = "ok"; +}; + +&qpic_bam { + status = "ok"; +}; + +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; From 35a4a8b6e9b133cf3a7d059ad4cf0e24cb4bd029 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:19 +0100 Subject: [PATCH 173/511] arm64: dts: qcom: msm8996: Sanitize pins In order to prepare for feature development, the DTs have to be workable with.. To achieve that: - Rename msmgpio to tlmm (consistency with newer DTs) - Rid msm8996-pins.dtsi and add the contents to msm8996.dtsi - Modernize the pin nodes, make them more concise - Add generic pin configuration for some hardware - Fix up some names in preparation for BLSP/UART name cleaning.. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 22 +- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 8 +- arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 653 ------------------- arch/arm64/boot/dts/qcom/msm8996.dtsi | 508 ++++++++++++++- 4 files changed, 502 insertions(+), 689 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/msm8996-pins.dtsi diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 409a5dec26159f..4212f5c6e8b662 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -188,16 +188,16 @@ label = "LS-UART1"; status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_2pins_default>; - pinctrl-1 = <&blsp2_uart1_2pins_sleep>; + pinctrl-0 = <&blsp2_uart2_2pins_default>; + pinctrl-1 = <&blsp2_uart2_2pins_sleep>; }; &blsp2_uart2 { label = "LS-UART0"; status = "disabled"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_4pins_default>; - pinctrl-1 = <&blsp2_uart2_4pins_sleep>; + pinctrl-0 = <&blsp2_uart3_4pins_default>; + pinctrl-1 = <&blsp2_uart3_4pins_sleep>; }; &camss { @@ -249,7 +249,7 @@ vdd-gfx-supply = <&vdd_gfx>; }; -&msmgpio { +&tlmm { gpio-line-names = "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ @@ -509,20 +509,20 @@ &pcie0 { status = "okay"; - perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>; + perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; }; &pcie1 { status = "okay"; - perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>; + perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; &pcie2 { status = "okay"; - perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>; + perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; @@ -933,9 +933,9 @@ &sdhc2 { /* External SD card */ pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 0x1>; + pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vreg_l13a_2p95>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index f6ddf17ada81b9..9b55eae39e3eb3 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -84,11 +84,11 @@ &blsp2_uart1 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_2pins_default>; - pinctrl-1 = <&blsp2_uart1_2pins_sleep>; + pinctrl-0 = <&blsp2_uart2_2pins_default>; + pinctrl-1 = <&blsp2_uart2_2pins_sleep>; }; -&msmgpio { +&tlmm { sdc2_pins_default: sdc2-pins-default { clk { pins = "sdc2_clk"; @@ -352,7 +352,7 @@ bus-width = <4>; - cd-gpios = <&msmgpio 38 0x1>; + cd-gpios = <&tlmm 38 0x1>; vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vreg_l13a_2p95>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi deleted file mode 100644 index ac1ede57936174..00000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ /dev/null @@ -1,653 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - - wcd9xxx_intr { - wcd_intr_default: wcd_intr_default{ - mux { - pins = "gpio54"; - function = "gpio"; - }; - - config { - pins = "gpio54"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* pull down */ - input-enable; - }; - }; - }; - - cdc_reset_ctrl { - cdc_reset_sleep: cdc_reset_sleep { - mux { - pins = "gpio64"; - function = "gpio"; - }; - config { - pins = "gpio64"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; - cdc_reset_active:cdc_reset_active { - mux { - pins = "gpio64"; - function = "gpio"; - }; - config { - pins = "gpio64"; - drive-strength = <16>; - bias-pull-down; - output-high; - }; - }; - }; - - blsp1_spi0_default: blsp1_spi0_default { - pinmux { - function = "blsp_spi1"; - pins = "gpio0", "gpio1", "gpio3"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio2"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio3"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio2"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp1_spi0_sleep: blsp1_spi0_sleep { - pinmux { - function = "gpio"; - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - blsp1_i2c2_default: blsp1_i2c2_default { - pinmux { - function = "blsp_i2c3"; - pins = "gpio47", "gpio48"; - }; - pinconf { - pins = "gpio47", "gpio48"; - drive-strength = <16>; - bias-disable = <0>; - }; - }; - - blsp1_i2c2_sleep: blsp1_i2c2_sleep { - pinmux { - function = "gpio"; - pins = "gpio47", "gpio48"; - }; - pinconf { - pins = "gpio47", "gpio48"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - blsp2_i2c0_default: blsp2_i2c0 { - pinmux { - function = "blsp_i2c7"; - pins = "gpio55", "gpio56"; - }; - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_i2c0_sleep: blsp2_i2c0_sleep { - pinmux { - function = "gpio"; - pins = "gpio55", "gpio56"; - }; - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_2pins_default: blsp2_uart1_2pins { - pinmux { - function = "blsp_uart8"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_4pins_default: blsp2_uart1_4pins { - pinmux { - function = "blsp_uart8"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_i2c1_default: blsp2_i2c1 { - pinmux { - function = "blsp_i2c8"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_i2c1_sleep: blsp2_i2c1_sleep { - pinmux { - function = "gpio"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_2pins_default: blsp2_uart2_2pins { - pinmux { - function = "blsp_uart9"; - pins = "gpio49", "gpio50"; - }; - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio49", "gpio50"; - }; - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_4pins_default: blsp2_uart2_4pins { - pinmux { - function = "blsp_uart9"; - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_spi5_default: blsp2_spi5_default { - pinmux { - function = "blsp_spi12"; - pins = "gpio85", "gpio86", "gpio88"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio87"; - }; - pinconf { - pins = "gpio85", "gpio86", "gpio88"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio87"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp2_spi5_sleep: blsp2_spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - }; - pinconf { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - pcie0_clkreq_default: pcie0_clkreq_default { - mux { - pins = "gpio36"; - function = "pci_e0"; - }; - - config { - pins = "gpio36"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_perst_default: pcie0_perst_default { - mux { - pins = "gpio35"; - function = "gpio"; - }; - - config { - pins = "gpio35"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie0_wake_default: pcie0_wake_default { - mux { - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_clkreq_sleep: pcie0_clkreq_sleep { - mux { - pins = "gpio36"; - function = "gpio"; - }; - - config { - pins = "gpio36"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie0_wake_sleep: pcie0_wake_sleep { - mux { - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie1_clkreq_default: pcie1_clkreq_default { - mux { - pins = "gpio131"; - function = "pci_e1"; - }; - - config { - pins = "gpio131"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_perst_default: pcie1_perst_default { - mux { - pins = "gpio130"; - function = "gpio"; - }; - - config { - pins = "gpio130"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_wake_default: pcie1_wake_default { - mux { - pins = "gpio132"; - function = "gpio"; - }; - - config { - pins = "gpio132"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_clkreq_sleep: pcie1_clkreq_sleep { - mux { - pins = "gpio131"; - function = "gpio"; - }; - - config { - pins = "gpio131"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie1_wake_sleep: pcie1_wake_sleep { - mux { - pins = "gpio132"; - function = "gpio"; - }; - - config { - pins = "gpio132"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_clkreq_default: pcie2_clkreq_default { - mux { - pins = "gpio115"; - function = "pci_e2"; - }; - - config { - pins = "gpio115"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie2_perst_default: pcie2_perst_default { - mux { - pins = "gpio114"; - function = "gpio"; - }; - - config { - pins = "gpio114"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_wake_default: pcie2_wake_default { - mux { - pins = "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio116"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_clkreq_sleep: pcie2_clkreq_sleep { - mux { - pins = "gpio115"; - function = "gpio"; - }; - - config { - pins = "gpio115"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_wake_sleep: pcie2_wake_sleep { - mux { - pins = "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - - cci0_default: cci0_default { - pinmux { - function = "cci_i2c"; - pins = "gpio17", "gpio18"; - }; - pinconf { - pins = "gpio17", "gpio18"; - drive-strength = <16>; - bias-disable; - }; - }; - - cci1_default: cci1_default { - pinmux { - function = "cci_i2c"; - pins = "gpio19", "gpio20"; - }; - pinconf { - pins = "gpio19", "gpio20"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_board_default: camera_board_default { - mux_pwdn { - function = "gpio"; - pins = "gpio98"; - }; - config_pwdn { - pins = "gpio98"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio104"; - }; - config_rst { - pins = "gpio104"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk1 { - function = "cam_mclk"; - pins = "gpio14"; - }; - config_mclk1 { - pins = "gpio14"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_front_default: camera_front_default { - mux_pwdn { - function = "gpio"; - pins = "gpio133"; - }; - config_pwdn { - pins = "gpio133"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio23"; - }; - config_rst { - pins = "gpio23"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk2 { - function = "cam_mclk"; - pins = "gpio15"; - }; - config_mclk2 { - pins = "gpio15"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera_rear_default { - mux_pwdn { - function = "gpio"; - pins = "gpio26"; - }; - config_pwdn { - pins = "gpio26"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio25"; - }; - config_rst { - pins = "gpio25"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk0 { - function = "cam_mclk"; - pins = "gpio13"; - }; - config_mclk0 { - pins = "gpio13"; - drive-strength = <16>; - bias-disable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 7e647843f7c79d..2f13d8e5d5212e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -694,15 +694,482 @@ }; }; - msmgpio: pinctrl@1010000 { + tlmm: pinctrl@1010000 { compatible = "qcom,msm8996-pinctrl"; reg = <0x01010000 0x300000>; interrupts = ; gpio-controller; - gpio-ranges = <&msmgpio 0 0 150>; + gpio-ranges = <&tlmm 0 0 150>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + blsp1_spi1_default: blsp1-spi1-default { + spi { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp1_spi1_sleep: blsp1-spi1-sleep { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_uart2_2pins_default: blsp2-uart1-2pins { + pins = "gpio4", "gpio5"; + function = "blsp_uart8"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_default: blsp2-i2c2 { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cci0_default: cci0-default { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + camera0_state_on: + camera_rear_default: camera-rear-default { + mclk0 { + pins = "gpio13"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + rst { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + pwdn { + pins = "gpio26"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci1_default: cci1-default { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + camera1_state_on: + camera_board_default: camera-board-default { + mclk1 { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + pwdn { + pins = "gpio98"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + rst { + pins = "gpio104"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera2_state_on: + camera_front_default: camera-front-default { + mclk2 { + pins = "gpio15"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + rst { + pins = "gpio23"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + pwdn { + pins = "gpio133"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + pcie0_state_on: pcie0-state-on { + perst { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio36"; + function = "pci_e0"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_state_off: pcie0-state-off { + perst { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio36"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_i2c3_default: blsp1-i2c2-default { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + drive-strength = <16>; + bias-disable = <0>; + }; + + blsp1_i2c3_sleep: blsp1-i2c2-sleep { + pins = "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-disable = <0>; + }; + + blsp2_uart3_4pins_default: blsp2-uart2-4pins { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_uart9"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_uart9"; + drive-strength = <2>; + bias-disable; + }; + + wcd_intr_default: wcd-intr-default{ + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + blsp2_i2c1_default: blsp2-i2c1 { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c0-sleep { + pins = "gpio55", "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c5_default: blsp2-i2c5 { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-disable; + }; + + /* Sleep state for BLSP2_I2C5 is missing.. */ + + cdc_reset_active: cdc-reset-active { + pins = "gpio64"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + + cdc_reset_sleep: cdc-reset-sleep { + pins = "gpio64"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + blsp2_spi6_default: blsp2-spi5-default { + spi { + pins = "gpio85", "gpio86", "gpio88"; + function = "blsp_spi12"; + drive-strength = <12>; + bias-disable; + }; + + cs { + pins = "gpio87"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp2_spi6_sleep: blsp2-spi5-sleep { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_i2c6_default: blsp2-i2c6 { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c6_sleep: blsp2-i2c6-sleep { + pins = "gpio87", "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_state_on: pcie1-state-on { + perst { + pins = "gpio130"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio131"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio132"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_state_off: pcie1-state-off { + /* Perst is missing? */ + clkreq { + pins = "gpio131"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake { + pins = "gpio132"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie2_state_on: pcie2-state-on { + perst { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio115"; + function = "pci_e2"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_state_off: pcie2-state-off { + /* Perst is missing? */ + clkreq { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc1_state_on: sdc1-state-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-state-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-clk-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_state_off: sdc2-clk-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; }; spmi_bus: qcom,spmi@400f000 { @@ -763,8 +1230,8 @@ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; - pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; + pinctrl-0 = <&pcie0_state_on>; + pinctrl-1 = <&pcie0_state_off>; linux,pci-domain = <0>; @@ -817,8 +1284,8 @@ <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; - pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; + pinctrl-0 = <&pcie1_state_on>; + pinctrl-1 = <&pcie1_state_off>; linux,pci-domain = <1>; @@ -868,8 +1335,8 @@ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; - pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; + pinctrl-0 = <&pcie2_state_on>; + pinctrl-1 = <&pcie2_state_off>; linux,pci-domain = <2>; clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, @@ -1877,8 +2344,8 @@ <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_spi0_default>; - pinctrl-1 = <&blsp1_spi0_sleep>; + pinctrl-0 = <&blsp1_spi1_default>; + pinctrl-1 = <&blsp1_spi1_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1892,8 +2359,8 @@ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c2_default>; - pinctrl-1 = <&blsp1_i2c2_sleep>; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1927,8 +2394,8 @@ <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c0_default>; - pinctrl-1 = <&blsp2_i2c0_sleep>; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1942,8 +2409,8 @@ <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c1_default>; - pinctrl-1 = <&blsp2_i2c1_sleep>; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1957,8 +2424,8 @@ <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_spi5_default>; - pinctrl-1 = <&blsp2_spi5_sleep>; + pinctrl-0 = <&blsp2_spi6_default>; + pinctrl-1 = <&blsp2_spi6_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -2033,13 +2500,13 @@ compatible = "slim217,1a0"; reg = <1 0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, <53 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "intr1", "intr2"; interrupt-controller; #interrupt-cells = <1>; - reset-gpios = <&msmgpio 64 0>; + reset-gpios = <&tlmm 64 0>; slim-ifc-dev = <&tasha_ifd>; @@ -2464,4 +2931,3 @@ ; }; }; -#include "msm8996-pins.dtsi" From ff5e2b87a1dfeb00c62c933ad4d5ddd16aac1da3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:20 +0100 Subject: [PATCH 174/511] arm64: dts: qcom: msm8996-*: Clean up QUP and UART names QUP and UART names start from 1. There are 6 QUPs and 2 UARTs per BLSP. Let's not further confuse programmers by stating otherwise. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 36 ++++++++++---------- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 4 +-- arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 16 ++++----- 4 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 4212f5c6e8b662..6b3b6a4c061322 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -41,14 +41,14 @@ / { aliases { - serial0 = &blsp2_uart1; - serial1 = &blsp2_uart2; - serial2 = &blsp1_uart1; - i2c0 = &blsp1_i2c2; + serial0 = &blsp2_uart2; + serial1 = &blsp2_uart3; + serial2 = &blsp1_uart2; + i2c0 = &blsp1_i2c3; i2c1 = &blsp2_i2c1; - i2c2 = &blsp2_i2c0; - spi0 = &blsp1_spi0; - spi1 = &blsp2_spi5; + i2c2 = &blsp2_i2c1; + spi0 = &blsp1_spi1; + spi1 = &blsp2_spi6; }; chosen { @@ -133,24 +133,24 @@ }; }; -&blsp1_i2c2 { +&blsp1_i2c3 { /* On Low speed expansion */ label = "LS-I2C0"; status = "okay"; }; -&blsp1_spi0 { +&blsp1_spi1 { /* On Low speed expansion */ label = "LS-SPI0"; status = "okay"; }; -&blsp1_uart1 { +&blsp1_uart2 { label = "BT-UART"; status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; bluetooth { compatible = "qcom,qca6174-bt"; @@ -166,7 +166,7 @@ status = "okay"; }; -&blsp2_i2c0 { +&blsp2_i2c1 { /* On High speed expansion */ label = "HS-I2C2"; status = "okay"; @@ -178,13 +178,13 @@ status = "okay"; }; -&blsp2_spi5 { +&blsp2_spi6 { /* On High speed expansion */ label = "HS-SPI1"; status = "okay"; }; -&blsp2_uart1 { +&blsp2_uart2 { label = "LS-UART1"; status = "okay"; pinctrl-names = "default", "sleep"; @@ -192,7 +192,7 @@ pinctrl-1 = <&blsp2_uart2_2pins_sleep>; }; -&blsp2_uart2 { +&blsp2_uart3 { label = "LS-UART0"; status = "disabled"; pinctrl-names = "default", "sleep"; @@ -428,7 +428,7 @@ }; }; - blsp1_uart1_default: blsp1_uart1_default { + blsp1_uart2_default: blsp1_uart2_default { mux { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "blsp_uart2"; @@ -441,7 +441,7 @@ }; }; - blsp1_uart1_sleep: blsp1_uart1_sleep { + blsp1_uart2_sleep: blsp1_uart2_sleep { mux { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index 9b55eae39e3eb3..4f67aa48633ba4 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -17,7 +17,7 @@ qcom,board-id = <0x00010018 0>; aliases { - serial0 = &blsp2_uart1; + serial0 = &blsp2_uart2; }; chosen { @@ -81,7 +81,7 @@ }; }; -&blsp2_uart1 { +&blsp2_uart2 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_uart2_2pins_default>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi index 5f46a1427f1f0e..1e1514e9158cca 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi @@ -7,7 +7,7 @@ / { aliases { - serial0 = &blsp2_uart1; + serial0 = &blsp2_uart2; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 2f13d8e5d5212e..0e564f88d17915 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2326,7 +2326,7 @@ bus-width = <4>; }; - blsp1_uart1: serial@7570000 { + blsp1_uart2: serial@7570000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x07570000 0x1000>; interrupts = ; @@ -2336,7 +2336,7 @@ status = "disabled"; }; - blsp1_spi0: spi@7575000 { + blsp1_spi1: spi@7575000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x07575000 0x600>; interrupts = ; @@ -2351,7 +2351,7 @@ status = "disabled"; }; - blsp1_i2c2: i2c@7577000 { + blsp1_i2c3: i2c@7577000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07577000 0x1000>; interrupts = ; @@ -2366,7 +2366,7 @@ status = "disabled"; }; - blsp2_uart1: serial@75b0000 { + blsp2_uart2: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x075b0000 0x1000>; interrupts = ; @@ -2376,7 +2376,7 @@ status = "disabled"; }; - blsp2_uart2: serial@75b1000 { + blsp2_uart3: serial@75b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x075b1000 0x1000>; interrupts = ; @@ -2386,7 +2386,7 @@ status = "disabled"; }; - blsp2_i2c0: i2c@75b5000 { + blsp2_i2c1: i2c@75b5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b5000 0x1000>; interrupts = ; @@ -2401,7 +2401,7 @@ status = "disabled"; }; - blsp2_i2c1: i2c@75b6000 { + blsp2_i2c2: i2c@75b6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b6000 0x1000>; interrupts = ; @@ -2416,7 +2416,7 @@ status = "disabled"; }; - blsp2_spi5: spi@75ba000{ + blsp2_spi6: spi@75ba000{ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x075ba000 0x600>; interrupts = ; From 76f4d70f617470297a0cd2d97b91c7326314273e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:21 +0100 Subject: [PATCH 175/511] arm64: dts: qcom: msm8996: Enlarge tcsr_mutex_regs size Set the tcsr_mutex_regs size to 0x40000 to allow for accessing all required registers that will be needed to support modem. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0e564f88d17915..455ee21458e583 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -473,7 +473,7 @@ tcsr_mutex_regs: syscon@740000 { compatible = "syscon"; - reg = <0x00740000 0x20000>; + reg = <0x00740000 0x40000>; }; tcsr: syscon@7a0000 { From fbb8a3a8b7317233e577fa42a6efb4e38e6bbc4d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:22 +0100 Subject: [PATCH 176/511] arm64: dts: qcom: msm8996: Add SDHCI1 Add SDHCI1 device to allow for usage of (more often than not) eMMC. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 455ee21458e583..f59e18e7860e91 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2309,6 +2309,29 @@ status = "disabled"; }; + sdhc1: sdhci@7464900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07464900 0x11c>, <0x07464000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + + bus-width = <8>; + non-removable; + status = "disabled"; + }; + sdhc2: sdhci@74a4900 { status = "disabled"; compatible = "qcom,sdhci-msm-v4"; From c33d9068a7509f5bab6b5d97d5519b629b1944c6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:23 +0100 Subject: [PATCH 177/511] arm64: dts: qcom: msm8996: Add BLSP2_I2C5 and BLSP2_I2C6 Add the fifth and sixth I2C host on the second BLSP, used for various board-specific peripherals. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f59e18e7860e91..17e7e9bd9e7076 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2439,6 +2439,35 @@ status = "disabled"; }; + blsp2_i2c5: i2c@75b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x75b9000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_i2c5_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c6: i2c@75ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x75ba000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c6_default>; + pinctrl-1 = <&blsp2_i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_spi6: spi@75ba000{ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x075ba000 0x600>; From 37b05cecfe96d6471ce51b224f35b573c2b79ddc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:24 +0100 Subject: [PATCH 178/511] arm64: dts: qcom: msm8996: Disable MDSS and Adreno by default Disable them by default to allow for booting without a display and proprietary firmware. Then, enable them on boards that didn't previously disable them. Hence, this commit brings no functional difference. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 ++++++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 6b3b6a4c061322..d4004fa8194bec 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -204,6 +204,10 @@ vdda-supply = <&vreg_l2a_1p25>; }; +&gpu { + status = "okay"; +}; + &hdmi { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index 4f67aa48633ba4..c6d7c6250de431 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -88,6 +88,14 @@ pinctrl-1 = <&blsp2_uart2_2pins_sleep>; }; +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + &tlmm { sdc2_pins_default: sdc2-pins-default { clk { diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 17e7e9bd9e7076..8efb1d192821be 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -522,6 +522,8 @@ #size-cells = <1>; ranges; + status = "disabled"; + mdp: mdp@901000 { compatible = "qcom,mdp5"; reg = <0x00901000 0x90000>; @@ -619,7 +621,8 @@ "ref"; }; }; - gpu@b00000 { + + gpu: gpu@b00000 { compatible = "qcom,adreno-530.2", "qcom,adreno"; #stream-id-cells = <16>; @@ -651,6 +654,8 @@ operating-points-v2 = <&gpu_opp_table>; + status = "disabled"; + gpu_opp_table: opp-table { compatible ="operating-points-v2"; From d774e762b032588a3adb38f8bc949b59e22a7749 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:25 +0100 Subject: [PATCH 179/511] arm64: dts: qcom: msm8996: Disable Venus by default Disable Venus by default to allow booting without closed firmware and enable it on the boards that didn't previously disable it. This commit brings no functional difference. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-7-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 4 ++++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index d4004fa8194bec..0a15589eb1d57c 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -1097,6 +1097,10 @@ }; +&venus { + status = "okay"; +}; + &wcd9335 { clock-names = "mclk", "slimbus"; clocks = <&div1_mclk>, diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index c6d7c6250de431..8c7a27e972b7f8 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -391,3 +391,7 @@ vdda-phy-max-microamp = <18380>; vdda-pll-max-microamp = <9440>; }; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8efb1d192821be..6ee54536519a8f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1625,7 +1625,7 @@ power-domains = <&mmcc GPU_GDSC>; }; - video-codec@c00000 { + venus: video-codec@c00000 { compatible = "qcom,msm8996-venus"; reg = <0x00c00000 0xff000>; interrupts = ; @@ -1656,7 +1656,7 @@ <&venus_smmu 0x2d>, <&venus_smmu 0x31>; memory-region = <&venus_region>; - status = "okay"; + status = "disabled"; video-decoder { compatible = "venus-decoder"; From f7342c7d2902b70ef060d84addf5ce3b57182516 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:26 +0100 Subject: [PATCH 180/511] arm64: dts: qcom: pm8994: Add RESIN node Add a RESIN node to support RESIN-connected buttons on some devices. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-8-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 19 +++++-------------- arch/arm64/boot/dts/qcom/pm8994.dtsi | 8 +++++++- 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 0a15589eb1d57c..51e17094d7b18e 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -253,6 +253,11 @@ vdd-gfx-supply = <&vdd_gfx>; }; +&pm8994_resin { + status = "okay"; + linux,code = ; +}; + &tlmm { gpio-line-names = "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ @@ -1034,20 +1039,6 @@ }; }; -&spmi_bus { - pmic@0 { - pon@800 { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; - &ufsphy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index c3876c82c87411..ad19016df04777 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -45,7 +45,6 @@ pm8994_pon: pon@800 { compatible = "qcom,pm8916-pon"; - reg = <0x800>; mode-bootloader = <0x2>; mode-recovery = <0x1>; @@ -58,6 +57,13 @@ linux,code = ; }; + pm8994_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; }; pm8994_temp: temp-alarm@2400 { From 12d5403757363880fa8c8d408932ecbe98efeeeb Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:27 +0100 Subject: [PATCH 181/511] arm64: dts: qcom: msm8996: Add DSI0 nodes Add required nodes to support DSI displays connected to the primary interface. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-9-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 78 +++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6ee54536519a8f..768fdfa510190b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -545,6 +545,11 @@ iommus = <&mdp_smmu 0>; + assigned-clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -555,9 +560,82 @@ remote-endpoint = <&hdmi_in>; }; }; + + port@1 { + reg = <1>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; }; }; + dsi0: dsi@994000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x00994000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "byte", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@994400 { + compatible = "qcom,dsi-phy-14nm"; + reg = <0x00994400 0x100>, + <0x00994500 0x300>, + <0x00994800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + status = "disabled"; + }; + hdmi: hdmi-tx@9a0000 { compatible = "qcom,hdmi-tx-8996"; reg = <0x009a0000 0x50c>, From 37aa540cbd30ced7217745378c37259ec460e657 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:28 +0100 Subject: [PATCH 182/511] arm64: dts: qcom: pmi8994: Add WLED node Add and configure WLED node to enable backlight control on WLED-enabled devices. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-10-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8994.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index e5ed28ab9b2de8..b4ac900ab115f7 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -32,5 +32,18 @@ #address-cells = <1>; #size-cells = <1>; }; + + pmi8994_wled: wled@d800 { + compatible = "qcom,pmi8994-wled"; + reg = <0xd800 0xd900>; + interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "short"; + qcom,num-strings = <3>; + /* Yes, all four strings *have to* be defined or things won't work. */ + qcom,enabled-strings = <0 1 2 3>; + qcom,cabc; + qcom,eternal-pfet; + status = "disabled"; + }; }; }; From 3343de9af75cef3f45aa27970bd1680d424da05e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 28 Feb 2021 14:08:29 +0100 Subject: [PATCH 183/511] arm64: dts: qcom: msm8996: Clean up the SDHCI2 node Fix the indentation, add pinctrl and move status="disabled" down. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210228130831.203765-11-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 33 +++++++++++++++------------ 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 768fdfa510190b..94f0a2ba120f6f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2416,20 +2416,25 @@ }; sdhc2: sdhci@74a4900 { - status = "disabled"; - compatible = "qcom,sdhci-msm-v4"; - reg = <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, - <0 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface", "core", "xo"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; - bus-width = <4>; + compatible = "qcom,sdhci-msm-v4"; + reg = <0x074a4900 0x314>, <0x074a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + + bus-width = <4>; + status = "disabled"; }; blsp1_uart2: serial@7570000 { From 4753492de9df1b1728b27e36b17c1c09ef1685b1 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Tue, 2 Mar 2021 03:51:10 +0000 Subject: [PATCH 184/511] arm64: dts: qcom: msm8996: Add usb3 interrupts Add hs_phy_irq and ss_phy_irq to usb3. Tested-by: Konrad Dybcio Signed-off-by: Yassine Oudjana Link: https://lore.kernel.org/r/dvfyYKA9vnJdunbQ1CL-dgjXtv_1wYpRnezdc3PHoCyrgmfi5KP0Dn4MtaumQEpHIQAHL9tTdqcaCK7YJWyrdWXCrPeGd4uMh-nFeu7xQYw=@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 94f0a2ba120f6f..076150c420a722 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2309,6 +2309,10 @@ #size-cells = <1>; ranges; + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_AGGRE2_USB3_AXI_CLK>, From 132f5a8df93430718412e1a1d1fe2f242824af9d Mon Sep 17 00:00:00 2001 From: Rajeshwari Ravindra Kamble Date: Fri, 7 May 2021 11:37:20 +0530 Subject: [PATCH 185/511] arm64: dts: qcom: SC7280: Add device node support for TSENS Adding device node for TSENS controller and critical interrupt support in SC7280. Signed-off-by: Rajeshwari Ravindra Kamble Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1620367641-23383-3-git-send-email-rkambl@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 2cc478553935ca..275113c9242f41 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -825,6 +825,28 @@ interrupt-controller; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <15>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <12>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sc7280-aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; From 9ec1c5867c0269777e4b4bf0d2ef926ac6eac882 Mon Sep 17 00:00:00 2001 From: Rajeshwari Ravindra Kamble Date: Fri, 7 May 2021 11:37:21 +0530 Subject: [PATCH 186/511] arm64: dts: qcom: SC7280: Add thermal zone support Adding thermal zone and cooling maps support in SC7280. Reviewed-by: Matthias Kaehlcke Signed-off-by: Rajeshwari Ravindra Kamble Link: https://lore.kernel.org/r/1620367641-23383-4-git-send-email-rkambl@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 852 +++++++++++++++++++++++++++ 1 file changed, 852 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 275113c9242f41..326f629b4789fc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -70,6 +71,7 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -88,6 +90,7 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; + #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -103,6 +106,7 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; + #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -118,6 +122,7 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; + #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -133,6 +138,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; + #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -148,6 +154,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; + #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -163,6 +170,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; + #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -178,6 +186,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; + #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -1140,6 +1149,849 @@ }; }; + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu8-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu8_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu8_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu8_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu8_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu8_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu9-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu9_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu9_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu9_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu9_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu9_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu10-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 13>; + + trips { + cpu10_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu10_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu10_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu10_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu10_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu11-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 14>; + + trips { + cpu11_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu11_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu11_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu11_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu11_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0_crit: aoss0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss1_crit: aoss1-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cpuss0_crit: cluster0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cpuss1_crit: cluster0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 1>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss0_crit: gpuss0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 2>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss1_crit: gpuss1-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nspss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 3>; + + trips { + nspss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nspss0_crit: nspss0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nspss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 4>; + + trips { + nspss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nspss1_crit: nspss1-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 5>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 6>; + + trips { + ddr_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + ddr_crit: ddr-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 7>; + + trips { + mdmss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdmss0_crit: mdmss0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 8>; + + trips { + mdmss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdmss1_crit: mdmss1-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 9>; + + trips { + mdmss2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdmss2_crit: mdmss2-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 10>; + + trips { + mdmss3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdmss3_crit: mdmss3-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 11>; + + trips { + camera0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0_crit: camera0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From 4dcaa68ee2176344f30dd7e898938c9d46cb6636 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:40:56 +0530 Subject: [PATCH 187/511] arm64: dts: qcom: sm8350: Add label for thermal-zones node Add label "thermal_zones" for thermal-zones node. Signed-off-by: satya priya Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1621937466-1502-2-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 2fc23f3d2c75c6..55f44ea454021d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1368,7 +1368,7 @@ }; }; - thermal-zones { + thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; From 0e17fe8cf8e112599c9812904f9eecdc3e8cde14 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:40:57 +0530 Subject: [PATCH 188/511] arm64: dts: qcom: pm7325: Add pm7325 base dts file Add base DTS file for pm7325 along with GPIOs and temp-alarm nodes. Signed-off-by: satya priya Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1621937466-1502-3-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7325.dtsi | 53 ++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm7325.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi b/arch/arm64/boot/dts/qcom/pm7325.dtsi new file mode 100644 index 00000000000000..e7f64a9ddc9cba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2021, The Linux Foundation. All rights reserved. + +#include +#include + +&spmi_bus { + pm7325: pmic@1 { + compatible = "qcom,pm7325", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7325_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7325_gpios: gpios@8800 { + compatible = "qcom,pm7325-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7325_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm7325_thermal: pm7325-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm7325_temp_alarm>; + + trips { + pm7325_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm7325_crit: pm7325-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; From 3795fe7d497b897a0d897e23f735e51866440477 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:40:58 +0530 Subject: [PATCH 189/511] arm64: dts: qcom: pm8350c: Add temp-alarm support Add temp-alarm support for PM8350C pmic. Signed-off-by: satya priya Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1621937466-1502-4-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index 2b9b75ecec600c..f926508957023b 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -13,6 +13,13 @@ #address-cells = <1>; #size-cells = <0>; + pm8350c_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm8350c_gpios: gpio@8800 { compatible = "qcom,pm8350c-gpio"; reg = <0x8800>; @@ -23,3 +30,25 @@ }; }; }; + +&thermal_zones { + pm8350c_thermal: pm8350c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350c_temp_alarm>; + + trips { + pm8350c_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350c_crit: pm8350c-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; From 6327abef804dbfc4ccb2c9e0991afc601de24997 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:40:59 +0530 Subject: [PATCH 190/511] arm64: dts: qcom: pm8350c: Correct the GPIO node Add gpio ranges and correct the compatible to add "qcom,spmi-gpio" as this pmic is on spmi bus. Reviewed-by: Matthias Kaehlcke Signed-off-by: satya priya Link: https://lore.kernel.org/r/1621937466-1502-5-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index f926508957023b..e1b75ae0a8233b 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -21,9 +21,10 @@ }; pm8350c_gpios: gpio@8800 { - compatible = "qcom,pm8350c-gpio"; + compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pm8350c_gpios 0 0 9>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From 7a3544e5d4e868ae918e1fb59cd1b0083ed12f59 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:41:00 +0530 Subject: [PATCH 191/511] arm64: dts: qcom: pmr735a: Add temp-alarm support Add temp-alarm support for PMR735A pmic. Signed-off-by: satya priya Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1621937466-1502-6-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmr735a.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmr735a.dtsi b/arch/arm64/boot/dts/qcom/pmr735a.dtsi index 1c675af13cbfca..b0a7cd6c067679 100644 --- a/arch/arm64/boot/dts/qcom/pmr735a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735a.dtsi @@ -13,6 +13,13 @@ #address-cells = <1>; #size-cells = <0>; + pmr735a_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmr735a_gpios: gpio@8800 { compatible = "qcom,pmr735a-gpio"; reg = <0x8800>; @@ -23,3 +30,25 @@ }; }; }; + +&thermal_zones { + pmr735a_thermal: pmr735a-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmr735a_temp_alarm>; + + trips { + pmr735a_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735a_crit: pmr735a-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; From f878e1baa4ae8211982022bde8f2ad06acbd234d Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:41:01 +0530 Subject: [PATCH 192/511] arm64: dts: qcom: pmr735a: Correct the GPIO node Add gpio ranges and correct the compatible to add "qcom,spmi-gpio" as this pmic is on spmi bus. Reviewed-by: Matthias Kaehlcke Signed-off-by: satya priya Link: https://lore.kernel.org/r/1621937466-1502-7-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmr735a.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmr735a.dtsi b/arch/arm64/boot/dts/qcom/pmr735a.dtsi index b0a7cd6c067679..b4b6ba24f8453c 100644 --- a/arch/arm64/boot/dts/qcom/pmr735a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735a.dtsi @@ -21,9 +21,10 @@ }; pmr735a_gpios: gpio@8800 { - compatible = "qcom,pmr735a-gpio"; + compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pmr735a_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From b2de4313605834cb9d50baa3901b2c1956092ca1 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:41:02 +0530 Subject: [PATCH 193/511] arm64: dts: qcom: pmk8350: Add peripherals for pmk8350 Add PON, RTC, VADC and ACD_TM support for PMK8350. Signed-off-by: satya priya Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1621937466-1502-8-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 48 +++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index 1530b8ff270f7a..ecd5ccd9549259 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2021, Linaro Limited */ +#include +#include #include #include @@ -13,6 +15,52 @@ #address-cells = <1>; #size-cells = <0>; + pmk8350_pon: pon@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; + + pmk8350_vadc: adc@3100 { + compatible = "qcom,spmi-adc7"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + }; + + pmk8350_adc_tm: adc-tm@3400 { + compatible = "qcom,adc-tm7"; + reg = <0x3400>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "threshold"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pmk8350_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + pmk8350_gpios: gpio@b000 { compatible = "qcom,pmk8350-gpio"; reg = <0xb000>; From d0927c2134d9eb75aa8937a8c9e191b13a8f0d56 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:41:03 +0530 Subject: [PATCH 194/511] arm64: dts: qcom: pmk8350: Correct the GPIO node Add gpio ranges and correct the compatible to add "qcom,spmi-gpio" as this pmic is on spmi bus. Reviewed-by: Matthias Kaehlcke Signed-off-by: satya priya Link: https://lore.kernel.org/r/1621937466-1502-9-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index ecd5ccd9549259..04fc2632a0b20c 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -62,9 +62,10 @@ }; pmk8350_gpios: gpio@b000 { - compatible = "qcom,pmk8350-gpio"; + compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio"; reg = <0xb000>; gpio-controller; + gpio-ranges = <&pmk8350_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From a1cbfdfdc2b1ca6cdc9f3b57d1776cae6783dd2f Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:41:04 +0530 Subject: [PATCH 195/511] arm64: dts: qcom: sc7280: Include PMIC DT files for sc7280-idp The sc7280-idp has four PMICs, include their .dtsi files. Reviewed-by: Matthias Kaehlcke Signed-off-by: satya priya Link: https://lore.kernel.org/r/1621937466-1502-10-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 54d2cb365b71a0..f2955808083fb4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -8,6 +8,10 @@ /dts-v1/; #include "sc7280.dtsi" +#include "pm7325.dtsi" +#include "pmr735a.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 IDP platform"; From fbd5a1d22607f77ea6fb31fbfdb91c08007ed3a1 Mon Sep 17 00:00:00 2001 From: satya priya Date: Tue, 25 May 2021 15:41:05 +0530 Subject: [PATCH 196/511] arm64: dts: qcom: sc7280: Add ADC channel nodes for PMIC temperatures to sc7280-idp Add channel nodes for the on die temperatures of PMICS pmk8350, pm8350, pmr735a and pmr735b. Signed-off-by: satya priya Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1621937466-1502-11-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index f2955808083fb4..704fb9a88a61b5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -7,6 +7,10 @@ /dts-v1/; +#include +#include +#include +#include #include "sc7280.dtsi" #include "pm7325.dtsi" #include "pmr735a.dtsi" @@ -238,6 +242,32 @@ }; }; +&pmk8350_vadc { + pm8350_die_temp { + reg = ; + label = "pm8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_die_temp { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmr735a_die_temp { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmr735b_die_temp { + reg = ; + label = "pmr735b_die_temp"; + qcom,pre-scaling = <1 1>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From fbe7be5b23ae6640d14a94d5fb71dddfce324976 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 25 May 2021 22:02:41 +0200 Subject: [PATCH 197/511] arm64: dts: qcom: msm8996: Strictly limit USB2 host to USB2 speeds As the name implies, the USB2 controller should only operate at USB2 speeds. Make sure it does just that by pinning it to USB High-Speed (USB2) mode. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210525200246.118323-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 076150c420a722..5a993c6b519eb4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2593,6 +2593,7 @@ assigned-clock-rates = <19200000>, <60000000>; power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; status = "disabled"; dwc3@7600000 { @@ -2601,6 +2602,7 @@ interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; phys = <&hsusb_phy2>; phy-names = "usb2-phy"; + maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; }; From a4bdd15e799ad335ecf0878d4cd7ea983f484843 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 25 May 2021 22:02:43 +0200 Subject: [PATCH 198/511] arm64: dts: qcom: msm8996: Add DMA to QUPs and UARTs Add BAM DMA nodes and add required properties to devices to enable DMA operations. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210525200246.118323-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 5a993c6b519eb4..859fe18aa8c7b0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2441,6 +2441,17 @@ status = "disabled"; }; + blsp1_dma: dma@7544000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07544000 0x2b000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + qcom,ee = <0>; + }; + blsp1_uart2: serial@7570000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x07570000 0x1000>; @@ -2448,6 +2459,8 @@ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -2461,6 +2474,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_spi1_default>; pinctrl-1 = <&blsp1_spi1_sleep>; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -2476,11 +2491,24 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_i2c3_default>; pinctrl-1 = <&blsp1_i2c3_sleep>; + dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + blsp2_dma: dma@7584000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07584000 0x2b000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + qcom,ee = <0>; + }; + blsp2_uart2: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x075b0000 0x1000>; @@ -2511,6 +2539,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c1_default>; pinctrl-1 = <&blsp2_i2c1_sleep>; + dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -2526,6 +2556,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c2_default>; pinctrl-1 = <&blsp2_i2c2_sleep>; + dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -2540,6 +2572,8 @@ clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_i2c5_default>; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -2555,6 +2589,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c6_default>; pinctrl-1 = <&blsp2_i2c6_sleep>; + dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -2570,6 +2606,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_spi6_default>; pinctrl-1 = <&blsp2_spi6_sleep>; + dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From fb97f63106f3174992a22fe5e42dda96a0810750 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Tue, 25 May 2021 20:58:54 +0300 Subject: [PATCH 199/511] ARM: dts: am335x: align GPIO hog names with dt-schema The GPIO Hog dt-schema node naming convention expect GPIO hogs node names to end with a 'hog' suffix. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblack-wireless.dts | 2 +- arch/arm/boot/dts/am335x-boneblue.dts | 2 +- arch/arm/boot/dts/am335x-bonegreen-wireless.dts | 4 ++-- arch/arm/boot/dts/am335x-icev2.dts | 4 ++-- arch/arm/boot/dts/am335x-shc.dts | 8 ++++---- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index 86cad991290610..80116646a3fe0a 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -101,7 +101,7 @@ }; &gpio3 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 69acaf4ea0f355..0afcc2ee0b636f 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -436,7 +436,7 @@ }; &gpio3 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index 7615327d906a48..74db0fc39397f8 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -101,7 +101,7 @@ }; &gpio1 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; output-high; @@ -118,7 +118,7 @@ /* an external pulldown on U21 pin 4. */ &gpio3 { - bt_aud_in { + bt-aud-in-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index e923d065304d9f..5e598ac96dcc7f 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -458,14 +458,14 @@ }; &gpio3 { - p4 { + pr1-mii-ctl-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_HIGH>; output-high; line-name = "PR1_MII_CTRL"; }; - p10 { + mux-mii-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 1eaa265334667b..2bfe60d3278394 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -140,14 +140,14 @@ }; &gpio1 { - hmtc_rst { + hmtc-rst-hog { gpio-hog; gpios = <24 GPIO_ACTIVE_LOW>; output-high; line-name = "homematic_reset"; }; - hmtc_prog { + hmtc-prog-hog { gpio-hog; gpios = <27 GPIO_ACTIVE_LOW>; output-high; @@ -156,14 +156,14 @@ }; &gpio3 { - zgb_rst { + zgb-rst-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_LOW>; output-low; line-name = "zigbee_reset"; }; - zgb_boot { + zgb-boot-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_HIGH>; output-high; From bd551acdde3ad40da1a97391abd6e0db7852bf66 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Tue, 25 May 2021 20:58:55 +0300 Subject: [PATCH 200/511] ARM: dts: am437x: align gpio hog names with dt-schema The GPIO Hog dt-schema node naming convention expect GPIO hogs node names to end with a 'hog' suffix. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++-- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 6e4d05d649e98a..45cbc7fb557a74 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -786,7 +786,7 @@ pinctrl-0 = <&gpio0_pins>; status = "okay"; - p23 { + sel-emmc-nand-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; /* SelEMMCorNAND selects between eMMC and NAND: @@ -819,7 +819,7 @@ status = "okay"; ti,no-reset-on-init; - p8 { + sel-lcd-hdmi-hog { /* * SelLCDorHDMI selects between display and audio paths: * Low: HDMI display with audio via HDMI diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index f517d1e843cf4c..d717d5ada81294 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -725,7 +725,7 @@ pinctrl-0 = <&display_mux_pins>; status = "okay"; - p1 { + sel-lcd-hdmi-hog { /* * SelLCDorHDMI selects between display and audio paths: * Low: HDMI display with audio via HDMI From cfb4ab3b5df86c6001127346d8331f5e87012f91 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Tue, 25 May 2021 20:58:56 +0300 Subject: [PATCH 201/511] ARM: dts: omap3: align gpio hog names with dt-schema The GPIO Hog dt-schema node naming convention expect GPIO hogs node names to end with a 'hog' suffix. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-evm-processor-common.dtsi | 2 +- arch/arm/boot/dts/omap3-gta04a5.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi index b4109f48ec1850..e6ba30a2116638 100644 --- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi @@ -195,7 +195,7 @@ * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. */ &gpio2 { - en_usb2_port { + en-usb2-port-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ output-low; diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts index fd84bbf3b9cc3b..9ce8d81250aa0d 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -37,7 +37,7 @@ }; &gpio5 { - irda_en { + irda-en-hog { gpio-hog; gpios = <(175-160) GPIO_ACTIVE_HIGH>; output-high; /* activate gpio_175 to disable IrDA receiver */ From 4823117cb80eedf31ddbc126b9bd92e707bd9a26 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Tue, 25 May 2021 20:58:57 +0300 Subject: [PATCH 202/511] ARM: dts: omap5-board-common: align gpio hog names with dt-schema The GPIO Hog dt-schema node naming convention expect GPIO hogs node names to end with a 'hog' suffix. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-board-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index d8f13626cfd1b5..45435bb88c8905 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -149,7 +149,7 @@ &gpio8 { /* TI trees use GPIO instead of msecure, see also muxing */ - p234 { + msecure-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; From 0c149400c2f676e7b4cc68e517db29005a7a38c7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 May 2021 09:54:06 +0200 Subject: [PATCH 203/511] ARM: dts: dra7x-evm: Align GPIO hog names with dt-schema The dt-schema for nxp,pcf8575 expects GPIO hogs node names to end with a 'hog' suffix. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra71-evm.dts | 2 +- arch/arm/boot/dts/dra72-evm-common.dtsi | 2 +- arch/arm/boot/dts/dra76-evm.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 38530dbb89a00b..3dcb6e1f49bcf1 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -366,7 +366,7 @@ reg = <0x26>; gpio-controller; #gpio-cells = <2>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 6d2cca6b44883e..a6436444303152 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -187,7 +187,7 @@ }; &pcf_hdmi { - p0 { + hdmi-i2c-disable-hog { /* * PM_OEn to High: Disable routing I2C3 to PM_I2C * With this PM_SEL(p3) should not matter diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index b65b2dd094d0ff..f2384277d5dcdc 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -268,7 +268,7 @@ */ lines-initial-states = <0x0f2b>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 4508f7ffde0dc6..fbe4030650b7cc 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -375,7 +375,7 @@ reg = <0x26>; gpio-controller; #gpio-cells = <2>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; From b644c5e01c870056e13a096e14b9a92075c8f682 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Sat, 22 May 2021 01:24:09 +0300 Subject: [PATCH 204/511] ARM: dts: am57xx-cl-som-am57x: fix ti,no-reset-on-init flag for gpios The ti,no-reset-on-init flag need to be at the interconnect target module level for the modules that have it defined. The ti-sysc driver handles this case, but produces warning, not a critical issue. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 5 ++--- arch/arm/boot/dts/dra7-l4.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 0d5fe2bfb683af..39eba2bc36ddf8 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -610,12 +610,11 @@ >; }; -&gpio3 { - status = "okay"; +&gpio3_target { ti,no-reset-on-init; }; -&gpio2 { +&gpio2_target { status = "okay"; ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 149144cdff35a9..6e33c0bf32a95e 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1343,7 +1343,7 @@ }; }; - target-module@55000 { /* 0x48055000, ap 13 0e.0 */ + gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x55000 0x4>, <0x55010 0x4>, @@ -1376,7 +1376,7 @@ }; }; - target-module@57000 { /* 0x48057000, ap 15 06.0 */ + gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x57000 0x4>, <0x57010 0x4>, From 2566d5b8c1670f7d7a44cc1426d254147ec5c421 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Sat, 22 May 2021 01:24:10 +0300 Subject: [PATCH 205/511] ARM: dts: am437x-gp-evm: fix ti,no-reset-on-init flag for gpios The ti,no-reset-on-init flag need to be at the interconnect target module level for the modules that have it defined. The ti-sysc driver handles this case, but produces warning, not a critical issue. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 5 ++++- arch/arm/boot/dts/am437x-l4.dtsi | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 45cbc7fb557a74..e2677682b540c0 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -813,11 +813,14 @@ status = "okay"; }; +&gpio5_target { + ti,no-reset-on-init; +}; + &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&display_mux_pins>; status = "okay"; - ti,no-reset-on-init; sel-lcd-hdmi-hog { /* diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index e217ffc0977056..a6f19ae7d3e6b3 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2070,7 +2070,7 @@ }; }; - target-module@22000 { /* 0x48322000, ap 116 64.0 */ + gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x22000 0x4>, <0x22010 0x4>, From d7d30b8fcd111e9feb171023c0e0c8d855582dcb Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Sat, 22 May 2021 01:24:11 +0300 Subject: [PATCH 206/511] ARM: dts: am335x: fix ti,no-reset-on-init flag for gpios The ti,no-reset-on-init flag need to be at the interconnect target module level for the modules that have it defined. The ti-sysc driver handles this case, but produces warning, not a critical issue. Signed-off-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 4 ++-- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi | 2 +- arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi | 2 +- arch/arm/boot/dts/am33xx-l4.dtsi | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 3ea28618038259..1103a2cb836fb0 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -393,10 +393,10 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; -&gpio3 { +&gpio3_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index d5f8d5e2eb5d28..45bf0273ecd856 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -646,7 +646,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 4e90f9c23d2e57..8121a199607cc7 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -150,7 +150,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi index 98d8ed4ad9677d..39e5d2ce600a10 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -353,7 +353,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 039a9ab4c7eaaa..dcce5e3e001eba 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1789,7 +1789,7 @@ }; }; - target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ + gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0xae000 0x4>, <0xae010 0x4>, From 7260620cd9e31514671ed8770769721c4d39fa19 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 26 May 2021 17:29:55 +0530 Subject: [PATCH 207/511] ARM: dts: dra7-l4: Drop ti,omap4-uart entry from UART nodes ti,omap4-uart was kept around to work with legacy omap-serial driver. Now that we have completed move to 8250-omap.c drop legacy compatible. This will simplify writing YAML schema. Signed-off-by: Vignesh Raghavendra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 6e33c0bf32a95e..4b336b831da25f 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1159,7 +1159,7 @@ ranges = <0x0 0x20000 0x1000>; uart3: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; @@ -1562,7 +1562,7 @@ ranges = <0x0 0x66000 0x1000>; uart5: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; @@ -1594,7 +1594,7 @@ ranges = <0x0 0x68000 0x1000>; uart6: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; @@ -1626,7 +1626,7 @@ ranges = <0x0 0x6a000 0x1000>; uart1: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1658,7 +1658,7 @@ ranges = <0x0 0x6c000 0x1000>; uart2: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; @@ -1690,7 +1690,7 @@ ranges = <0x0 0x6e000 0x1000>; uart4: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; @@ -2424,7 +2424,7 @@ ranges = <0x0 0x20000 0x1000>; uart7: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; @@ -2454,7 +2454,7 @@ ranges = <0x0 0x22000 0x1000>; uart8: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; @@ -2484,7 +2484,7 @@ ranges = <0x0 0x24000 0x1000>; uart9: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; @@ -4530,7 +4530,7 @@ ranges = <0x0 0xb000 0x1000>; uart10: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; From 40a95e2915e3f08145c82507a0df046793810adb Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 26 May 2021 17:29:56 +0530 Subject: [PATCH 208/511] ARM: dts: am437x-l4: Drop ti,omap2-uart entry from UART nodes ti,omap2-uart was kept around to work with legacy omap-serial driver. Now that we have completed move to 8250-omap.c drop legacy compatible. This will simplify writing YAML schema. Signed-off-by: Vignesh Raghavendra Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index a6f19ae7d3e6b3..d681f51005780d 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -194,7 +194,7 @@ ranges = <0x0 0x9000 0x1000>; uart0: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = ; }; @@ -712,7 +712,7 @@ ranges = <0x0 0x22000 0x1000>; uart1: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; @@ -740,7 +740,7 @@ ranges = <0x0 0x24000 0x1000>; uart2: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; @@ -1399,7 +1399,7 @@ ranges = <0x0 0xa6000 0x1000>; uart3: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; @@ -1427,7 +1427,7 @@ ranges = <0x0 0xa8000 0x1000>; uart4: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; @@ -1455,7 +1455,7 @@ ranges = <0x0 0xaa000 0x1000>; uart5: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = ; status = "disabled"; From 71f729ef73ce68de35f15b6ce9c257a4140bec04 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 18 May 2021 12:36:42 -0500 Subject: [PATCH 209/511] ARM: dts: OMAP2420: Drop interrupt-names from mailbox node The interrupt-names property is neither defined nor used in either of the OMAP Mailbox binding or the driver. So, drop them. This is in preparation for converting the OMAP Mailbox binding to YAML format. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2420.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 494bf6972005ba..35f8d1f6878edf 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -192,7 +192,6 @@ compatible = "ti,omap2-mailbox"; reg = <0x48094000 0x200>; interrupts = <26>, <34>; - interrupt-names = "dsp", "iva"; ti,hwmods = "mailbox"; #mbox-cells = <1>; ti,mbox-num-users = <4>; From 94a69e06264891fc01098aad794a2b327c248d2f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 18 May 2021 12:36:43 -0500 Subject: [PATCH 210/511] ARM: dts: OMAP2/OMAP3: Rename processor sub-mailbox nodes The OMAP sub-mailbox used to communicate with the DSP and IVA remote processors are currently named after the processor name. These can be confused with the remote processors themselves. Rename them to remove the ambiguity and use the prefix mbox to also adhere to the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2420.dtsi | 4 ++-- arch/arm/boot/dts/omap2430.dtsi | 2 +- arch/arm/boot/dts/omap3.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 35f8d1f6878edf..bb529a2a295db1 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -196,11 +196,11 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; - mbox_dsp: dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; - mbox_iva: iva { + mbox_iva: mbox-iva { ti,mbox-tx = <2 1 3>; ti,mbox-rx = <3 1 3>; }; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index d19d8ba3b60705..23115ba61bc06c 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -284,7 +284,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; - mbox_dsp: dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index c5b9da0d7e6cea..574bda7a4afdb9 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -440,7 +440,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <2>; ti,mbox-num-fifos = <2>; - mbox_dsp: dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; From 8e880dfefd61fdb80945b45978d6ac821e83d29b Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 18 May 2021 12:36:44 -0500 Subject: [PATCH 211/511] ARM: dts: AM33xx/AM43xx: Rename wkup_m3 sub-mailbox node The OMAP sub-mailbox used to communicate with the Wakeup M3 remote processor is currently named wkup_m3. This name can be confused with the remote processor node. So, rename this to mbox-wkup-m3 to remove the ambiguity and to also adhere to the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 2 +- arch/arm/boot/dts/am437x-l4.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index dcce5e3e001eba..268793bd88cb77 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1486,7 +1486,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { + mbox_wkupm3: mbox-wkup-m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index d681f51005780d..204d3d42b09f0f 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -1168,7 +1168,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { + mbox_wkupm3: mbox-wkup-m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; From 9e7f5ee1137397def6580461e27e5efcb68183ee Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 18 May 2021 12:36:45 -0500 Subject: [PATCH 212/511] ARM: dts: OMAP2+: Replace underscores in sub-mailbox node names A number of sub-mailbox node names in various OMAP2+ dts files are currently using underscores. This is not adhering to the node name convention, fix all of these to use hiphens. These nodes are already using the prefix mbox, so they will be in compliance with the sub-mailbox node name convention being added in the OMAP Mailbox YAML binding as well. Signed-off-by: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 8 ++++---- arch/arm/boot/dts/dm816x.dtsi | 2 +- arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi | 6 +++--- arch/arm/boot/dts/dra72x.dtsi | 6 +++--- arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi | 2 +- arch/arm/boot/dts/dra74x.dtsi | 8 ++++---- arch/arm/boot/dts/omap4-l4.dtsi | 4 ++-- arch/arm/boot/dts/omap5-l4.dtsi | 4 ++-- 8 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 39eba2bc36ddf8..aed81568a297d0 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -454,20 +454,20 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 3551a64963f8d4..1825d912b8ab45 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -351,7 +351,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <0 0 0>; }; diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi index a25749a1c36590..a5bdc6431d8d03 100644 --- a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi @@ -5,17 +5,17 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index d403acc754b688..85ab1f46e56b21 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -77,12 +77,12 @@ }; &mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -90,7 +90,7 @@ }; &mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi index b1147a4b77f9d6..3256631510c564 100644 --- a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi @@ -6,7 +6,7 @@ #include "dra7-ipu-dsp-common.dtsi" &mailbox6 { - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index e1850d6c841a70..411ad295c201d0 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -188,12 +188,12 @@ }; &mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -201,12 +201,12 @@ }; &mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 99721673d7afdd..46b8f9efd41316 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -600,11 +600,11 @@ #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { + mbox_ipu: mbox-ipu { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <2 0 0>; }; diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index b148b289e83015..06cc3a19ddaa93 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -616,11 +616,11 @@ #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { + mbox_ipu: mbox-ipu { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <2 0 0>; }; From 1b32fce42bff899dfb9b72962f46ca5542c7647c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 25 May 2021 11:15:12 +0200 Subject: [PATCH 213/511] ARM: dts: alt: Add SW2 as GPIO keys SW2 on Alt is connected as on Lager board. So, use the same GPIO settings. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20210525091512.29119-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794-alt.dts | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index f9dba5688d3ffd..f330d796a772c3 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r8a7794.dtsi" #include +#include / { model = "Alt"; @@ -94,6 +95,42 @@ #size-cells = <1>; }; + keyboard { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + + one { + linux,code = ; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + }; + two { + linux,code = ; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; + three { + linux,code = ; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + }; + four { + linux,code = ; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + }; + }; + vga-encoder { compatible = "adi,adv7123"; @@ -319,6 +356,11 @@ groups = "usb1"; function = "usb1"; }; + + keyboard_pins: keyboard { + pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; + bias-pull-up; + }; }; &cmt0 { From 43ffb52862c631ebdf7ec8a12fe826f5d531c88e Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 29 Apr 2021 10:42:53 +0200 Subject: [PATCH 214/511] arm64: dts: meson: vim3: enable hdmi audio loopback Enable audio capture frontends and a tdm decoder. This makes it possible to loopback the audio played on the hdmi codec, which is the only output interface at the moment. Of course, one TODDR device would be enough to do that but since the 3 FRDDRs are enabled on the playback side, let's do the same on the capture side. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20210429084253.59692-1-jbrunet@baylibre.com --- .../boot/dts/amlogic/meson-khadas-vim3.dtsi | 41 +++++++++++++++++-- .../dts/amlogic/meson-sm1-khadas-vim3l.dts | 13 ++++++ 2 files changed, 50 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 66d67524b03198..3cf4ecb6d52e3c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -171,11 +171,16 @@ sound { compatible = "amlogic,axg-sound-card"; model = "KHADAS-VIM3"; - audio-aux-devs = <&tdmout_a>; + audio-aux-devs = <&tdmin_a>, <&tdmout_a>; audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", "TDMOUT_A IN 1", "FRDDR_B OUT 0", "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT"; + "TDM_A Playback", "TDMOUT_A OUT", + "TDMIN_A IN 0", "TDM_A Capture", + "TDMIN_A IN 3", "TDM_A Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT"; assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, @@ -198,8 +203,20 @@ sound-dai = <&frddr_c>; }; - /* 8ch hdmi interface */ dai-link-3 { + sound-dai = <&toddr_a>; + }; + + dai-link-4 { + sound-dai = <&toddr_b>; + }; + + dai-link-5 { + sound-dai = <&toddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-6 { sound-dai = <&tdmif_a>; dai-format = "i2s"; dai-tdm-slot-tx-mask-0 = <1 1>; @@ -214,7 +231,7 @@ }; /* hdmi glue */ - dai-link-4 { + dai-link-7 { sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; codec { @@ -454,10 +471,26 @@ status = "okay"; }; +&tdmin_a { + status = "okay"; +}; + &tdmout_a { status = "okay"; }; +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + &tohdmitx { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index 06de0b1ce72678..f2c09814359441 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -32,6 +32,19 @@ regulator-boot-on; regulator-always-on; }; + + sound { + model = "G12B-KHADAS-VIM3L"; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT", + "TDMIN_A IN 0", "TDM_A Capture", + "TDMIN_A IN 13", "TDM_A Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT"; + }; }; &cpu0 { From ddbdaa4d596396e3aa0d60a0ab023d19822a3682 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 14 May 2021 16:32:53 +0200 Subject: [PATCH 215/511] arm64: dts: meson-sm1: add toacodec node Add toacodec node for Amlogic SM1 SoCs. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20210514143255.3352774-2-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index c309517abae32f..3d8b1f4f2001b2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -401,6 +401,16 @@ status = "disabled"; }; + toacodec: audio-controller@740 { + compatible = "amlogic,sm1-toacodec", + "amlogic,g12a-toacodec"; + reg = <0x0 0x740 0x0 0x4>; + #sound-dai-cells = <1>; + sound-name-prefix = "TOACODEC"; + resets = <&clkc_audio AUD_RESET_TOACODEC>; + status = "disabled"; + }; + tohdmitx: audio-controller@744 { compatible = "amlogic,sm1-tohdmitx", "amlogic,g12a-tohdmitx"; From c53ab8f96af1f1fcaa0c1bc851a7704ae4b413d2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 14 May 2021 16:32:54 +0200 Subject: [PATCH 216/511] dt-bindings: arm: amlogic: add Banana PI M5 bindings Add bindings for the Banana PI M5 board. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210514143255.3352774-3-narmstrong@baylibre.com --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 97fb9626634435..6423377710eeac 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -167,6 +167,7 @@ properties: - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC items: - enum: + - bananapi,bpi-m5 - hardkernel,odroid-c4 - hardkernel,odroid-hc4 - khadas,vim3l From 976e920183e406726637db925efdf8b407a2d03a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 14 May 2021 16:32:55 +0200 Subject: [PATCH 217/511] arm64: dts: meson-sm1: add Banana PI BPI-M5 board dts Banana Pi BPI-M5 is a credit card format SBC with the following features: - Amlogic S905X3 quad core Cortex-A55 - Mali-G31 GPU - 4GB LPDDR4 - 16GB eMMC flash - 4 USB 3.0 - 1 GbE ethernet - HDMI output - 2x LEDS - SDCard - 2.5mm Jack with Stereo Audio + CVBS - Infrared Received - ADC Button - GPIO Button - 40 pins header + 3pins debug header Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210514143255.3352774-4-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/meson-sm1-bananapi-m5.dts | 646 ++++++++++++++++++ 2 files changed, 647 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index a58ccecfcb551b..faa0a79a34f549 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts new file mode 100644 index 00000000000000..effaa138b5f983 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts @@ -0,0 +1,646 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 BayLibre SAS + * Author: Neil Armstrong + */ + +/dts-v1/; + +#include "meson-sm1.dtsi" +#include +#include +#include +#include +#include + +/ { + compatible = "bananapi,bpi-m5", "amlogic,sm1"; + model = "Banana Pi BPI-M5"; + + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + key { + label = "SW3"; + linux,code = ; + press-threshold-microvolt = <1700000>; + }; + }; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* TOFIX: handle CVBS_DET on SARADC channel 0 */ + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key { + label = "SW1"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + green { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + + blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_1v8: regulator-emmc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + dc_in: regulator-dc_in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddio_c: regulator-vddio_c { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_C"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + + gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>; + gpios-states = <1>; + + states = <1800000 0>, + <3300000 1>; + }; + + tflash_vdd: regulator-tflash_vdd { + compatible = "regulator-fixed"; + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + vddcpu: regulator-vddcpu { + /* + * SY8120B1ABC DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <1050000>; + + vin-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + /* USB Hub Power Enable */ + vl_pwr_en: regulator-vl_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "VL_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + + gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "BPI-M5"; + audio-widgets = "Line", "Lineout"; + audio-aux-devs = <&tdmout_b>, <&tdmout_c>, + <&tdmin_a>, <&tdmin_b>, <&tdmin_c>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "TDMOUT_C IN 0", "FRDDR_A OUT 2", + "TDMOUT_C IN 1", "FRDDR_B OUT 2", + "TDMOUT_C IN 2", "FRDDR_C OUT 2", + "TDM_C Playback", "TDMOUT_C OUT", + "TDMIN_A IN 4", "TDM_B Loopback", + "TDMIN_B IN 4", "TDM_B Loopback", + "TDMIN_C IN 4", "TDM_B Loopback", + "TDMIN_A IN 5", "TDM_C Loopback", + "TDMIN_B IN 5", "TDM_C Loopback", + "TDMIN_C IN 5", "TDM_C Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT", + "TODDR_A IN 2", "TDMIN_C OUT", + "TODDR_B IN 2", "TDMIN_C OUT", + "TODDR_C IN 2", "TDMIN_C OUT", + "Lineout", "ACODEC LOLP", + "Lineout", "ACODEC LORP"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + dai-link-3 { + sound-dai = <&toddr_a>; + }; + + dai-link-4 { + sound-dai = <&toddr_b>; + }; + + dai-link-5 { + sound-dai = <&toddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-6 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + + codec-1 { + sound-dai = <&toacodec TOACODEC_IN_B>; + }; + }; + + /* i2s jack output interface */ + dai-link-7 { + sound-dai = <&tdmif_c>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; + }; + + codec-1 { + sound-dai = <&toacodec TOACODEC_IN_C>; + }; + }; + + /* hdmi glue */ + dai-link-8 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + + /* acodec glue */ + dai-link-9 { + sound-dai = <&toacodec TOACODEC_OUT>; + + codec { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddao_1v8>; + status = "okay"; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; + clock-latency = <50000>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&gpio { + gpio-line-names = + /* GPIOZ */ + "ETH_MDIO", /* GPIOZ_0 */ + "ETH_MDC", /* GPIOZ_1 */ + "ETH_RXCLK", /* GPIOZ_2 */ + "ETH_RX_DV", /* GPIOZ_3 */ + "ETH_RXD0", /* GPIOZ_4 */ + "ETH_RXD1", /* GPIOZ_5 */ + "ETH_RXD2", /* GPIOZ_6 */ + "ETH_RXD3", /* GPIOZ_7 */ + "ETH_TXCLK", /* GPIOZ_8 */ + "ETH_TXEN", /* GPIOZ_9 */ + "ETH_TXD0", /* GPIOZ_10 */ + "ETH_TXD1", /* GPIOZ_11 */ + "ETH_TXD2", /* GPIOZ_12 */ + "ETH_TXD3", /* GPIOZ_13 */ + "ETH_INTR", /* GPIOZ_14 */ + "ETH_NRST", /* GPIOZ_15 */ + /* GPIOH */ + "HDMI_SDA", /* GPIOH_0 */ + "HDMI_SCL", /* GPIOH_1 */ + "HDMI_HPD", /* GPIOH_2 */ + "HDMI_CEC", /* GPIOH_3 */ + "VL-RST_N", /* GPIOH_4 */ + "CON1-P36", /* GPIOH_5 */ + "VL-PWREN", /* GPIOH_6 */ + "WiFi_3V3_1V8", /* GPIOH_7 */ + "TFLASH_VDD_EN", /* GPIOH_8 */ + /* BOOT */ + "eMMC_D0", /* BOOT_0 */ + "eMMC_D1", /* BOOT_1 */ + "eMMC_D2", /* BOOT_2 */ + "eMMC_D3", /* BOOT_3 */ + "eMMC_D4", /* BOOT_4 */ + "eMMC_D5", /* BOOT_5 */ + "eMMC_D6", /* BOOT_6 */ + "eMMC_D7", /* BOOT_7 */ + "eMMC_CLK", /* BOOT_8 */ + "", + "eMMC_CMD", /* BOOT_10 */ + "", + "eMMC_RST#", /* BOOT_12 */ + "eMMC_DS", /* BOOT_13 */ + /* GPIOC */ + "SD_D0_B", /* GPIOC_0 */ + "SD_D1_B", /* GPIOC_1 */ + "SD_D2_B", /* GPIOC_2 */ + "SD_D3_B", /* GPIOC_3 */ + "SD_CLK_B", /* GPIOC_4 */ + "SD_CMD_B", /* GPIOC_5 */ + "CARD_EN_DET", /* GPIOC_6 */ + "", + /* GPIOA */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", + "CON1-P27", /* GPIOA_14 */ + "CON1-P28", /* GPIOA_15 */ + /* GPIOX */ + "CON1-P16", /* GPIOX_0 */ + "CON1-P18", /* GPIOX_1 */ + "CON1-P22", /* GPIOX_2 */ + "CON1-P11", /* GPIOX_3 */ + "CON1-P13", /* GPIOX_4 */ + "CON1-P07", /* GPIOX_5 */ + "CON1-P33", /* GPIOX_6 */ + "CON1-P15", /* GPIOX_7 */ + "CON1-P19", /* GPIOX_8 */ + "CON1-P21", /* GPIOX_9 */ + "CON1-P24", /* GPIOX_10 */ + "CON1-P23", /* GPIOX_11 */ + "CON1-P08", /* GPIOX_12 */ + "CON1-P10", /* GPIOX_13 */ + "CON1-P29", /* GPIOX_14 */ + "CON1-P31", /* GPIOX_15 */ + "CON1-P26", /* GPIOX_16 */ + "CON1-P03", /* GPIOX_17 */ + "CON1-P05", /* GPIOX_18 */ + "CON1-P32"; /* GPIOX_19 */ + + /* + * WARNING: The USB Hub on the BPI-M5 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = ; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&gpio_ao { + gpio-line-names = + /* GPIOAO */ + "DEBUG TX", /* GPIOAO_0 */ + "DEBUG RX", /* GPIOAO_1 */ + "SYS_LED2", /* GPIOAO_2 */ + "UPDATE_KEY", /* GPIOAO_3 */ + "CON1-P40", /* GPIOAO_4 */ + "IR_IN", /* GPIOAO_5 */ + "TF_3V3N_1V8_EN", /* GPIOAO_6 */ + "CON1-P35", /* GPIOAO_7 */ + "CON1-P12", /* GPIOAO_8 */ + "CON1-P37", /* GPIOAO_9 */ + "CON1-P38", /* GPIOAO_10 */ + "SYS_LED", /* GPIOAO_11 */ + /* GPIOE */ + "VDDEE_PWM", /* GPIOE_0 */ + "VDDCPU_PWM", /* GPIOE_1 */ + "TF_PWR_EN"; /* GPIOE_2 */ +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&dc_in>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddao_1v8>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + /* TOFIX: SD card is barely usable in SDR modes */ + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&vddio_c>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmif_c { + status = "okay"; +}; + +&tdmin_a { + status = "okay"; +}; + +&tdmin_b { + status = "okay"; +}; + +&tdmin_c { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tdmout_c { + status = "okay"; +}; + +&toacodec { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; +}; + +&usb2_phy0 { + phy-supply = <&dc_in>; +}; + +&usb2_phy1 { + /* Enable the hub which is connected to this port */ + phy-supply = <&vl_pwr_en>; +}; From 9e79e58f330ea4860f2ced65a8a35dfb05fc03c1 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 19 May 2021 17:41:35 +0100 Subject: [PATCH 218/511] arm64: tegra: Add PMU node for Tegra194 Populate the device-tree node for the PMU device on Tegra194. This also fixes the following warning that is observed on booting Tegra194. ERR KERN kvm: pmu event creation failed -2 Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9449156fae3916..2e40b604728335 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2345,6 +2345,20 @@ }; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 + &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; + }; + psci { compatible = "arm,psci-1.0"; status = "okay"; From d67113c261c196232c96dbed1ff2fbd071c8c457 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 20 May 2021 11:18:22 +0200 Subject: [PATCH 219/511] ARM: dts: rockchip: move mmc aliases to board dts on rk3066/rk3188 As suggested by Arnd Bergmann, the newly added mmc aliases should be board specific, so move them from the general dtsi to the individual boards. Suggested-by: Arnd Bergmann Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210520091822.28491-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 5 +++++ arch/arm/boot/dts/rk3066a-marsboard.dts | 4 ++++ arch/arm/boot/dts/rk3066a-mk808.dts | 5 +++++ arch/arm/boot/dts/rk3066a-rayeager.dts | 6 ++++++ arch/arm/boot/dts/rk3188-bqedison2qc.dts | 6 ++++++ arch/arm/boot/dts/rk3188-px3-evb.dts | 5 +++++ arch/arm/boot/dts/rk3188-radxarock.dts | 4 ++++ arch/arm/boot/dts/rk3xxx.dtsi | 3 --- 8 files changed, 35 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index eba7a134497647..390aa33cd55ac8 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -12,6 +12,11 @@ model = "bq Curie 2"; compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index 6b121658d93cc2..a66d915aa0f657 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -10,6 +10,10 @@ model = "MarsBoard RK3066"; compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; + aliases { + mmc0 = &mmc0; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index eed9e60cffa231..9790bc63b50a11 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -10,6 +10,11 @@ model = "Rikomagic MK808"; compatible = "rikomagic,mk808", "rockchip,rk3066a"; + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index a73e8900c92410..12b2e59aebc478 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -11,6 +11,12 @@ model = "Rayeager PX2"; compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &emmc; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 66a0ff196eb1f4..85d3fce0142f6e 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -13,6 +13,12 @@ model = "BQ Edison2 Quad-Core"; compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &emmc; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index c32e1d441cf70b..39c60426c9c95a 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -11,6 +11,11 @@ model = "Rockchip PX3-EVB"; compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; + aliases { + mmc0 = &mmc0; + mmc1 = &emmc; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index b0fef82c0a71b7..36c0945f43b228 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -11,6 +11,10 @@ model = "Radxa Rock"; compatible = "radxa,rock", "rockchip,rk3188"; + aliases { + mmc0 = &mmc0; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index d473552e854747..f9bbc242444486 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -21,9 +21,6 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; - mshc0 = &emmc; - mshc1 = &mmc0; - mshc2 = &mmc1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; From b8928c2b5dba7484a80077d12be702ff71d8190f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 30 Mar 2021 20:18:31 +0200 Subject: [PATCH 220/511] arm64: tegra: Consolidate audio card names The current scheme for audio card names is suboptimal because it causes the automatically generated names (for ID and driver) to be truncated, which in turn can cause conflicts. Introduce a new scheme which reuses the board model for the names and appends the "HDA" and "APE" suffixes for the HDA and APE, respectively. As a side-effect these suffixes end up being used as the ID of the SoC sound cards which makes it easy for users to select them when using the ALSA command-line utilities, for example. As a separate measure, the driver name for the cards is now set by the corresponding audio driver (either tegra-hda or tegra-ape), making it a more useful identifier than the currently normalized card name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 4 ++-- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 683743f81849ac..74c1a5df3fdb75 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -817,7 +817,7 @@ }; hda@3510000 { - nvidia,model = "jetson-tx2-hda"; + nvidia,model = "NVIDIA Jetson TX2 HDA"; status = "okay"; }; @@ -1109,6 +1109,6 @@ <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>, <&dspk1_port>, <&dspk2_port>; - label = "jetson-tx2-ape"; + label = "NVIDIA Jetson TX2 APE"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index d618f197a1d3cd..96bd01cadb187d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -554,7 +554,7 @@ }; hda@3510000 { - nvidia,model = "jetson-xavier-hda"; + nvidia,model = "NVIDIA Jetson AGX Xavier HDA"; status = "okay"; }; @@ -831,7 +831,7 @@ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, <&dmic3_port>; - label = "jetson-xavier-ape"; + label = "NVIDIA Jetson AGX Xavier APE"; widgets = "Microphone", "CVB-RT MIC Jack", diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index d1d77220154f0c..a717d2b6613148 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -36,7 +36,7 @@ }; hda@3510000 { - nvidia,model = "jetson-xavier-nx-hda"; + nvidia,model = "NVIDIA Jetson Xavier NX HDA"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 497635af7fab90..7d3e3634743ee7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -424,6 +424,6 @@ <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>; - label = "jetson-tx1-ape"; + label = "NVIDIA Jetson TX1 APE"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index a9caaf7c0d67eb..d8409c1b43800d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1345,7 +1345,7 @@ }; hda@70030000 { - nvidia,model = "jetson-tx1-hda"; + nvidia,model = "NVIDIA Jetson TX1 HDA"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 14c128a5e248d6..7dbb13f20de760 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -441,7 +441,7 @@ }; hda@70030000 { - nvidia,model = "jetson-nano-hda"; + nvidia,model = "NVIDIA Jetson Nano HDA"; status = "okay"; }; @@ -1043,6 +1043,6 @@ <&i2s3_port>, <&i2s4_port>, <&dmic1_port>, <&dmic2_port>; - label = "jetson-nano-ape"; + label = "NVIDIA Jetson Nano APE"; }; }; From ec2fb989d03e7f79f7cd901cf9abf40aebba7acf Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 23 Apr 2021 11:31:33 +0530 Subject: [PATCH 221/511] arm64: dts: ti: k3-am64-mcu: Fix the compatible string in GPIO DT node Fix the compatible string in mcu domain GPIO device tree node. Fixes: 01a91e01b8fd ("arm64: dts: ti: k3-am64: Add GPIO DT nodes") Signed-off-by: Aswath Govindraju Reviewed-by: Lokesh Vutla Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210423060133.16473-1-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index deb19ae5e168ae..eaf7edb2ef4dd0 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -87,7 +87,7 @@ }; mcu_gpio0: gpio@4201000 { - compatible = "ti,am64-gpio", "keystone-gpio"; + compatible = "ti,am64-gpio", "ti,keystone-gpio"; reg = <0x0 0x4201000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; From 6ec8ba764165f6ecb6f6f7efbfd2ec7ad76dedcb Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 23 Apr 2021 12:17:57 +0530 Subject: [PATCH 222/511] arm64: dts: ti: k3-j7200: Remove "#address-cells" property from GPIO DT nodes GPIO device tree nodes do not have child nodes. Therefore, "#address-cells" property should not be added. Fixes: e0b2e6af39ea ("arm64: dts: ti: k3-j7200: Add gpio nodes") Signed-off-by: Aswath Govindraju Reviewed-by: Lokesh Vutla Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210423064758.25520-1-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ---- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 -- 2 files changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 19fea8adbcff42..7e71691959026e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -696,7 +696,6 @@ <149>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; @@ -714,7 +713,6 @@ <158>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; @@ -732,7 +730,6 @@ <167>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; @@ -750,7 +747,6 @@ <176>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 5663fe3ea46602..343449af53fb90 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -117,7 +117,6 @@ interrupts = <103>, <104>, <105>, <106>, <107>, <108>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <85>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; @@ -134,7 +133,6 @@ interrupts = <112>, <113>, <114>, <115>, <116>, <117>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <85>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; From a2894d85f44ba3f2bdf5806c8dc62e2ec40c1c09 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 12 May 2021 21:03:08 +0530 Subject: [PATCH 223/511] arm64: dts: ti: j7200-main: Enable USB2 PHY RX sensitivity workaround Enable work around feature built into the controller to address issue with RX Sensitivity for USB2 PHY. Fixes: 6197d7139d12 ("arm64: dts: ti: k3-j7200-main: Add USB controller") Signed-off-by: Roger Quadros Signed-off-by: Aswath Govindraju Reviewed-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210512153308.5840-1-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 7e71691959026e..a4b4b17a6ad74a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -683,6 +683,7 @@ "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; + cdns,phyrst-a-enable; }; }; From 69db725cdb2b803af67897a08ea54467d11f6020 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 26 May 2021 16:20:41 +0300 Subject: [PATCH 224/511] arm64: dts: ti: k3-am654x/j721e/j7200-common-proc-board: Fix MCU_RGMII1_TXC direction The MCU RGMII MCU_RGMII1_TXC pin is defined as input by mistake, although this does not make any difference functionality wise it's better to update to avoid confusion. Hence fix MCU RGMII MCU_RGMII1_TXC pin pinmux definitions to be an output in K3 am654x/j721e/j7200 board files. Signed-off-by: Grygorii Strashko Reviewed-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210526132041.6104-1-grygorii.strashko@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index eddb2ffb93ca69..97c3440884830d 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -136,7 +136,7 @@ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ - AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */ + AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */ AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index bedd01b7a32cea..d14f3c18b65fc0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -90,7 +90,7 @@ J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 60764366e22bdb..351bb84db65bf9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -237,7 +237,7 @@ J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; From 44b615ac9fab16d1552cd8360454077d411e3c35 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 27 May 2021 15:42:42 +0200 Subject: [PATCH 225/511] arm64: dts: renesas: Add missing opp-suspend properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tag the highest "Power Optimized" (1.5 GHz) Cortex-A57 operating point table entries for the RZ/G2M, R-Car M3-W and M3-W+ SoCs with the "opp-suspend" property. This makes sure the system will enter suspend in the same performance state as it will be resumed by the firmware later, avoiding state inconsistencies after resume. Based on a patch for R-Car M3-W in the BSP by Takeshi Kihara . Fixes: 800037e815b91d8c ("arm64: dts: renesas: r8a774a1: Add operating points") Fixes: da7e3113344fda50 ("arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices") Fixes: f51746ad7d1ff6b4 ("arm64: dts: renesas: Add Renesas R8A77961 SoC support") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/45a061c3b0463aac7d10664f47c4afdd999da50d.1619699721.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77960.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77961.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c3d312af6fe95f..78c121a89f11b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -76,6 +76,7 @@ opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; + opp-suspend; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index d21be2f195b3be..63bb395a6a6449 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -75,6 +75,7 @@ opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; + opp-suspend; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 941f18e5f5d29c..c8b73108a4c818 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -64,6 +64,7 @@ opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; + opp-suspend; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; From 659b38203f04f5c3d1dc60f1a3e54b582ad3841c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 29 Apr 2021 14:39:12 +0200 Subject: [PATCH 226/511] arm64: dts: renesas: r8a7796[01]: Fix OPP table entry voltages Correct the voltages in the "Power Optimized" (<= 1.5 GHz) Cortex-A57 operating point table entries for the R-Car M3-W and M3-W+ SoCs from 0.82V to 0.83V, as per the R-Car Gen3 EC Manual Errata for Revision 0.53. Based on a patch for R-Car M3-W in the BSP by Takeshi Kihara . Fixes: da7e3113344fda50 ("arm64: dts: renesas: r8a7796: Add OPPs table for cpu devices") Fixes: f51746ad7d1ff6b4 ("arm64: dts: renesas: Add Renesas R8A77961 SoC support") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b9e9db907514790574429b83d070c823b36085ef.1619699909.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 6 +++--- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 63bb395a6a6449..2bd8169735d351 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -63,17 +63,17 @@ opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; opp-suspend; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index c8b73108a4c818..3c73ee47791542 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -52,17 +52,17 @@ opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; opp-suspend; }; From 28cce9540b135cf42d6332e5bca8e5b5dd998b38 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 15:10:52 +0200 Subject: [PATCH 227/511] ARM: dts: lager: Configure pull-up for SOFT_SW GPIO keys The GPIO pins connected to the 4 Software Switches (SW2) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Link: https://lore.kernel.org/r/9fae3c0c2c0000f6b43c9ce87fe64a594b30a7da.1619785905.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7790-lager.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 2dad0742d2ba15..fa6d986b5d4632 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -81,6 +81,9 @@ keyboard { compatible = "gpio-keys"; + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + one { linux,code = ; label = "SW2-1"; @@ -659,6 +662,11 @@ groups = "audio_clk_a"; function = "audio_clk"; }; + + keyboard_pins: keyboard { + pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28"; + bias-pull-up; + }; }; ðer { From 1f27fedead91eb6077c299a98ea3d9fe2f9955db Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 15:10:53 +0200 Subject: [PATCH 228/511] ARM: dts: blanche: Configure pull-up for SOFT_SW and SW25 GPIO keys The GPIO pins connected to the 4 Software Switches (SW2) and the second Tact Switch (SW25) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. Note that the GPIO pin connected to the first Tact Switch (SW24) does have an external pull-up resistor. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/011e4c461767f2dd690b655b3dd501eb554184c1.1619785905.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7792-blanche.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index c100ae903a46bb..62aa9f61321bea 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -112,6 +112,9 @@ keyboard { compatible = "gpio-keys"; + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + key-1 { linux,code = ; label = "SW2-1"; @@ -235,6 +238,11 @@ function = "du1"; }; + keyboard_pins: keyboard { + pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02"; + bias-pull-up; + }; + pmic_irq_pins: pmicirq { groups = "intc_irq2"; function = "intc"; From 0003fa76d973e15263d8d03494aeef6a4361efa3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 15:10:54 +0200 Subject: [PATCH 229/511] ARM: dts: gose: Configure pull-up for SOFT_SW GPIO keys The GPIO pins connected to the 4 Software Switches ("SOFT_SW", SW2) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. While at it, rename the surrounding device node from "gpio-keys" to "keyboard", to comply with generic node name recommendations. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/1cdec892b1491309b12bdaf7bc8428b3a19b1ed5.1619785905.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7793-gose.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 87fa57a99399b7..479e0fdf0c3731 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -64,9 +64,12 @@ reg = <0 0x40000000 0 0x40000000>; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + key-1 { gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; linux,code = ; @@ -567,6 +570,11 @@ function = "audio_clk"; }; + keyboard_pins: keyboard { + pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; + bias-pull-up; + }; + vin0_pins: vin0 { groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; function = "vin0"; From 0eb17349042f1c5d8294b6b0a58bcda8b5db0e9d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 15:10:55 +0200 Subject: [PATCH 230/511] ARM: dts: silk: Configure pull-up for SOFT_SW GPIO keys The GPIO pins connected to the 4 Software Switches ("SOFT_SW", SW12) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. While at it, rename the surrounding device node from "gpio-keys" to "keyboard", to comply with generic node name recommendations. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/45f38a5333feba9bea80efeb5a41a6c3f60deda2.1619785905.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7794-silk.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index eb89a27a6ed0c9..cafa3046daa4ba 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -45,9 +45,12 @@ reg = <0 0x40000000 0 0x40000000>; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + key-3 { gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; linux,code = ; @@ -358,6 +361,11 @@ function = "du1"; }; + keyboard_pins: keyboard { + pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; + bias-pull-up; + }; + ssi_pins: sound { groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; function = "ssi"; From ef3082db434f3f87b83ccaa1ce4ebfd05535b651 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:51 +0300 Subject: [PATCH 231/511] ARM: tegra: acer-a500: Improve microphone detection Use edge-triggered interrupt and set delay to 100ms for microphone hook detection. This doesn't fix any known problems, but there is a smaller chance to miss insertion of the microphone now, which previously happened rarely. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2298fc034183b6..d7d97b7e479420 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -420,11 +420,14 @@ reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <2>; + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = < 0x0000 /* MIC_LR_OUT# GPIO, output, low */ 0x0000 /* FM2018-enable GPIO, output, low */ From a99d77c4b2ac9095d9bd5969996905886debbe8b Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:52 +0300 Subject: [PATCH 232/511] ARM: tegra: acer-a500: Specify proper voltage for WiFi SDIO bus Tegra20 has v2.00 SDMMC controller which doesn't support voltage switching and the WiFi SDIO bus voltage is fixed to 1.8v in accordance to the board's schematics, while MMC core confusingly saying that it's 3.3v because of the v2.00. Let's correct the voltage in the device-tree just for consistency. This is a minor improvement which doesn't fix any problems. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index d7d97b7e479420..eff9bfb2d44267 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -762,7 +762,7 @@ mmc-pwrseq = <&brcm_wifi_pwrseq>; vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_sys>; /* Azurewave AW-NH611 BCM4329 */ wifi@1 { From c46240c005ae7fe10c2fe753ead996379cbf73ff Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:53 +0300 Subject: [PATCH 233/511] ARM: tegra: acer-a500: Bump thermal trips by 10C It's possible to hit the temperature of the thermal zone in a very warm environment under a constant load, like watching a video using software decoding. It's even easier to hit the limit with a slightly overclocked CPU. Bump the temperature limit by 10C in order to improve user experience. Acer A500 has a large board and 10" display panel which are used for the heat dissipation, the SoC is placed far away from battery, hence we can safely bump the temperature limit. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index eff9bfb2d44267..15b7965599ee6e 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1059,15 +1059,15 @@ trips { trip0: cpu-alert0 { - /* start throttling at 50C */ - temperature = <50000>; + /* start throttling at 60C */ + temperature = <60000>; hysteresis = <200>; type = "passive"; }; trip1: cpu-crit { - /* shut down at 60C */ - temperature = <60000>; + /* shut down at 70C */ + temperature = <70000>; hysteresis = <2000>; type = "critical"; }; From b39a16b577cc11c7ab3fb67c8723c7ea057d96d4 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:54 +0300 Subject: [PATCH 234/511] ARM: tegra: Add reg property to Tegra20 EMC table device-tree nodes The reg property is now specified for the emc-tables nodes in the Tegra20 device-tree binding. Add reg property to the EMC table device-tree nodes of Tegra20 board device-trees in order to silence dt_binding_check warning about the missing property. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++++ arch/arm/boot/dts/tegra20-paz00.dts | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 15b7965599ee6e..883b76f1039b76 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1088,6 +1088,7 @@ emc-tables@0 { nvidia,ram-code = <0>; /* elpida-8gb */ + reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -1185,6 +1186,7 @@ emc-tables@1 { nvidia,ram-code = <1>; /* elpida-4gb */ + reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1282,6 +1284,7 @@ emc-tables@2 { nvidia,ram-code = <2>; /* hynix-8gb */ + reg = <2>; #address-cells = <1>; #size-cells = <0>; @@ -1379,6 +1382,7 @@ emc-tables@3 { nvidia,ram-code = <3>; /* hynix-4gb */ + reg = <3>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 940a9f31cd8640..63d62418d4b869 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -318,6 +318,7 @@ nvidia,ram-code = <0x0>; #address-cells = <1>; #size-cells = <0>; + reg = <0>; emc-table@166500 { reg = <166500>; From 5f45da704de425d74abd75feaa928fc8a3df03ba Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:55 +0300 Subject: [PATCH 235/511] ARM: tegra: wm8903: Fix polarity of headphones-detection GPIO in device-trees All Tegra boards which use WM8903 audio codec are specifying a wrong polarity for the headphones detection GPIO. The kernel driver hardcodes the polarity to active-low, which is the correct polarity, so we can fix the device-trees safely. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 +- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-medcom-wide.dts | 2 +- arch/arm/boot/dts/tegra20-plutux.dts | 2 +- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- arch/arm/boot/dts/tegra20-tec.dts | 2 +- arch/arm/boot/dts/tegra20-ventana.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 883b76f1039b76..1976c383912aa4 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1033,7 +1033,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; nvidia,headset; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 86494cb4d5a1d9..ae4312eedcbd53 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -748,7 +748,7 @@ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; + GPIO_ACTIVE_LOW>; nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index a348ca30e522b0..b31c9bca16e6a4 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -84,7 +84,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 378f23b2958b15..5811b7006a9bf6 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -52,7 +52,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index c24d4a37613e99..92d494b8c3d25a 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -911,7 +911,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 44ced60315de17..10ff09d86efa7f 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -61,7 +61,7 @@ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; + GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 99a356c1ccec34..5a2578b3707f42 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -709,7 +709,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 2dff14b87f3e61..d9dd11569d4b20 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -630,7 +630,7 @@ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; + GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, From 2e09908f37c34356baae72f047bbb8fc9faac32f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:56 +0300 Subject: [PATCH 236/511] ARM: tegra: paz00: Add CPU thermal zone Add thermal zone with a passive cooling trip for CPU. Attach it to the LM90 sensor which monitors CPU temperature. Now CPU frequencies will be throttled once trip point is reached, preventing critical overheat. Tested-by: Agneli Tested-by: Paul Fertser Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 42 +++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 63d62418d4b869..3180bff90756fd 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -2,6 +2,8 @@ /dts-v1/; #include +#include + #include "tegra20.dtsi" #include "tegra20-cpu-opp.dtsi" #include "tegra20-cpu-opp-microvolt.dtsi" @@ -498,9 +500,10 @@ }; }; - adt7461@4c { + adt7461: temperature-sensor@4c { compatible = "adi,adt7461"; reg = <0x4c>; + #thermal-sensor-cells = <1>; }; }; @@ -655,11 +658,46 @@ cpu0: cpu@0 { cpu-supply = <&cpu_vdd_reg>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { cpu-supply = <&cpu_vdd_reg>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <500>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + thermal-sensors = <&adt7461 1>; + + trips { + trip0: cpu-alert0 { + /* start throttling at 80C */ + temperature = <80000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: cpu-crit { + /* shut down at 85C */ + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; }; From 8b73d8c3d2c93c6e3db19d8c2641fc74dc9f8bf1 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:57 +0300 Subject: [PATCH 237/511] ARM: tegra: nexus7: Add i2c-thermtrip node Add i2c-thermtrip node which enables emergency shutdown by PMC on SoC die overheat detected by TSENSOR. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi | 9 +++++++++ .../boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index 17b6682ffce8a4..53966fa4eef25e 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -182,4 +182,13 @@ enable-active-high; vin-supply = <&vdd_3v3_sys>; }; + + pmc@7000e400 { + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x3c>; + nvidia,reg-addr = <0x41>; + nvidia,reg-data = <0xe0>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi index b97da45ebdb48b..06b5e8a5ce5dd0 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -147,4 +147,13 @@ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + pmc@7000e400 { + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x80>; + }; + }; }; From 7168137532d2d27d34811cd5a073ad5c3215b592 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:58 +0300 Subject: [PATCH 238/511] ARM: tegra: nexus7: Improve thermal zones Remove unused thermal zone just to clean up device-tree and set critical temperature further apart from the passive cooling trip point since during or thermal testing of Asus Transformer devices we found that CPU could reach the critical temperature in a certain kernel configurations for a brief moment if critical trip point is set close to the passive trip point and then device will be immediately shut off without getting a chance to cool down using passive cooling. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index dc773b1bf8ee81..3376d06facbbaa 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1252,13 +1252,6 @@ }; thermal-zones { - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <0>; /* milliseconds */ - - thermal-sensors = <&nct72 0>; - }; - cpu-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ @@ -1274,8 +1267,8 @@ }; trip1: cpu-crit { - /* shut down at 60C */ - temperature = <60000>; + /* shut down at 65C */ + temperature = <65000>; hysteresis = <2000>; type = "critical"; }; From 4405d933b66c0c9268de3b3d9cab3e3b780c64f1 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:25:59 +0300 Subject: [PATCH 239/511] ARM: tegra: nexus7: Remove monitored-battery property The bq27541 Linux kernel driver will try to reprogram controller based on the values from monitored-battery node, but it fails to do so because controller was locked by manufacturer. Still this is a very undesirable behaviour, hence let's remove the optional battery node. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 3376d06facbbaa..c6264738f593b3 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -927,7 +927,6 @@ compatible = "ti,bq27541"; reg = <0x55>; power-supplies = <&power_supply>; - monitored-battery = <&battery_cell>; }; power_supply: charger@6a { From c4dd6066bc304649e3159f1c7a08ece25d537e00 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 10 May 2021 23:26:00 +0300 Subject: [PATCH 240/511] ARM: tegra: nexus7: Correct 3v3 regulator GPIO of PM269 variant The 3v3 regulator GPIO is GP6 and not GP7, which is the DDR regulator. Both regulators are always-on, nevertheless the DT model needs to be corrected, fix it. Reported-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi index 06b5e8a5ce5dd0..9365ae607239f6 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -144,7 +144,7 @@ }; vdd_3v3_sys: regulator@1 { - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; enable-active-high; }; From 592b74b1f0ebfe49d2e66b2b4bd95ff3678c5696 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 11 May 2021 00:10:06 +0300 Subject: [PATCH 241/511] ARM: tegra: Add cooling cells to ACTMON device-tree node The ACTMON module monitors activity of memory clients and decisions about a minimum required memory frequency are made based on info from ACTMON. Add cooling cells to ACTMON device-tree node in order to turn it into a cooling device that will throttle memory freq on overheat. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 3 ++- arch/arm/boot/dts/tegra30.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 0b678afb2a5ccf..8b38f123f55428 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -283,7 +283,7 @@ reg = <0x0 0x60007000 0x0 0x1000>; }; - actmon@6000c800 { + actmon: actmon@6000c800 { compatible = "nvidia,tegra124-actmon"; reg = <0x0 0x6000c800 0x0 0x400>; interrupts = ; @@ -295,6 +295,7 @@ operating-points-v2 = <&emc_bw_dfs_opp_table>; interconnects = <&mc TEGRA124_MC_MPCORER &emc>; interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 44a6dbba708181..c577c191be4bbf 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -410,7 +410,7 @@ reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ }; - actmon@6000c800 { + actmon: actmon@6000c800 { compatible = "nvidia,tegra30-actmon"; reg = <0x6000c800 0x400>; interrupts = ; @@ -422,6 +422,7 @@ operating-points-v2 = <&emc_bw_dfs_opp_table>; interconnects = <&mc TEGRA30_MC_MPCORER &emc>; interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { From fe7482b88590635939c4bb786e1cd3bbd9ea1682 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 11 May 2021 00:10:07 +0300 Subject: [PATCH 242/511] ARM: tegra: nexus7: Enable memory frequency thermal throttling using ACTMON The ACTMON module monitors activity of memory clients and then devfreq driver makes decisions about a required memory frequency based on info from ACTMON. Add ACTMON device to the thermal zone of Nexus 7 in order to use it as a cooling device which throttles memory freq on overheat. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index c6264738f593b3..ae8300baa2d476 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1279,7 +1279,9 @@ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; }; }; }; From 4c101a4466983abe7798493ef17279cc3f8eb028 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 11 May 2021 00:10:08 +0300 Subject: [PATCH 243/511] ARM: tegra: ouya: Enable memory frequency thermal throttling using ACTMON The ACTMON module monitors activity of memory clients and then devfreq driver makes decisions about a required memory frequency based on info from ACTMON. Add ACTMON device to the thermal zone of Ouya in order to use it as a cooling device which throttles memory freq on overheat. Tested-by: Peter Geis Tested-by: Matt Merhar Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-ouya.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 9a10e0d6976266..ab8744f3d72dac 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -463,7 +463,9 @@ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; }; }; }; From d42b3e045a34ec7c88c818ee057f7c2ecc8f9fdd Mon Sep 17 00:00:00 2001 From: Andreas Rehn Date: Tue, 25 May 2021 19:31:59 +0200 Subject: [PATCH 244/511] ARM: dts: sun8i: v3s: enable emac for zero Dock dwmac-sun8i supports v3s and Licheepi-zero Dock provides an ethernet port furthermore, align nodes in alphabetical order Signed-off-by: Andreas Rehn Reviewed-by: Andre Przywara Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210525173159.183415-1-rehn.andreas86@gmail.com --- .../boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts index db5cd0b8574b32..752ad05c8f8315 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts @@ -49,16 +49,18 @@ compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; + aliases { + ethernet0 = &emac; + }; + leds { /* The LEDs use PG0~2 pins, which conflict with MMC1 */ status = "disabled"; }; }; -&mmc1 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; +&emac { + allwinner,leds-active-low; status = "okay"; }; @@ -94,3 +96,10 @@ voltage = <800000>; }; }; + +&mmc1 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; From c4a41429951890d0bf7c1ef49b1fa1c8dfb1a034 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 16 May 2021 19:30:41 +0300 Subject: [PATCH 245/511] dt-bindings: clock: tegra: Convert to schema Convert NVIDIA Tegra clock bindings to schema. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../bindings/clock/nvidia,tegra114-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra124-car.txt | 107 ---------------- .../bindings/clock/nvidia,tegra124-car.yaml | 115 ++++++++++++++++++ .../bindings/clock/nvidia,tegra20-car.txt | 63 ---------- .../bindings/clock/nvidia,tegra20-car.yaml | 69 +++++++++++ .../bindings/clock/nvidia,tegra210-car.txt | 56 --------- .../bindings/clock/nvidia,tegra30-car.txt | 63 ---------- 7 files changed, 184 insertions(+), 352 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt deleted file mode 100644 index 9acea9d931600e..00000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra114 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra114-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA114_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt deleted file mode 100644 index 7f02fb4ca4adb0..00000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra124 and Tegra132 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in the header files - (which covers IDs common - to Tegra124 and Tegra132) and - (for Tegra124-specific clocks). -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. -- nvidia,external-memory-controller : phandle of the EMC driver. - -The node should contain a "emc-timings" subnode for each supported RAM type (see -field RAM_CODE in register PMC_STRAPPING_OPT_A). - -Required properties for "emc-timings" nodes : -- nvidia,ram-code : Should contain the value of RAM_CODE this timing set - is used for. - -Each "emc-timings" node should contain a "timing" subnode for every supported -EMC clock rate. - -Required properties for "timing" nodes : -- clock-frequency : Should contain the memory clock rate to which this timing -relates. -- nvidia,parent-clock-frequency : Should contain the rate at which the current -parent of the EMC clock should be running at this timing. -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - emc-parent : the clock that should be the parent of the EMC clock at this -timing. - -Example SoC include file: - -/ { - tegra_car: clock@60006000 { - compatible = "nvidia,tegra124-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA124_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <112400000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; - - clock@60006000 { - emc-timings-3 { - nvidia,ram-code = <3>; - - timing-12750000 { - clock-frequency = <12750000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - timing-20400000 { - clock-frequency = <20400000>; - nvidia,parent-clock-frequency = <408000000>; - clocks = <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "emc-parent"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml new file mode 100644 index 00000000000000..ec7ab148365258 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Clock and Reset Controller + +maintainers: + - Jon Hunter + - Thierry Reding + +description: | + The Clock and Reset (CAR) is the HW module responsible for muxing and gating + Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. + + CLKGEN provides the registers to program the PLLs. It controls most of + the clock source programming and most of the clock dividers. + + CLKGEN input signals include the external clock for the reference frequency + (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). + + Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. + + RSTGEN provides the registers needed to control resetting of each block in + the Tegra system. + +properties: + compatible: + const: nvidia,tegra124-car + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + "#reset-cells": + const: 1 + + nvidia,external-memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the external memory controller node + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that + this timing set is used for + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + external memory clock rate in Hz + minimum: 1000000 + maximum: 1000000000 + + nvidia,parent-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + rate of parent clock in Hz + minimum: 1000000 + maximum: 1000000000 + + clocks: + items: + - description: parent clock of EMC + + clock-names: + items: + - const: emc-parent + + required: + - clock-frequency + - nvidia,parent-clock-frequency + - clocks + - clock-names + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - '#clock-cells' + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + + car: clock-controller@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb-controller@c5004000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5004000 0x4000>; + clocks = <&car TEGRA124_CLK_USB2>; + resets = <&car TEGRA124_CLK_USB2>; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt deleted file mode 100644 index 6c5901b503d019..00000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra20 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra20-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA20_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml new file mode 100644 index 00000000000000..459d2a52539355 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Clock and Reset Controller + +maintainers: + - Jon Hunter + - Thierry Reding + +description: | + The Clock and Reset (CAR) is the HW module responsible for muxing and gating + Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. + + CLKGEN provides the registers to program the PLLs. It controls most of + the clock source programming and most of the clock dividers. + + CLKGEN input signals include the external clock for the reference frequency + (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). + + Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. + + RSTGEN provides the registers needed to control resetting of each block in + the Tegra system. + +properties: + compatible: + enum: + - nvidia,tegra20-car + - nvidia,tegra30-car + - nvidia,tegra114-car + - nvidia,tegra210-car + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + + car: clock-controller@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb-controller@c5004000 { + compatible = "nvidia,tegra20-ehci"; + reg = <0xc5004000 0x4000>; + clocks = <&car TEGRA20_CLK_USB2>; + resets = <&car TEGRA20_CLK_USB2>; + }; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt deleted file mode 100644 index 26f237f641b71f..00000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt +++ /dev/null @@ -1,56 +0,0 @@ -NVIDIA Tegra210 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra210-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra210-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA210_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt deleted file mode 100644 index 63618cde12df16..00000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra30 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra30-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - . -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra30-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA30_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; From 1cebcf9932ab76102e8cfc555879574693ba8956 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 9 Apr 2021 01:00:01 +0200 Subject: [PATCH 246/511] ARM: dts: stm32: Rework LAN8710Ai PHY reset on DHCOM SoM The Microchip LAN8710Ai PHY requires XTAL1/CLKIN external clock to be enabled when the nRST is toggled according to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B page 35 section 3.8.5.1 Hardware Reset: " A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page 59 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal. " This is accidentally fulfilled in the current setup, where ETHCK_K is used to supply both PHY XTAL1/CLKIN and is also fed back through eth_clk_fb to supply ETHRX clock of the DWMAC. Hence, the DWMAC enables ETHRX clock, that has ETHCK_K as parent, so ETHCK_K clock are also enabled, and then the PHY reset toggles. However, this is not always the case, e.g. in case the PHY XTAL1/CLKIN clock are supplied by some other clock source than ETHCK_K or in case ETHRX clock are not supplied by ETHCK_K. In the later case, ETHCK_K would be kept disabled, while ETHRX clock would be enabled, so the PHY would not be receiving XTAL1/CLKIN clock and the reset would fail. Improve the DT by adding the PHY clock phandle into the PHY node, which then also requires moving the PHY reset GPIO specifier in the same place and that then also requires correct PHY reset GPIO timing, so add that too. A brief note regarding the timing, the datasheet says the reset should stay asserted for at least 100uS and software should wait at least 200nS after deassertion. Set both delays to 500uS which should be plenty. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 272a1a67a9adc1..31d08423a32f09 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -123,7 +123,6 @@ max-speed = <100>; phy-handle = <&phy0>; st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; mdio0 { #address-cells = <1>; @@ -132,6 +131,13 @@ phy0: ethernet-phy@1 { reg = <1>; + /* LAN8710Ai */ + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; + clocks = <&rcc ETHCK_K>; + reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <500>; interrupt-parent = <&gpioi>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; From 135adbbee4c66f89b57519633cbf8c3c35b6c4da Mon Sep 17 00:00:00 2001 From: Timon Baetz Date: Sun, 30 May 2021 10:55:44 +0000 Subject: [PATCH 247/511] ARM: dts: exynos: Disable unused camera input for I9100 As the back camera is not implemented disable the second pair of fimc child nodes as they are not functional. This prevents creating the associated /dev/videoX devices. Signed-off-by: Timon Baetz Link: https://lore.kernel.org/r/20210530105535.4165-1-timon.baetz@protonmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-i9100.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index db70f62cc08fcc..55922176807e67 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -314,7 +314,8 @@ }; &fimc_1 { - status = "okay"; + /* Back camera not implemented */ + status = "disabled"; assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; assigned-clock-parents = <&clock CLK_SCLK_MPLL>; @@ -330,7 +331,8 @@ }; &fimc_3 { - status = "okay"; + /* Back camera not implemented */ + status = "disabled"; assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; assigned-clock-parents = <&clock CLK_SCLK_MPLL>; From a927e48338c7513a1688d646a292d8a2718a0a88 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Thu, 20 May 2021 18:29:39 +0100 Subject: [PATCH 248/511] ARM: dts: qcom: Add ADM DMA + NAND definitions to ipq806x Now the ADM driver is in mainline add the appropriate definitions for it and the NAND controller to get NAND working on IPQ806x platforms, Signed-off-by: Jonathan McDowell Link: https://lore.kernel.org/r/17f88a26860f5976ad08dd3c12ea079ba474b6fd.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 67 +++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 98995ead441342..3f666021ff231d 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -185,6 +185,31 @@ bias-pull-up; }; }; + + nand_pins: nand_pins { + mux { + pins = "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; + bias-disable; + }; + + pullups { + pins = "gpio39"; + bias-pull-up; + }; + + hold { + pins = "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + bias-bus-hold; + }; + }; }; intc: interrupt-controller@2000000 { @@ -226,6 +251,26 @@ reg = <0x02098000 0x1000>, <0x02008000 0x1000>; }; + adm_dma: dma-controller@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = ; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; + + status = "disabled"; + }; + saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; @@ -403,6 +448,28 @@ status = "disabled"; }; + nand: nand-controller@1ac00000 { + compatible = "qcom,ipq806x-nand"; + reg = <0x1ac00000 0x800>; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + sata: sata@29000000 { compatible = "qcom,ipq806x-ahci", "generic-ahci"; reg = <0x29000000 0x180>; From 8e3ce01b542b02619b98536889b74600047587b5 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Thu, 20 May 2021 18:29:52 +0100 Subject: [PATCH 249/511] ARM: dts: qcom: Add tsens details to ipq806x Signed-off-by: Jonathan McDowell Link: https://lore.kernel.org/r/f7ebf47ca9e7e973e696e6b9b4fff3a2ac5da40d.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 241 ++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 3f666021ff231d..9628092217cb54 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -46,6 +46,228 @@ }; }; + thermal-zones { + tsens_tz_sensor0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 0>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 1>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 5>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 6>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 7>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor8 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 8>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor9 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 9>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor10 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 10>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + memory { device_type = "memory"; reg = <0x0 0x0>; @@ -503,6 +725,12 @@ reg = <0x00700000 0x1000>; #address-cells = <1>; #size-cells = <1>; + tsens_calib: calib@400 { + reg = <0x400 0xb>; + }; + tsens_calib_backup: calib_backup@410 { + reg = <0x410 0xb>; + }; }; gcc: clock-controller@900000 { @@ -510,6 +738,19 @@ reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor@900000 { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; }; tcsr: syscon@1a400000 { From cf18f424ad7b976af7ae98a52cde668990bbd73d Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Thu, 20 May 2021 18:30:00 +0100 Subject: [PATCH 250/511] ARM: dts: qcom: Add USB port definitions to ipq806x Signed-off-by: Jonathan McDowell Link: https://lore.kernel.org/r/ad2121defc539abdb339b23eef80a8930b5f086e.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 88 +++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 9628092217cb54..239266b55c37dc 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1026,6 +1026,94 @@ status = "disabled"; }; + hs_phy_0: phy@100f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + ss_phy_0: phy@100f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x100f8830 0x30>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb3_0: usb3@100f8800 { + compatible = "qcom,dwc3", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100f8800 0x8000>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_0_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_0: dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = ; + phys = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_1: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + ss_phy_1: phy@110f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x110f8830 0x30>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + usb3_1: usb3@110f8800 { + compatible = "qcom,dwc3", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x110f8800 0x8000>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_1_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_1: dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = ; + phys = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; regulator-name = "SDCC Power"; From 40cf5c884a965554a424797afb424ffbca4c24b3 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Thu, 20 May 2021 18:30:08 +0100 Subject: [PATCH 251/511] ARM: dts: qcom: add L2CC and RPM for IPQ8064 This adds the L2CC IPC resource and RPM devices to the IPQ8064 device tree. Tested on a Mikrotik RB3011. Signed-off-by: Jonathan McDowell Link: https://lore.kernel.org/r/a99eb2a27214b8f41070d7f1faec591e35666b21.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 239266b55c37dc..7bcf5ef9215751 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -2,6 +2,8 @@ /dts-v1/; #include +#include +#include #include #include #include @@ -753,11 +755,38 @@ }; }; + rpm: rpm@108000 { + compatible = "qcom,rpm-ipq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; + + clocks = <&gcc RPM_MSG_RAM_H_CLK>; + clock-names = "ram"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + tcsr: syscon@1a400000 { compatible = "qcom,tcsr-ipq8064", "syscon"; reg = <0x1a400000 0x100>; }; + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + }; + lcc: clock-controller@28000000 { compatible = "qcom,lcc-ipq8064"; reg = <0x28000000 0x1000>; From 2011fc7a8b5b7415d7cd885fc84ada88d37569d3 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Thu, 20 May 2021 18:30:16 +0100 Subject: [PATCH 252/511] ARM: dts: qcom: Enable NAND + USB for RB3011 Enable the NAND + USB devices for the MikroTik RB3011 platform now they're in the main IPQ806x DT. Signed-off-by: Jonathan McDowell Link: https://lore.kernel.org/r/1e5c89ba0d2491ca374f10e0446e21d0e42afd34.1621531633.git.noodles@earth.li Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts index 282b89ce3d451b..f7ea2e5dd19143 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -216,6 +216,10 @@ }; }; +&adm_dma { + status = "okay"; +}; + &gmac0 { status = "okay"; @@ -251,6 +255,39 @@ status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nandcs@0 { + compatible = "qcom,nandcs"; + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + label = "RouterBoard NAND 1 Boot"; + reg = <0x0000000 0x0800000>; + }; + + main@800000 { + label = "RouterBoard NAND 1 Main"; + reg = <0x0800000 0x7800000>; + }; + }; + }; +}; + &qcom_pinmux { buttons_pins: buttons_pins { mux { @@ -305,4 +342,25 @@ input-disable; }; }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio4"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; + + status = "okay"; }; From 58b2785dda93bba47201334c6a4f95712690bda8 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 26 May 2021 17:01:25 +0200 Subject: [PATCH 253/511] arm64: dts: qcom: ipq8074: disable USB phy by default One of the QUSB USB PHY-s has been left enabled by default, this is probably just a mistake as other USB PHY-s are disabled by default. It makes no sense to have it enabled by default as not all board implement USB ports, so disable it. Reviewed-by: Kathiravan T Signed-off-by: Robert Marko Link: https://lore.kernel.org/r/20210526150125.1816335-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index a32e5e79ab0b75..b358f95c47ab7c 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -165,6 +165,7 @@ clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; }; pcie_phy0: phy@86000 { From af260f1f7dbd336250685fa67b5d0ebe816e0907 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 27 May 2021 21:44:54 +0200 Subject: [PATCH 254/511] arm64: dts: qcom: msm8996: Rename speedbin node The speedbin value blown in the efuse is used to determine is used to determine the voltage and frequency value for different IPs, including GPU, CPUs... So it's really not a gpu specific information. This patch simply renames 'gpu_speed_bin' node to 'speedbin'. Signed-off-by: Loic Poulain Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210527194455.782108-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 859fe18aa8c7b0..e2bb98c5709191 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -425,7 +425,7 @@ bits = <1 4>; }; - gpu_speed_bin: gpu_speed_bin@133 { + speedbin_efuse: speedbin@133 { reg = <0x133 0x1>; bits = <5 3>; }; @@ -724,7 +724,7 @@ power-domains = <&mmcc GPU_GX_GDSC>; iommus = <&adreno_smmu 0>; - nvmem-cells = <&gpu_speed_bin>; + nvmem-cells = <&speedbin_efuse>; nvmem-cell-names = "speed_bin"; qcom,gpu-quirk-two-pass-use-wfi; From 15c5a08c8427ded579427908ee32ab946cb51f46 Mon Sep 17 00:00:00 2001 From: Vincent Knecht Date: Fri, 28 May 2021 13:43:45 +0200 Subject: [PATCH 255/511] arm64: dts: qcom: msm8916-alcatel-idol347: enable touchscreen Enable the MStar msg2638 touchscreen. Reviewed-by: Stephan Gerhold Signed-off-by: Vincent Knecht Link: https://lore.kernel.org/r/20210528114345.543761-1-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 540b1fa4b26034..670bd1bebd732a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -45,6 +45,24 @@ status = "okay"; }; +&blsp_i2c4 { + status = "okay"; + + touchscreen@26 { + compatible = "mstar,msg2638"; + reg = <0x26>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_reset_default>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + touchscreen-size-x = <2048>; + touchscreen-size-y = <2048>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -281,6 +299,14 @@ bias-pull-up; }; + ts_int_reset_default: ts-int-reset-default { + pins = "gpio13", "gpio100"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + usb_id_default: usb-id-default { pins = "gpio69"; function = "gpio"; From 0500629017380d4e2c1cdfd15bae411cd2a63c06 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Sat, 17 Apr 2021 09:19:51 +0300 Subject: [PATCH 256/511] arm64: dts: qcom: sm8150: Add DMA nodes With this patch, DMA has a chance of probing and doing something useful. Reviewed-by: Konrad Dybcio Reviewed-by: Vinod Koul Signed-off-by: Felipe Balbi Link: https://lore.kernel.org/r/20210417061951.2105530-3-balbi@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 70 ++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 51235a9521c243..2ebf1512471b43 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2019, Linaro Limited */ +#include #include #include #include @@ -577,6 +578,29 @@ <&sleep_clk>; }; + gpi_dma0: dma-controller@800000 { + compatible = "qcom,sm8150-gpi-dma"; + reg = <0 0x800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x00d6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -695,6 +719,29 @@ }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8150-gpi-dma"; + reg = <0 0xa00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x0616 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; @@ -795,6 +842,29 @@ }; }; + gpi_dma2: dma-controller@c00000 { + compatible = "qcom,sm8150-gpi-dma"; + reg = <0 0xc00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x07b6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_2: geniqup@cc0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00cc0000 0x0 0x6000>; From 84c856d07d80a3141bad136bb4927746d3cc418a Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 13 May 2021 11:37:05 +0530 Subject: [PATCH 257/511] arm64: dts: qcom: sm8350: use interconnect enums Add interconnect enums instead of numbers now that interconnect is in mainline. Reviewed-by: Bhupesh Sharma Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210513060705.382184-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 55f44ea454021d..b9c43c2fc2263b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -707,7 +708,7 @@ <&rpmhpd 12>; power-domain-names = "load_state", "cx", "mss"; - interconnects = <&mc_virt 0 &mc_virt 1>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; memory-region = <&pil_modem_mem>; @@ -1114,7 +1115,7 @@ <&rpmhpd 10>; power-domain-names = "load_state", "cx", "mxc"; - interconnects = <&compute_noc 1 &mc_virt 1>; + interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; memory-region = <&pil_cdsp_mem>; From 1dee9e3b0997fef7170f7ea2d8eab47d0cd334d8 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 13 May 2021 11:37:33 +0530 Subject: [PATCH 258/511] arm64: dts: qcom: sm8350: fix the node unit addresses Some node unit addresses were put wrongly in the dts, resulting in below warning when run with W=1 arch/arm64/boot/dts/qcom/sm8350.dtsi:693.34-702.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c222000: simple-bus unit address format error, expected "c263000" arch/arm64/boot/dts/qcom/sm8350.dtsi:704.34-713.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c223000: simple-bus unit address format error, expected "c265000" arch/arm64/boot/dts/qcom/sm8350.dtsi:1180.32-1185.5: Warning (simple_bus_reg): /soc@0/interconnect@90e0000: simple-bus unit address format error, expected "90c0000" Fix by correcting to the correct address as given in reg node Reviewed-by: Robert Foss Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210513060733.382420-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index b9c43c2fc2263b..0d16392bb9767b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -741,7 +741,7 @@ interrupt-controller; }; - tsens0: thermal-sensor@c222000 { + tsens0: thermal-sensor@c263000 { compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ @@ -752,7 +752,7 @@ #thermal-sensor-cells = <1>; }; - tsens1: thermal-sensor@c223000 { + tsens1: thermal-sensor@c265000 { compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ @@ -1228,7 +1228,7 @@ }; }; - dc_noc: interconnect@90e0000 { + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8350-dc-noc"; reg = <0 0x090c0000 0 0x4200>; #interconnect-cells = <1>; From caaf1f38d9a7d1abbb52743b76f63a79d4fee27a Mon Sep 17 00:00:00 2001 From: Roja Rani Yarubandi Date: Wed, 24 Mar 2021 15:48:36 +0530 Subject: [PATCH 259/511] arm64: dts: qcom: sc7180: Remove QUP-CORE ICC path We had introduced the QUP-CORE ICC path to put proxy votes from QUP wrapper on behalf of earlycon, if other users of QUP-CORE turn off this clock before the real console is probed, unclocked access to HW was seen from earlycon. With ICC sync state support proxy votes are no longer need as ICC will ensure that the default bootloader votes are not removed until all it's consumer are probed. We can safely remove ICC path for QUP-CORE clock from QUP wrapper device. Signed-off-by: Roja Rani Yarubandi Signed-off-by: Akash Asthana Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20210324101836.25272-3-rojay@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 6228ba2d851325..d8955d3cc7d097 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -768,8 +768,6 @@ #size-cells = <2>; ranges; iommus = <&apps_smmu 0x43 0x0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; - interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -1059,8 +1057,6 @@ #size-cells = <2>; ranges; iommus = <&apps_smmu 0x4c3 0x0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; - interconnect-names = "qup-core"; status = "disabled"; i2c6: i2c@a80000 { From 39441f73d91a1fd7e5594b34ac2999f31a9da246 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 22 Mar 2021 09:46:33 -0700 Subject: [PATCH 260/511] arm64: dts: qcom: sc7180: lazor: Simplify disabling of charger thermal zone Commit f73558cc83d1 ("arm64: dts: qcom: sc7180: Disable charger thermal zone for lazor") disables the charger thermal zone for specific lazor revisions due to an unsupported thermistor type. The initial idea was to disable the thermal zone for older revisions and leave it enabled for newer ones that use a supported thermistor. Finally the thermistor won't be changed on newer revisions, hence the thermal zone should be disabled for all lazor (and limozeen) revisions. Instead of disabling it per revision do it once in the shared .dtsi for lazor. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20210322094628.v4.1.I6d587e7ae72a5a47253bb95dfdc3158f8cc8a157@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 9 --------- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 9 --------- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts | 9 --------- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 9 +++++++++ 4 files changed, 9 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts index 5c997cd9006973..30e3e769d2b4f7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -14,15 +14,6 @@ compatible = "google,lazor-rev0", "qcom,sc7180"; }; -/* - * Lazor is stuffed with a 47k NTC as charger thermistor which currently is - * not supported by the PM6150 ADC driver. Disable the charger thermal zone - * to avoid using bogus temperature values. - */ -&charger_thermal { - status = "disabled"; -}; - &pp3300_hub { /* pp3300_l7c is used to power the USB hub */ /delete-property/regulator-always-on; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index d9fbcc7bc5bd48..c2ef06367baf72 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -14,15 +14,6 @@ compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; }; -/* - * Lazor is stuffed with a 47k NTC as charger thermistor which currently is - * not supported by the PM6150 ADC driver. Disable the charger thermal zone - * to avoid using bogus temperature values. - */ -&charger_thermal { - status = "disabled"; -}; - &pp3300_hub { /* pp3300_l7c is used to power the USB hub */ /delete-property/regulator-always-on; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts index ea8c2ee097416b..b474df47cd70b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts @@ -14,12 +14,3 @@ model = "Google Lazor (rev3+)"; compatible = "google,lazor", "qcom,sc7180"; }; - -/* - * Lazor is stuffed with a 47k NTC as charger thermistor which currently is - * not supported by the PM6150 ADC driver. Disable the charger thermal zone - * to avoid using bogus temperature values. - */ -&charger_thermal { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 6b10b96173e877..00535aaa43c985 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -21,6 +21,15 @@ ap_h1_spi: &spi0 {}; semtech,avg-pos-strength = <64>; }; +/* + * Lazor is stuffed with a 47k NTC as charger thermistor which currently is + * not supported by the PM6150 ADC driver. Disable the charger thermal zone + * to avoid using bogus temperature values. + */ +&charger_thermal { + status = "disabled"; +}; + ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; From ad6fc14313387d3cddf75d7ff9ae668849006e09 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 22 Mar 2021 09:46:34 -0700 Subject: [PATCH 261/511] arm64: dts: qcom: sc7180: Add pompom rev3 The only kernel visible change with respect to rev2 is that pompom rev3 changed the charger thermistor from a 47k to a 100k NTC to use a thermistor which is supported by the PM6150 ADC driver. Disable the charger thermal zone for pompom rev1 and rev2 to avoid the use of bogus temperature values from the unsupported thermistor. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20210322094628.v4.2.I4138c3edee23d1efa637eef51e841d9d2e266659@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../dts/qcom/sc7180-trogdor-pompom-r1.dts | 12 ++++++ .../dts/qcom/sc7180-trogdor-pompom-r2-lte.dts | 4 +- .../dts/qcom/sc7180-trogdor-pompom-r2.dts | 38 +++++-------------- .../dts/qcom/sc7180-trogdor-pompom-r3-lte.dts | 14 +++++++ .../dts/qcom/sc7180-trogdor-pompom-r3.dts | 15 ++++++++ .../boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 29 ++++++++++++++ 7 files changed, 83 insertions(+), 31 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d452b26d531d3e..67d04a8ebeaff9 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -53,6 +53,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts index e720e7bd0d70c4..e122a6b481ffaf 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts @@ -9,11 +9,23 @@ #include "sc7180-trogdor-pompom.dtsi" +/delete-node/ &keyboard_controller; +#include + / { model = "Google Pompom (rev1)"; compatible = "google,pompom-rev1", "qcom,sc7180"; }; +/* + * Pompom rev1 is stuffed with a 47k NTC as charger thermistor which currently + * is not supported by the PM6150 ADC driver. Disable the charger thermal zone + * to avoid using bogus temperature values. + */ +&charger_thermal { + status = "disabled"; +}; + &pp3300_hub { /* pp3300_l7c is used to power the USB hub */ /delete-property/regulator-always-on; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts index 791d496ad046c1..00e187c08eb911 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts @@ -9,6 +9,6 @@ #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Pompom (rev2+) with LTE"; - compatible = "google,pompom-sku0", "qcom,sc7180"; + model = "Google Pompom (rev2) with LTE"; + compatible = "google,pompom-rev2-sku0", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts index 984d7337da784e..4f32e6733f4c40 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts @@ -10,35 +10,15 @@ #include "sc7180-trogdor-pompom.dtsi" / { - model = "Google Pompom (rev2+)"; - compatible = "google,pompom", "qcom,sc7180"; + model = "Google Pompom (rev2)"; + compatible = "google,pompom-rev2", "qcom,sc7180"; }; -&keyboard_controller { - function-row-physmap = < - MATRIX_KEY(0x00, 0x02, 0) /* T1 */ - MATRIX_KEY(0x03, 0x02, 0) /* T2 */ - MATRIX_KEY(0x02, 0x02, 0) /* T3 */ - MATRIX_KEY(0x01, 0x02, 0) /* T4 */ - MATRIX_KEY(0x03, 0x04, 0) /* T5 */ - MATRIX_KEY(0x02, 0x04, 0) /* T6 */ - MATRIX_KEY(0x01, 0x04, 0) /* T7 */ - MATRIX_KEY(0x02, 0x09, 0) /* T8 */ - MATRIX_KEY(0x01, 0x09, 0) /* T9 */ - MATRIX_KEY(0x00, 0x04, 0) /* T10 */ - >; - linux,keymap = < - MATRIX_KEY(0x00, 0x02, KEY_BACK) - MATRIX_KEY(0x03, 0x02, KEY_REFRESH) - MATRIX_KEY(0x02, 0x02, KEY_ZOOM) - MATRIX_KEY(0x01, 0x02, KEY_SCALE) - MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) - MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) - MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) - MATRIX_KEY(0x02, 0x09, KEY_MUTE) - MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) - MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) - - CROS_STD_MAIN_KEYMAP - >; +/* + * Pompom rev2 is stuffed with a 47k NTC as charger thermistor which currently + * is not supported by the PM6150 ADC driver. Disable the charger thermal zone + * to avoid using bogus temperature values. + */ +&charger_thermal { + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts new file mode 100644 index 00000000000000..e90b73c353bb0b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pompom board device tree source + * + * Copyright 2021 Google LLC. + */ + +#include "sc7180-trogdor-pompom-r3.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pompom (rev3+) with LTE"; + compatible = "google,pompom-sku0", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts new file mode 100644 index 00000000000000..f8aac63a53ef80 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pompom board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-pompom.dtsi" + +/ { + model = "Google Pompom (rev3+)"; + compatible = "google,pompom", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 622b5f1b88a2cc..a246dbd74cc11e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -107,6 +107,35 @@ ap_ts_pen_1v8: &i2c4 { }; }; +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + &panel { compatible = "kingdisplay,kd116n21-30nv-a010"; }; From b502efda6480d7577f9f822fd450d6bc3a4ac2e6 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 22 Mar 2021 09:46:35 -0700 Subject: [PATCH 262/511] arm64: dts: qcom: sc7180: Add CoachZ rev3 CoachZ rev3 uses a 100k NTC thermistor for the charger temperatures, instead of the 47k NTC that is stuffed in earlier revisions. Add .dts files for rev3. The 47k NTC currently isn't supported by the PM6150 ADC driver. Disable the charger thermal zone for rev1 and rev2 to avoid the use of bogus temperature values. This also gets rid of the explicit DT files for rev2 and handles rev2 in the rev1 .dts instead. There was some back and forth downstream involving the 'dmic_clk_en' pin, after that was sorted out the DT for rev1 and rev2 is the same. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20210322094628.v4.3.I95b8a63103b77cab6a7cf9c150f0541db57fda98@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 ++-- .../boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts | 4 ++-- .../boot/dts/qcom/sc7180-trogdor-coachz-r1.dts | 13 +++++++++++-- ...-r2-lte.dts => sc7180-trogdor-coachz-r3-lte.dts} | 6 +++--- ...r-coachz-r2.dts => sc7180-trogdor-coachz-r3.dts} | 4 ++-- 5 files changed, 20 insertions(+), 11 deletions(-) rename arch/arm64/boot/dts/qcom/{sc7180-trogdor-coachz-r2-lte.dts => sc7180-trogdor-coachz-r3-lte.dts} (69%) rename arch/arm64/boot/dts/qcom/{sc7180-trogdor-coachz-r2.dts => sc7180-trogdor-coachz-r3.dts} (75%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 67d04a8ebeaff9..7f2d6e83b15852 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -37,8 +37,8 @@ dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts index 533c048903ea10..82dc00cc7fb9e1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts @@ -9,8 +9,8 @@ #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google CoachZ (rev1) with LTE"; - compatible = "google,coachz-rev1-sku0", "qcom,sc7180"; + model = "Google CoachZ (rev1 - 2) with LTE"; + compatible = "google,coachz-rev1-sku0", "google,coachz-rev2-sku0", "qcom,sc7180"; }; &cros_ec_proximity { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts index 1b1dbdb2a82f2d..28812334ed04b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts @@ -10,8 +10,17 @@ #include "sc7180-trogdor-coachz.dtsi" / { - model = "Google CoachZ (rev1)"; - compatible = "google,coachz-rev1", "qcom,sc7180"; + model = "Google CoachZ (rev1 - 2)"; + compatible = "google,coachz-rev1", "google,coachz-rev2", "qcom,sc7180"; +}; + +/* + * CoachZ rev1 is stuffed with a 47k NTC as charger thermistor which currently + * is not supported by the PM6150 ADC driver. Disable the charger thermal zone + * to avoid using bogus temperature values. + */ +&charger_thermal { + status = "disabled"; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts similarity index 69% rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts index 6e7745801faeba..d23409034e8cc8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts @@ -2,14 +2,14 @@ /* * Google CoachZ board device tree source * - * Copyright 2020 Google LLC. + * Copyright 2021 Google LLC. */ -#include "sc7180-trogdor-coachz-r2.dts" +#include "sc7180-trogdor-coachz-r3.dts" #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google CoachZ (rev2+) with LTE"; + model = "Google CoachZ (rev3+) with LTE"; compatible = "google,coachz-sku0", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts similarity index 75% rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts index 4f69b6ba299f1a..a02d2d57c78c50 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts @@ -2,7 +2,7 @@ /* * Google CoachZ board device tree source * - * Copyright 2020 Google LLC. + * Copyright 2021 Google LLC. */ /dts-v1/; @@ -10,6 +10,6 @@ #include "sc7180-trogdor-coachz.dtsi" / { - model = "Google CoachZ (rev2+)"; + model = "Google CoachZ (rev3+)"; compatible = "google,coachz", "qcom,sc7180"; }; From 90173a954a22414b39b566790131c7b8a969d8f8 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 27 May 2021 21:44:55 +0200 Subject: [PATCH 263/511] arm64: dts: qcom: msm8996: Add CPU opps Add the operating points capabilities of the kryo CPUs, that can be used for frequency scaling. There are two differents operating point tables, one for the big cluster and one for the LITTLE cluster. This frequency scaling support can then be used as a passive cooling device (cpufreq cooling device). Only add nominal fmax for now, since there is no dynamic control of VDD APC (s11..) which is statically set at its nominal value. Original patch link: https://patchwork.kernel.org/project/linux-arm-msm/patch/1595253740-29466-6-git-send-email-loic.poulain@linaro.org/ Signed-off-by: Loic Poulain [konrad: drop the thermals part, rebase and remove spaces within <>] Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210527194455.782108-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 234 ++++++++++++++++++++++++++ 1 file changed, 234 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index e2bb98c5709191..578902fbafd92c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -44,6 +45,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 0>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -58,6 +62,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 0>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; }; @@ -68,6 +75,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 1>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -82,6 +92,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 1>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_1>; }; @@ -121,6 +134,227 @@ }; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + /* Nominal fmax for now */ + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + /* Nominal fmax for now */ + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm-msm8996"; From 0a275a35ceab07cb622ff212c54d6866e246ac53 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 27 May 2021 21:29:58 +0200 Subject: [PATCH 264/511] arm64: dts: qcom: msm8996: Make CPUCC actually probe (and work) Fix the compatible to make the driver probe and tell the driver where to look for the "xo" clock to make sure everything works. Then we get a happy (eh, happier) 8996: somainline-sdcard:/home/konrad# cat /sys/kernel/debug/clk/pwrcl_pll/clk_rate 1152000000 Don't backport without "arm64: dts: qcom: msm8996: Add CPU opps", as the system fails to boot without consumers for these clocks. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210527192958.775434-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 578902fbafd92c..df662b0f0a4bab 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2530,9 +2530,14 @@ }; }; }; + kryocc: clock-controller@6400000 { - compatible = "qcom,apcc-msm8996"; + compatible = "qcom,msm8996-apcc"; reg = <0x06400000 0x90000>; + + clock-names = "xo"; + clocks = <&xo_board>; + #clock-cells = <1>; }; From f890f89d9a80fffbfa7ca791b78927e5b8aba869 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Thu, 15 Apr 2021 21:39:13 +0200 Subject: [PATCH 265/511] arm64: dts: qcom: msm8994-angler: Fix gpio-reserved-ranges 85-88 Reserve GPIO pins 85-88 as these aren't meant to be accessible from the application CPUs (causes reboot). Yet another fix similar to 9134586715e3, 5f8d3ab136d0, which is needed to allow angler to boot after 3edfb7bd76bd ("gpiolib: Show correct direction from the beginning"). Fixes: feeaf56ac78d ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support") Signed-off-by: Petr Vorel Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210415193913.1836153-1-petr.vorel@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts index baa55643b40fff..ffe1a9bd8f7053 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts @@ -32,3 +32,7 @@ }; }; }; + +&tlmm { + gpio-reserved-ranges = <85 4>; +}; From 5f551b5ce55575b14c26933fe9b49365ea246b3d Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 23 Mar 2021 19:55:34 -0700 Subject: [PATCH 266/511] arm64: dts: qcom: trogdor: Add no-hpd to DSI bridge node We should indicate that we're not using the HPD pin on this device, per the binding document. Otherwise if code in the future wants to enable HPD in the bridge when this property is absent we'll be wasting power powering hpd when we don't use it on trogdor boards. We didn't notice this before because the kernel driver blindly disables hpd, but that won't be true for much longer. Reviewed-by: Laurent Pinchart Reviewed-by: Douglas Anderson Cc: Laurent Pinchart Cc: Douglas Anderson Fixes: 7ec3e67307f8 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt") Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20210324025534.1837405-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index b89e6f78fd20f9..3ba34f0c9b184b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -650,6 +650,8 @@ edp_brij_i2c: &i2c2 { clocks = <&rpmhcc RPMH_LN_BB_CLK3>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>; From eb9b7bfd5954f5f6ac4d57313541dd0294660aad Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 24 Mar 2021 23:48:36 +0300 Subject: [PATCH 267/511] arm64: dts: qcom: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210324204836.29668-8-Sergey.Semin@baikalelectronics.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 51e17094d7b18e..068692350e000b 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -1063,7 +1063,7 @@ status = "okay"; extcon = <&usb2_id>; - dwc3@7600000 { + usb@7600000 { extcon = <&usb2_id>; dr_mode = "otg"; maximum-speed = "high-speed"; @@ -1074,7 +1074,7 @@ status = "okay"; extcon = <&usb3_id>; - dwc3@6a00000 { + usb@6a00000 { extcon = <&usb3_id>; dr_mode = "otg"; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index b358f95c47ab7c..7542d1eee62cd9 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -428,7 +428,7 @@ resets = <&gcc GCC_USB0_BCR>; status = "disabled"; - dwc_0: dwc3@8a00000 { + dwc_0: usb@8a00000 { compatible = "snps,dwc3"; reg = <0x8a00000 0xcd00>; interrupts = ; @@ -469,7 +469,7 @@ resets = <&gcc GCC_USB1_BCR>; status = "disabled"; - dwc_1: dwc3@8c00000 { + dwc_1: usb@8c00000 { compatible = "snps,dwc3"; reg = <0x8c00000 0xcd00>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index df662b0f0a4bab..9d4f22e625f5c1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2566,7 +2566,7 @@ power-domains = <&gcc USB30_GDSC>; status = "disabled"; - dwc3@6a00000 { + usb@6a00000 { compatible = "snps,dwc3"; reg = <0x06a00000 0xcc00>; interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; @@ -2873,7 +2873,7 @@ qcom,select-utmi-as-pipe-clk; status = "disabled"; - dwc3@7600000 { + usb@7600000 { compatible = "snps,dwc3"; reg = <0x07600000 0xcc00>; interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index e9d3ce29937c4e..6f294f9c0cdf15 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1964,7 +1964,7 @@ resets = <&gcc GCC_USB_30_BCR>; - usb3_dwc3: dwc3@a800000 { + usb3_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0x0a800000 0xcd00>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index a80c578484ba3e..f8a55307b8554a 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -337,7 +337,7 @@ &usb3 { status = "okay"; - dwc3@7580000 { + usb@7580000 { dr_mode = "host"; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 339790ba585de9..9c4be020d5689a 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -544,7 +544,7 @@ assigned-clock-rates = <19200000>, <200000000>; status = "disabled"; - dwc3@7580000 { + usb@7580000 { compatible = "snps,dwc3"; reg = <0x07580000 0xcd00>; interrupts = ; @@ -573,7 +573,7 @@ assigned-clock-rates = <19200000>, <133333333>; status = "disabled"; - dwc3@78c0000 { + usb@78c0000 { compatible = "snps,dwc3"; reg = <0x078c0000 0xcc00>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d8955d3cc7d097..e0822f6ec150fc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2856,7 +2856,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; interconnect-names = "usb-ddr", "apps-usb"; - usb_1_dwc3: dwc3@a600000 { + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a86fe71a66d19..1796ae8372be24 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3781,7 +3781,7 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; - usb_1_dwc3: dwc3@a600000 { + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; @@ -3829,7 +3829,7 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; interconnect-names = "usb-ddr", "apps-usb"; - usb_2_dwc3: dwc3@a800000 { + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2ebf1512471b43..142cf786c6cf16 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2338,7 +2338,7 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; - usb_1_dwc3: dwc3@a600000 { + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; From c0dcfe6a784fdf7fcc0fdc74bfbb06e9f77de964 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 24 Mar 2021 16:14:24 -0700 Subject: [PATCH 268/511] arm64: dts: qcom: c630: Add no-hpd to DSI bridge node We should indicate that we're not using the HPD pin on this device, per the binding document. Otherwise if code in the future wants to enable HPD in the bridge when this property is absent we'll be enabling HPD when it isn't supposed to be used. Presumably this board isn't using hpd on the bridge. Reviewed-by: Douglas Anderson Cc: Laurent Pinchart Cc: Douglas Anderson Cc: Steev Klimaszewski Fixes: 956e9c85f47b ("arm64: dts: qcom: c630: Define eDP bridge and panel") Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20210324231424.2890039-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 140db2d5ba3173..c2a709a384e9ee 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -376,6 +376,8 @@ clocks = <&sn65dsi86_refclk>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>; From dc5d91250ae6b810bc8d599d8d6590a06a4ce84a Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 29 Mar 2021 15:00:51 +0300 Subject: [PATCH 269/511] arm64: dts: qcom: sm8250: fix display nodes Use sm8250 compatibles instead of sdm845 compatibles Reviewed-by: Stephen Boyd Signed-off-by: Jonathan Marek Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210329120051.3401567-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6f2..75f9476109e69c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2370,7 +2370,7 @@ }; mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; + compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -2402,7 +2402,7 @@ ranges; mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; + compatible = "qcom,sm8250-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; From c1124180eb9883891ad2acef89c9d17d6190eab4 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 15 Mar 2021 10:38:54 -0700 Subject: [PATCH 270/511] arm64: dts: qcom: sc7180: Fix sc7180-qmp-usb3-dp-phy reg sizes As per Dmitry Baryshkov [1]: a) The 2nd "reg" should be 0x3c because "Offset 0x38 is USB3_DP_COM_REVISION_ID3 (not used by the current driver though)." b) The 3rd "reg" "is a serdes region and qmp_v3_dp_serdes_tbl contains registers 0x148 and 0x154." I think because the 3rd "reg" is a serdes region we should just use the same size as the 1st "reg"? [1] https://lore.kernel.org/r/ee5695bb-a603-0dd5-7a7f-695e919b1af1@linaro.org Reviewed-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Cc: Stephen Boyd Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Rob Clark Fixes: 58fd7ae621e7 ("arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy") Reported-by: Dmitry Baryshkov Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20210315103836.1.I9a97120319d43b42353aeac4d348624d60687df7@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e0822f6ec150fc..295844e90dd532 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2750,8 +2750,8 @@ usb_1_qmpphy: phy-wrapper@88e9000 { compatible = "qcom,sc7180-qmp-usb3-dp-phy"; reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x38>, - <0 0x088ea000 0 0x40>; + <0 0x088e8000 0 0x3c>, + <0 0x088ea000 0 0x18c>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; From 822c8f2a2f2c0dccf0cb7edfd9c1f4276c4f4b2a Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 14 Apr 2021 11:10:26 -0700 Subject: [PATCH 271/511] arm64: dts: qcom: sc7180: coachz: Add thermal config for skin temperature Add ADC and thermal monitor configuration for skin temperature, plus a thermal zone that monitors the skin temperature and uses the big cores as cooling devices. CoachZ rev1 is stuffed with an incompatible thermistor for the skin temperature, disable the thermal zone for rev1 to avoid the use of bogus temperature values. Reviewed-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20210414111007.v1.1.I1a438604a79025307f177347d45815987b105cb5@changeid Signed-off-by: Bjorn Andersson --- .../dts/qcom/sc7180-trogdor-coachz-r1.dts | 9 +++ .../boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 63 +++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts index 28812334ed04b1..21b516e0694a4b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts @@ -23,6 +23,15 @@ status = "disabled"; }; +/* + * CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature, + * which currently is not supported by the PM6150 ADC driver. Disable the + * skin temperature thermal zone to avoid using bogus temperature values. + */ +&skin_temp_thermal { + status = "disabled"; +}; + &tlmm { gpio-line-names = "HUB_RST_L", "AP_RAM_ID0", diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 4c6e433c8226a3..8c1146c5bdfee0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -25,6 +25,50 @@ ap_h1_spi: &spi0 {}; IOVDD-supply = <&pp1800_l15a>; #sound-dai-cells = <0>; }; + + thermal-zones { + skin_temp_thermal: skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&pm6150_adc_tm 1>; + sustainable-power = <814>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <42000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <45000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <60000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; &ap_spi_fp { @@ -77,6 +121,25 @@ ap_ts_pen_1v8: &i2c4 { compatible = "boe,nv110wtm-n61"; }; +&pm6150_adc { + skin-temp-thermistor@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + skin-temp-thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pp3300_dx_edp { gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; From 7dbd121a2c587cfbe0a4382e508447292b52cdb1 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 10 Apr 2021 07:34:39 +0530 Subject: [PATCH 272/511] arm64: dts: qcom: sc7280: Add cpufreq hw node Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SC7280 SoCs. Reviewed-by: Matthias Kaehlcke Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/1618020280-5470-2-git-send-email-tdas@codeaurora.org [bjorn: Dropped reg-names] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 326f629b4789fc..0cc7e104f9503f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -71,6 +71,7 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -90,6 +91,7 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -106,6 +108,7 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -122,6 +125,7 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -138,6 +142,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -154,6 +159,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -170,6 +176,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -186,6 +193,7 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -1147,6 +1155,16 @@ #clock-cells = <1>; }; }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,cpufreq-epss"; + reg = <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>, + <0 0x18593000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <1>; + }; }; thermal_zones: thermal-zones { From 422a295221bba81301a87b002b02bb63444edabc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 10 Apr 2021 07:34:40 +0530 Subject: [PATCH 273/511] arm64: dts: qcom: sc7280: Add clock controller nodes Add support for the video, gpu, display, lpass clock controller device nodes for SC7280 SoC. Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/1618020280-5470-3-git-send-email-tdas@codeaurora.org [bjorn: Dropped includes, as they are not present in v5.13-rc1] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 54 ++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0cc7e104f9503f..13054a182d2bd0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -333,6 +333,31 @@ }; }; + lpasscc: lpasscc@3000000 { + compatible = "qcom,sc7280-lpasscc"; + reg = <0 0x03000000 0 0x40>, + <0 0x03c04000 0 0x4>, + <0 0x03389000 0 0x24>; + reg-names = "qdsp6ss", "top_cc", "cc"; + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sc7280-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, @@ -829,6 +854,35 @@ interrupts = ; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sc7280-videocc"; + reg = <0 0xaaf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc7280-dispcc"; + reg = <0 0xaf00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <0>, <0>, <0>, <0>, <0>, <0>; + clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; From d4282fb4f8f9683711ae6c076da16aa8e675fdbd Mon Sep 17 00:00:00 2001 From: Sujit Kautkar Date: Fri, 14 May 2021 11:34:34 -0700 Subject: [PATCH 274/511] arm64: dts: qcom: sc7180: Move rmtfs memory region Move rmtfs memory region so that it does not overlap with system RAM (kernel data) when KAsan is enabled. This puts rmtfs right after mba_mem which is not supposed to increase beyond 0x94600000 Reviewed-by: Sibi Sankar Signed-off-by: Sujit Kautkar Link: https://lore.kernel.org/r/20210514113430.1.Ic2d032cd80424af229bb95e2c67dd4de1a70cb0c@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index d2a867ca493291..52899dd4feb021 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -46,7 +46,7 @@ /* Increase the size from 2MB to 8MB */ &rmtfs_mem { - reg = <0x0 0x84400000 0x0 0x800000>; + reg = <0x0 0x94600000 0x0 0x800000>; }; / { From a1dff44b354c0e2721aeae075a287d07daf1c76b Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 27 Apr 2021 13:03:40 +0530 Subject: [PATCH 275/511] dt-bindings: mailbox: Add WPSS client index to IPCC Add WPSS remote processor client index to Inter-Processor Communication Controller (IPCC) block. Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/1619508824-14413-2-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/mailbox/qcom-ipcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h index 4c23eefed5f30f..eb91a6c05b7139 100644 --- a/include/dt-bindings/mailbox/qcom-ipcc.h +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -29,5 +29,6 @@ #define IPCC_CLIENT_PCIE1 14 #define IPCC_CLIENT_PCIE2 15 #define IPCC_CLIENT_SPSS 16 +#define IPCC_CLIENT_WPSS 24 #endif From c3bbe55c942d2a1abc9ec5d8d3a04de303cf75c9 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 27 Apr 2021 13:03:44 +0530 Subject: [PATCH 276/511] arm64: dts: qcom: sc7280: Add nodes to boot WPSS Add miscellaneous nodes to boot the Wireless Processor Subsystem (WPSS) on SC7280 SoCs. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/1619508824-14413-6-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 138 +++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 13054a182d2bd0..0b6f119dce1055 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include @@ -52,6 +54,11 @@ no-map; }; + smem_mem: memory@80900000 { + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + }; + cpucp_mem: memory@80b00000 { no-map; reg = <0x0 0x80b00000 0x0 0x100000>; @@ -268,6 +275,119 @@ }; }; + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -333,6 +453,12 @@ }; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex", "syscon"; + reg = <0 0x01f40000 0 0x40000>; + #hwlock-cells = <1>; + }; + lpasscc: lpasscc@3000000 { compatible = "qcom,sc7280-lpasscc"; reg = <0 0x03000000 0 0x40>, @@ -896,6 +1022,12 @@ interrupt-controller; }; + pdc_reset: reset-controller@b5e0000 { + compatible = "qcom,sc7280-pdc-global"; + reg = <0 0x0b5e0000 0 0x20000>; + #reset-cells = <1>; + }; + tsens0: thermal-sensor@c263000 { compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ @@ -918,6 +1050,12 @@ #thermal-sensor-cells = <1>; }; + aoss_reset: reset-controller@c2a0000 { + compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; + reg = <0 0x0c2a0000 0 0x31000>; + #reset-cells = <1>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sc7280-aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; From 17bf8dfa2ac7a49e09e6d1a29bd3ac881e947386 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 29 Apr 2021 11:10:26 +0530 Subject: [PATCH 277/511] dt-bindings: arm: qcom: Document google,senor board Document the google,senor board based on sc7280 SoC Acked-by: Rob Herring Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/1619674827-26650-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 9b27e991bddcef..2babb95de35448 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -178,6 +178,7 @@ properties: - items: - enum: - qcom,sc7280-idp + - google,senor - const: qcom,sc7280 - items: From 9d6e639cbaa1f27fedccb456dd2f70ecc39b5aca Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 29 Apr 2021 11:10:27 +0530 Subject: [PATCH 278/511] arm64: dts: qcom: sc7280: Add "google,senor" to the compatible The sc7280 IDP board is also called senor in the Chrome OS builds. Add the "google,senor" compatible so coreboot/depthcharge knows what device tree blob to pick Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/1619674827-26650-2-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 704fb9a88a61b5..3900cfc0956292 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -19,7 +19,7 @@ / { model = "Qualcomm Technologies, Inc. sc7280 IDP platform"; - compatible = "qcom,sc7280-idp", "qcom,sc7280"; + compatible = "qcom,sc7280-idp", "google,senor", "qcom,sc7280"; aliases { serial0 = &uart5; From 28b9a4679d8074512f12967497c161b992eb3b75 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Apr 2021 17:00:12 +0200 Subject: [PATCH 279/511] ARM: dts: stm32: Remove extra size-cells on dhcom-pdk2 Fix make dtbs_check warning: arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml: gpio-keys-polled: '#address-cells' is a dependency of '#size-cells' arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml: gpio-keys: '#address-cells' is a dependency of '#size-cells' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 5523f4138fd695..0fbf9913e8df7e 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -34,7 +34,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #size-cells = <0>; poll-interval = <20>; /* @@ -60,7 +59,6 @@ gpio-keys { compatible = "gpio-keys"; - #size-cells = <0>; button-1 { label = "TA2-GPIO-B"; From 4b5fadef3fc2ab8863ffdf31eed6a745b1bf6e61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Apr 2021 17:00:13 +0200 Subject: [PATCH 280/511] ARM: dts: stm32: Fix touchscreen node on dhcom-pdk2 Fix make dtbs_check warning: arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml:0:0: /soc/i2c@40015000/polytouch@38: failed to match any schema with compatible: ['edt,edt-ft5x06'] Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 0fbf9913e8df7e..b8c8f0b284c314 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -182,8 +182,8 @@ }; - polytouch@38 { - compatible = "edt,edt-ft5x06"; + touchscreen@38 { + compatible = "edt,edt-ft5406"; reg = <0x38>; interrupt-parent = <&gpiog>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ From c90b2c4fc9c3f5660a359377aabc1998456ae5b1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 26 Apr 2021 12:45:36 +0200 Subject: [PATCH 281/511] ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151 Configure qspi's mdma from buffer transfer (max 128 bytes) to block transfer (max 64K bytes). mtd_speedtest shows that write throughtput increases : - from 734 to 782 KiB/s (~6.5%) with s25fl512s SPI-NOR. - from 4848 to 5319 KiB/s (~9.72%) with Micron SPI-NAND. Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index fcd3230c469b7e..3f74d13995acd1 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1369,8 +1369,8 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = ; - dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>, - <&mdma1 22 0x2 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, + <&mdma1 22 0x2 0x10100008 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; From a270a2b24de5be0480136cbbd7805b9134762b97 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 18 May 2021 09:58:33 +0200 Subject: [PATCH 282/511] arm64: dts: meson: set 128bytes FIFO size on uart A The first UART controller in "Everything-Else" power domain, usually used for Bluetooth HCI has 128bytes FIFO depth. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210518075833.3736038-4-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 895c43c7af9f7e..3f5254eeb47b1e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1871,6 +1871,7 @@ status = "disabled"; clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; clock-names = "xtal", "pclk", "baud"; + fifo-size = <128>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 793d48f7239064..00c6f53290d438 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2317,6 +2317,7 @@ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; + fifo-size = <128>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 3d00404aae0f4a..6b457b2c30a4bc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -301,6 +301,7 @@ reg = <0x0 0x84c0 0x0 0x18>; interrupts = ; status = "disabled"; + fifo-size = <128>; }; uart_B: serial@84dc { From 0171b07373cc8c2815ca5fa79a7308fdefa54ca4 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Sat, 10 Apr 2021 21:35:21 +0200 Subject: [PATCH 283/511] ARM: dts: stm32: fix stm32mp157c-odyssey card detect pin MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The microSD card detect pin is physically connected to the MPU pin PI3. The Device Tree configuration of the card detect pin was wrong—it was set to pin PB7 instead. If such configuration was used, the kernel would hang on “Waiting for root device” when booting from a microSD card. Signed-off-by: Grzegorz Szymaszek Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-odyssey.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts index a7ffec8f151649..be1dd5e9e7443f 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -64,7 +64,7 @@ pinctrl-0 = <&sdmmc1_b4_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,neg-edge; bus-width = <4>; From bf24b91f4baf7e421c770a1d9c7d381b10206ac9 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:25 +0200 Subject: [PATCH 284/511] ARM: dts: stm32: fix gpio-keys node on STM32 MCU boards Fix following warning observed with "make dtbs_check W=1" command. It concerns f429 eval and disco boards, f769 disco board. Warning (unit_address_vs_reg): /gpio_keys/button@0: node has a unit name, but no reg or ranges property Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32429i-eval.dts | 8 +++----- arch/arm/boot/dts/stm32746g-eval.dts | 6 ++---- arch/arm/boot/dts/stm32f429-disco.dts | 6 ++---- arch/arm/boot/dts/stm32f469-disco.dts | 6 ++---- arch/arm/boot/dts/stm32f769-disco.dts | 6 ++---- 5 files changed, 11 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 7e10ae744c9d14..9ac1ffe53413c2 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -119,17 +119,15 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Wake up"; linux,code = ; gpios = <&gpioa 0 0>; }; - button@1 { + button-1 { label = "Tamper"; linux,code = ; gpios = <&gpioc 13 0>; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index ca8c192449ee9d..327613fd9666c1 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -81,12 +81,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Wake up"; linux,code = ; gpios = <&gpioc 13 0>; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 3dc068b91ca159..075ac57d0bf4af 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -81,12 +81,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 0>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 2e1b3bbbe4b5b8..8c982ae79f432f 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -104,12 +104,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index 0ce7fbc20fa4dc..be943b70198063 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -75,12 +75,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; From e4b948415a89a219d13e454011cdcf9e63ecc529 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:26 +0200 Subject: [PATCH 285/511] ARM: dts: stm32: fix RCC node name on stm32f429 MCU This prevent warning observed with "make dtbs_check W=1" Warning (simple_bus_reg): /soc/rcc@40023810: simple-bus unit address format error, expected "40023800" Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index f6530d724d0043..41e0087bdbf9dd 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -709,7 +709,7 @@ status = "disabled"; }; - rcc: rcc@40023810 { + rcc: rcc@40023800 { #reset-cells = <1>; #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; From 2388f14d8747f8304e26ee870790e188c9431efd Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:27 +0200 Subject: [PATCH 286/511] ARM: dts: stm32: fix timer nodes on STM32 MCU to prevent warnings Prevent warning seen with "make dtbs_check W=1" command: Warning (avoid_unnecessary_addr_size): /soc/timers@40001c00: unnecessary address-cells/size-cells without "ranges" or child "reg" property Reviewed-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 8 -------- arch/arm/boot/dts/stm32f746.dtsi | 8 -------- arch/arm/boot/dts/stm32h743.dtsi | 4 ---- 3 files changed, 20 deletions(-) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 41e0087bdbf9dd..8748d58502980e 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -283,8 +283,6 @@ }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; @@ -299,8 +297,6 @@ }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; @@ -633,8 +629,6 @@ }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; @@ -649,8 +643,6 @@ }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index e1df603fc98168..72c1b76684b6a9 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -265,8 +265,6 @@ }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; @@ -281,8 +279,6 @@ }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; @@ -531,8 +527,6 @@ }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; @@ -547,8 +541,6 @@ }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 05ecdf9ff03a44..6e42ca2dada2c6 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -485,8 +485,6 @@ }; lptimer4: timer@58002c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002c00 0x400>; clocks = <&rcc LPTIM4_CK>; @@ -501,8 +499,6 @@ }; lptimer5: timer@58003000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58003000 0x400>; clocks = <&rcc LPTIM5_CK>; From 5f459cb0d67d6df6f74eac253ea10de9e9986812 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 1 Jun 2021 05:31:16 +0300 Subject: [PATCH 287/511] dt-bindings: soc: tegra-pmc: Document core power domain All NVIDIA Tegra SoCs have a core power domain where majority of hardware blocks reside. Document the new core power domain properties. Reviewed-by: Rob Herring Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 43fd2f8927d036..0afec83cc72327 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -301,6 +301,33 @@ patternProperties: additionalProperties: false + core-domain: + type: object + description: | + The vast majority of hardware blocks of Tegra SoC belong to a + Core power domain, which has a dedicated voltage rail that powers + the blocks. + + properties: + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + required: + - operating-points-v2 + - "#power-domain-cells" + + additionalProperties: false + + core-supply: + description: + Phandle to voltage regulator connected to the SoC Core power rail. + required: - compatible - reg @@ -325,6 +352,7 @@ examples: tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x7000e400 0x400>; + core-supply = <®ulator>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; @@ -338,17 +366,24 @@ examples: nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + powergates { pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, <&tegra_car TEGRA210_CLK_APB2APE>; resets = <&tegra_car 198>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; pd_xusbss: xusba { clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; }; From ad7395c7482d34b63b2d8547acafc796e331319a Mon Sep 17 00:00:00 2001 From: Judy Hsiao Date: Tue, 1 Jun 2021 10:21:17 +0800 Subject: [PATCH 288/511] arm64: dts: qcom: sc7180: add label for secondary mi2s Adds label for MI2S secondary block to allow follower projects to override for the four speaker support which uses I2S SD1 line on gpio52 pin. Reviewed-by: Stephen Boyd Signed-off-by: Judy Hsiao Link: https://lore.kernel.org/r/20210601022117.4071117-1-judyhsiao@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 3ba34f0c9b184b..a4cbdc36c306eb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -769,7 +769,7 @@ hp_i2c: &i2c9 { qcom,capture-sd-lines = <0>; }; - mi2s@1 { + secondary_mi2s: mi2s@1 { reg = ; qcom,playback-sd-lines = <0>; }; From 253adffb0e98eaf6da2e7cf73ae68695e21f2f3c Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Fri, 25 Oct 2019 10:42:10 +0200 Subject: [PATCH 289/511] ARM: dts: at91: sama5d4: fix pinctrl muxing Fix pinctrl muxing, PD28, PD29 and PD31 can be muxed to peripheral A. It allows to use SCK0, SCK1 and SPI0_NPCS2 signals. Signed-off-by: Ludovic Desroches Fixes: 679f8d92bb01 ("ARM: at91/dt: sama5d4: add pioD pin mux mask and enable pioD") Cc: stable@vger.kernel.org # v4.4+ Reviewed-by: Claudiu Beznea Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20191025084210.14726-1-ludovic.desroches@microchip.com --- arch/arm/boot/dts/sama5d4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 05c55875835d54..f70a8528b9598c 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -787,7 +787,7 @@ 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ - 0x0003ff00 0x8002a800 0x00000000 /* pioD */ + 0xb003ff00 0x8002a800 0x00000000 /* pioD */ 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ >; From 946437cfb0d2eff41352458847e3a01ad0f1b460 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Tue, 1 Jun 2021 12:00:14 +0800 Subject: [PATCH 290/511] arm64: dts: mt8183: remove syscon from smi_common node We don't need to register smi_common as syscon. Also add required property power-domains for this node. Signed-off-by: Hsin-Yi Wang Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210601040014.2970805-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index c5e822b6b77a3f..e074c0d402ff72 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1263,13 +1263,14 @@ }; smi_common: smi@14019000 { - compatible = "mediatek,mt8183-smi-common", "syscon"; + compatible = "mediatek,mt8183-smi-common"; reg = <0 0x14019000 0 0x1000>; clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_GALS_COMM0>, <&mmsys CLK_MM_GALS_COMM1>; clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; }; imgsys: syscon@15020000 { From 7e149fd8349034431852fb1f6db0229da935c3fe Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Thu, 27 May 2021 15:55:56 +0800 Subject: [PATCH 291/511] arm64: dts: mt8183: add supply name for eeprom Add supplies for eeprom for mt8183 boards. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210527075556.1709140-5-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi index b442e38a3156dc..28966a65391b09 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -88,11 +88,13 @@ pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; eeprom@58 { compatible = "atmel,24c32"; reg = <0x58>; pagesize = <32>; + vcc-supply = <&mt6358_vcama2_reg>; }; }; @@ -101,11 +103,13 @@ pinctrl-0 = <&i2c4_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; eeprom@54 { compatible = "atmel,24c32"; reg = <0x54>; pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index 2f5234a16eadf0..3aa79403c0c2c2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -62,11 +62,13 @@ pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; eeprom@58 { compatible = "atmel,24c64"; reg = <0x58>; pagesize = <32>; + vcc-supply = <&mt6358_vcamio_reg>; }; }; @@ -75,11 +77,13 @@ pinctrl-0 = <&i2c4_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; eeprom@54 { compatible = "atmel,24c64"; reg = <0x54>; pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi index fbc471ccf805fb..30c183c96a54cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -71,11 +71,13 @@ pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; eeprom@58 { compatible = "atmel,24c32"; reg = <0x58>; pagesize = <32>; + vcc-supply = <&mt6358_vcama2_reg>; }; }; @@ -84,11 +86,13 @@ pinctrl-0 = <&i2c4_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; eeprom@54 { compatible = "atmel,24c32"; reg = <0x54>; pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; }; }; From d318da52658088cbde66263213dbc7debc1a9f1d Mon Sep 17 00:00:00 2001 From: Steven Lee Date: Tue, 25 May 2021 13:53:06 +0800 Subject: [PATCH 292/511] ARM: dts: aspeed-g6: Add pinctrl settings AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces. Currently, only SGPIO master 1 and SGPIO slve 1 in the pinctrl dtsi. SGPIO master 2 and slave 2 should be added in pinctrl dtsi as well. Signed-off-by: Steven Lee Reviewed-by: Andrew Jeffery Reviewed-by: Linus Walleij Acked-by: Joel Stanley Link: https://lore.kernel.org/r/20210525055308.31069-3-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 7028e21bdd9808..7e90d713f5e58e 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -862,11 +862,21 @@ groups = "SGPM1"; }; + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; + pinctrl_sgps1_default: sgps1_default { function = "SGPS1"; groups = "SGPS1"; }; + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; + pinctrl_sioonctrl_default: sioonctrl_default { function = "SIOONCTRL"; groups = "SIOONCTRL"; From 239566b032f3accb1b39c764697751857ad8bb37 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 26 May 2021 14:42:20 +0930 Subject: [PATCH 293/511] ARM: dts: aspeed: Set earlycon boot argument Most of the aspeed boards have copied the 'earlyprink' string in the bootargs. However, there's no earlyprink driver configured in the defconfigs, so this does nothing. A combination of setting stdout in the chosen node and adding earlycon to bootargs causes early serial output to appear early. This changes all boards to use this option. The console=ttyS4,115200 option is still required, as this is used by the run time uart driver. Signed-off-by: Joel Stanley Acked-by: Andrew Jeffery Acked-by: Alexander Filippov Link: https://lore.kernel.org/r/20210526051220.136432-1-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-swift.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts | 2 +- 29 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 8bec21ed0de536..583a241f115188 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -13,7 +13,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 6aeb47c44eba27..79d17841b3d700 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -34,7 +34,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; leds { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 8f5ec22e51c25f..bbf8d548397bbe 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -9,7 +9,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts index c2ece0b91885e1..3395de96ee1162 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts index 2c29ac037d3253..7c6af7f226e75c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index dcab6e78dfa410..33e413ca07e4a2 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -15,7 +15,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 5ef88c377358bc..01dace8f5e5f7e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -55,7 +55,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index 2fb8b147f489a6..90a3f485c67a98 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -280,7 +280,7 @@ chosen { stdout-path = &uart1; - bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk"; + bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlycon"; }; ast-adc-hwmon { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 7b4b2b126ad849..b6b16356f571a2 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -37,7 +37,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts index 07593897fc9a1c..1752f3250e44d9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts index 80c92e065a10a1..5a98a19f445e03 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory { diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts index 6e9baf3bba5310..d5b7d28cda887c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts index c29e5f4d86adb5..8f543cca7c21f1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts @@ -27,7 +27,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts index 084c455ad4cbfd..bcc1820f5c0733 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts @@ -27,7 +27,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts index 73319917cb743d..3ef8358ff764a0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts index 42b37a20424176..c0847636f20b90 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index 15c1f0ac81dcd8..a52a289cee85ec 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -57,7 +57,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts index 8503152faaf085..7d38d121ec6da9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts index 91dced7e784989..3d4bdad27c2dcc 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index eb4e93a57ff443..cd660c1ff3f503 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index fd2e014dae7526..084f54866f386e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -9,7 +9,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts index d56b5ed09b3706..4816486c0c9eb8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index c1478d2db6026c..e863ec08897071 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -13,7 +13,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; + bootargs = "console=ttyS4,115200n8 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index 01074b6e3e03e6..328ef472c479d9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 85d58a63ae9050..230f3584bcab01 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 4bcc82046362b1..7ae4ea0d2931bf 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -17,7 +17,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts index 03c161493ffc44..61bc74b423cf3e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts @@ -14,7 +14,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts index a68ff0675c28a0..9605e53f5bbfc0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -28,7 +28,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts index bc16ad2b5c80a3..50f3c6a5c0c8df 100644 --- a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts +++ b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory@80000000 { From 9e8cf4b4f93ff6bab6ff0eefd09c1fe55b17152f Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Mon, 17 May 2021 11:00:34 +0700 Subject: [PATCH 294/511] ARM: dts: aspeed: mtjade: Enable OCP card support via NC-SI Enable OCP card support on Ampere's Mt. Jade BMC. Signed-off-by: Quan Nguyen Signed-off-by: Phong Vo Signed-off-by: Thang Q. Nguyen Link: https://lore.kernel.org/r/20210517040036.13667-2-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index bbf8d548397bbe..0a26fad51ee61b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -332,6 +332,16 @@ status = "okay"; }; +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + &mac1 { status = "okay"; pinctrl-names = "default"; @@ -540,7 +550,8 @@ /*O0-O7*/ "","","","","","","","", /*P0-P7*/ "","","","","","","","", /*Q0-Q7*/ "","","","","","UID_BUTTON","","", - /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","", + /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", + "OCP_MAIN_PWREN","RESET_BUTTON","","", /*S0-S7*/ "","","","","","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", From 73a89a96f55d70765fa885659e2fda5e0b5db0b0 Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Mon, 17 May 2021 11:00:35 +0700 Subject: [PATCH 295/511] ARM: dts: aspeed: mtjade: Add PSU support Enable PSU support on Ampere's Mt. Jade BMC. Signed-off-by: Quan Nguyen Signed-off-by: Phong Vo Signed-off-by: Thang Q. Nguyen Link: https://lore.kernel.org/r/20210517040036.13667-3-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 42 ++++++++++++++++++- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 0a26fad51ee61b..a1178d5b585935 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -110,6 +110,30 @@ linux,code = ; }; + psu1_vin_good { + label = "PSU1_VIN_GOOD"; + gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu2_vin_good { + label = "PSU2_VIN_GOOD"; + gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu1_present { + label = "PSU1_PRESENT"; + gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu2_present { + label = "PSU2_PRESENT"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; gpioA0mux: mux-controller { @@ -436,6 +460,19 @@ status = "okay"; }; +&i2c10 { + status = "okay"; + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + }; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; +}; + &gfx { status = "okay"; memory-region = <&gfx_memory>; @@ -539,8 +576,9 @@ "S1_DDR_SAVE","","", /*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","", "","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","S1_BMC_SPECIAL_BOOT","","","","","", + /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", + /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", + "","","","","", /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","", "","","","", /*K0-K7*/ "","","","","","","","", From 959ff7f6f42459cd91d1e8b31828d557fd4ee872 Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Mon, 17 May 2021 11:00:36 +0700 Subject: [PATCH 296/511] ARM: dts: aspeed: mtjade: switch to 64MB flash layout As the 32MB flash layout will soon be exhausted, switch to 64MB layout. Signed-off-by: Quan Nguyen Signed-off-by: Phong Vo Signed-off-by: Thang Q. Nguyen Link: https://lore.kernel.org/r/20210517040036.13667-4-quan@os.amperecomputing.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index a1178d5b585935..57b0c45a2298fb 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -304,7 +304,7 @@ m25p,fast-read; label = "bmc"; /* spi-max-frequency = <50000000>; */ -#include "openbmc-flash-layout.dtsi" +#include "openbmc-flash-layout-64.dtsi" }; }; From 8dec60e7b8d0cc1ca0001e64b17e339ff5158703 Mon Sep 17 00:00:00 2001 From: Troy Lee Date: Tue, 16 Mar 2021 08:59:32 +0000 Subject: [PATCH 297/511] ARM: dts: aspeed: Grow u-boot partition 64MiB OpenBMC flash layout Aspeed AST2600 u-boot requires 600KiB+ flash space. Sharing the same openbmc-flash-layout-64.dtsi requires to resize the flash partition. The updated flash layout as follows: - u-boot: 896 KiB - u-boot-env: 128 KiB - kernel: 9MiB - rofs: 32 MiB - rwfs: 22 MiB Signed-off-by: Troy Lee Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20210316085932.2601-1-troy_lee@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 32 +------------------ .../arm/boot/dts/openbmc-flash-layout-64.dtsi | 18 +++++------ 2 files changed, 10 insertions(+), 40 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index c670f3a45fbb36..b7eb552640cbf3 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -163,37 +163,7 @@ m25p,fast-read; label = "bmc"; spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0xe0000>; // 896KB - label = "u-boot"; - }; - - u-boot-env@e0000 { - reg = <0xe0000 0x20000>; // 128KB - label = "u-boot-env"; - }; - - kernel@100000 { - reg = <0x100000 0x900000>; // 9MB - label = "kernel"; - }; - - rofs@a00000 { - reg = <0xa00000 0x2000000>; // 32MB - label = "rofs"; - }; - - rwfs@6000000 { - reg = <0x2a00000 0x1600000>; // 22MB - label = "rwfs"; - }; - }; +#include "openbmc-flash-layout-64.dtsi" }; }; diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi index 91163867be3483..31f59de5190b8e 100644 --- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi +++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi @@ -9,27 +9,27 @@ partitions { #size-cells = <1>; u-boot@0 { - reg = <0x0 0x60000>; // 384KB + reg = <0x0 0xe0000>; // 896KB label = "u-boot"; }; - u-boot-env@60000 { - reg = <0x60000 0x20000>; // 128KB + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB label = "u-boot-env"; }; - kernel@80000 { - reg = <0x80000 0x500000>; // 5MB + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB label = "kernel"; }; - rofs@580000 { - reg = <0x580000 0x2a80000>; // 42.5MB + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB label = "rofs"; }; - rwfs@3000000 { - reg = <0x3000000 0x1000000>; // 16MB + rwfs@6000000 { + reg = <0x2a00000 0x1600000>; // 22MB label = "rwfs"; }; }; From 18d5c7bf50c6d820c366c2a23d71d468b14c87d6 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 19 May 2021 15:37:54 -0500 Subject: [PATCH 298/511] arm64: dts: rockchip: add rk817 codec to Odroid Go Add the new rk817 codec driver to the Odroid Go Advance. Signed-off-by: Chris Morgan Tested-by: Maciej Matuszczyk Link: https://lore.kernel.org/r/20210519203754.27184-5-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3326-odroid-go2.dts | 36 +++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index 49c97f76df774f..017c1a76d9aae0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -165,6 +165,31 @@ }; }; + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Analog"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + }; + vccsys: vccsys { compatible = "regulator-fixed"; regulator-name = "vcc3v8_sys"; @@ -269,11 +294,14 @@ reg = <0x20>; interrupt-parent = <&gpio0>; interrupts = ; + clock-output-names = "rk808-clkout1", "xin32k"; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S1_OUT>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; + pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; wakeup-source; #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "xin32k"; + #sound-dai-cells = <0>; vcc1-supply = <&vccsys>; vcc2-supply = <&vccsys>; @@ -432,6 +460,10 @@ }; }; }; + + rk817_codec: codec { + rockchip,mic-in-differential; + }; }; }; From 8c3d64251ac5c5a3d10364f6b07d3603ac1e7b4a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 1 Jun 2021 18:47:59 +0200 Subject: [PATCH 299/511] arm64: dts: rockchip: rename nodename for phy-rockchip-inno-usb2 The pattern: "^(|usb-|usb2-|usb3-|pci-|pcie-|sata-)phy(@[0-9a-f,]+)*$" in phy-provider.yaml has required "#phy-cells" for phy nodes. The "phy-cells" in rockchip-inno-usb2 nodes are located in subnodes. Rename the nodename to pattern "usb2phy@[0-9a-f]+$" to prevent notifications. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/schemas/ phy/phy-provider.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210601164800.7670-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 4e243d72e16fa1..248ebb61aa7901 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -822,7 +822,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,px30-usb2phy"; reg = <0x100 0x20>; clocks = <&pmucru SCLK_USBPHY_REF>; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index bc0bdc3d86ff8f..8c821acb21ffbc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -819,7 +819,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,rk3328-usb2phy"; reg = <0x100 0x10>; clocks = <&xin24m>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a2eba535769398..c1a253507ac4c8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1418,7 +1418,7 @@ status = "disabled"; }; - u2phy0: usb2-phy@e450 { + u2phy0: usb2phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; clocks = <&cru SCLK_USB2PHY0_REF>; @@ -1445,7 +1445,7 @@ }; }; - u2phy1: usb2-phy@e460 { + u2phy1: usb2phy@e460 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe460 0x10>; clocks = <&cru SCLK_USB2PHY1_REF>; From 9fcf74b274a1dc5bcda37c34470061ef1e1130dd Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Tue, 1 Jun 2021 18:48:00 +0200 Subject: [PATCH 300/511] arm64: dts: rockchip: add USB support to rk3308.dtsi The Rockchip RK3308 features an integrated USB 2.0 phy, an USB OTG controller and OHCI/EHCI interfaces. This patch adds all of those to the RK3308 dtsi and thereby enables USB support on the RK3308. Signed-off-by: Tobias Schramm Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210601164800.7670-6-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 74 +++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 0c5fa9801e6fd0..4fca2c4a53223c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -164,7 +164,7 @@ grf: grf@ff000000 { compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x10000>; + reg = <0x0 0xff000000 0x0 0x08000>; reboot-mode { compatible = "syscon-reboot-mode"; @@ -177,6 +177,42 @@ }; }; + usb2phy_grf: syscon@ff008000 { + compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff008000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2phy@100 { + compatible = "rockchip,rk3308-usb2phy"; + reg = <0x100 0x10>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + clocks = <&cru SCLK_USBPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + status = "disabled"; + + u2phy_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + detect_grf: syscon@ff00b000 { compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; reg = <0x0 0xff00b000 0x0 0x1000>; @@ -579,6 +615,42 @@ status = "disabled"; }; + usb20_otg: usb@ff400000 { + compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host_ehci: usb@ff440000 { + compatible = "generic-ehci"; + reg = <0x0 0xff440000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@ff450000 { + compatible = "generic-ohci"; + reg = <0x0 0xff450000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + sdmmc: mmc@ff480000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff480000 0x0 0x4000>; From 2fd2300a9c17ee1c48b1b7a7fabbb90fd12a64f1 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 1 Jun 2021 18:47:58 +0200 Subject: [PATCH 301/511] ARM: dts: rockchip: rename nodename for phy-rockchip-inno-usb2 The pattern: "^(|usb-|usb2-|usb3-|pci-|pcie-|sata-)phy(@[0-9a-f,]+)*$" in phy-provider.yaml has required "#phy-cells" for phy nodes. The "phy-cells" in rockchip-inno-usb2 nodes are located in subnodes. Rename the nodename to pattern "usb2phy@[0-9a-f]+$" to prevent notifications. make ARCH=arm dtbs_check DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/schemas/ phy/phy-provider.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210601164800.7670-4-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 4 ++-- arch/arm/boot/dts/rv1108.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 5774bc309eb747..cffd7acfb94fc6 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -190,7 +190,7 @@ status = "disabled"; }; - u2phy0: usb2-phy@760 { + u2phy0: usb2phy@760 { compatible = "rockchip,rk3228-usb2phy"; reg = <0x0760 0x0c>; clocks = <&cru SCLK_OTGPHY0>; @@ -217,7 +217,7 @@ }; }; - u2phy1: usb2-phy@800 { + u2phy1: usb2phy@800 { compatible = "rockchip,rk3228-usb2phy"; reg = <0x0800 0x0c>; clocks = <&cru SCLK_OTGPHY1>; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 884872ca5207f8..9bd0acf3b7086c 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -265,7 +265,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,rv1108-usb2phy"; reg = <0x100 0x0c>; clocks = <&cru SCLK_USBPHY>; From 60fba46d6e7a6e5de4be2ea158aa6134ec7a161e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 3 Jun 2021 14:10:10 +0200 Subject: [PATCH 302/511] ARM: dts: rockchip: remove #phy-cells from usbphy node rk3066/rk3188 The review process of rockchip-usb-phy.yaml was not finished when the patch in the link below was already applied. Remove the unneeded #phy-cells property. https://lore.kernel.org/r/20210512122346.9463-4-jbx6244@gmail.com Fixes: 6e4e4e2a2558 ("ARM: dts: rockchip: move and restyle grf nodes rk3066/rk3188") Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210603121010.4315-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 1 - arch/arm/boot/dts/rk3188.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 30dcf557ec33fd..511311d257bdbc 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -684,7 +684,6 @@ usbphy: usbphy { compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; - #phy-cells = <0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 3a0c50026b074a..b36fcdd9a51602 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -644,7 +644,6 @@ usbphy: usbphy { compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; - #phy-cells = <0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 010da3daf9278ed03d38b7dcb0422f1a7df1bdd3 Mon Sep 17 00:00:00 2001 From: Santosh Puranik Date: Fri, 30 Apr 2021 13:59:58 -0500 Subject: [PATCH 303/511] ARM: dts: aspeed: Everest: Fix cable card PCA chips Correct two PCA chips which were placed on the wrong I2C bus and address. Signed-off-by: Eddie James Signed-off-by: Santosh Puranik Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 168 +++++++++---------- 1 file changed, 83 insertions(+), 85 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 3295c8c7c05c8c..27af28c8847d0a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -353,10 +353,47 @@ &i2c1 { status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; - pca2: pca9552@61 { +&i2c3 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + + power-supply@68 { + compatible = "ibm,cffps"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps"; + reg = <0x69>; + }; + + power-supply@6a { + compatible = "ibm,cffps"; + reg = <0x6a>; + }; + + power-supply@6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; +}; + +&i2c4 { + status = "okay"; + + pca2: pca9552@65 { compatible = "nxp,pca9552"; - reg = <0x61>; + reg = <0x65>; #address-cells = <1>; #size-cells = <0>; @@ -424,12 +461,54 @@ reg = <9>; type = ; }; + }; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c4mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + }; + + i2c4mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c4mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; }; +}; - pca3: pca9552@62 { +&i2c5 { + status = "okay"; + + pca3: pca9552@66 { compatible = "nxp,pca9552"; - reg = <0x62>; + reg = <0x66>; #address-cells = <1>; #size-cells = <0>; @@ -512,87 +591,6 @@ }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; - - power-supply@68 { - compatible = "ibm,cffps"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps"; - reg = <0x69>; - }; - - power-supply@6a { - compatible = "ibm,cffps"; - reg = <0x6a>; - }; - - power-supply@6b { - compatible = "ibm,cffps"; - reg = <0x6b>; - }; -}; - -&i2c4 { - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; - - i2c4mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - }; - - i2c4mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - i2c4mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - i2c-switch@70 { compatible = "nxp,pca9546"; reg = <0x70>; From 189e847a0f0bcf99df5aea85e634abada5fbfbf4 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Fri, 30 Apr 2021 13:59:59 -0500 Subject: [PATCH 304/511] ARM: dts: aspeed: Rainier 4U: Remove fan updates The 4U fans do not need a different "tach-pulses" property than the 2U machine. In addition, the "maxim,fan-dual-tach" property does not exist upstream yet, so it should also be removed. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- .../boot/dts/aspeed-bmc-ibm-rainier-4u.dts | 30 ------------------- 1 file changed, 30 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts index f7fd3b3c90d08b..342546a3c0f5a9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts @@ -19,33 +19,3 @@ reg = <0x6b>; }; }; - -&fan0 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan1 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan2 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan3 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan4 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan5 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; From 51b48037238ffb0af7488dd3a122531c6a56e4b4 Mon Sep 17 00:00:00 2001 From: Vishwanatha Subbanna Date: Fri, 30 Apr 2021 14:00:00 -0500 Subject: [PATCH 305/511] ARM: dts: aspeed: Everest: Add directly controlled LEDs These LEDs are directly connected to the BMC's GPIO bank Signed-off-by: Eddie James Signed-off-by: Vishwanatha Subbanna Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 33 ++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 27af28c8847d0a..2ddd10e93a80cb 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -202,6 +202,35 @@ linux,code = <12>; }; }; + + leds { + compatible = "gpio-leds"; + + /* RTC battery fault LED at the back */ + led-rtc-battery { + gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>; + }; + + /* BMC Card fault LED at the back */ + led-bmc { + gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure Identify LED at the back */ + led-rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure fault LED at the back */ + led-rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + + /* PCIE slot power LED */ + led-pcieslot-power { + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; + }; + }; }; &gpio0 { @@ -214,7 +243,7 @@ /*F0-F7*/ "PIN_HOLE_RESET_IN_N","","", "PIN_HOLE_RESET_OUT_N","","","","", /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", + /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","","", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", @@ -222,7 +251,7 @@ /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", + /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "","","","","","","","", /*R0-R7*/ "","","","","","I2C_FLASH_MICRO_N","","", /*S0-S7*/ "","","","","","","","", From d5dd6fd128c899a2f2e6fff0222221b3ace8c7cb Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 3 Jun 2021 16:15:36 +0930 Subject: [PATCH 306/511] ARM: dts: aspeed-g5: Add SCU phandle to GFX node In v5.13 the DRM driver gained support for using a phandle to the SCU, instead of matching on the scu compatible. Link: https://lore.kernel.org/r/20210603064536.165297-1-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d733c1f161c1b9..329eaeef66fb79 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -264,6 +264,7 @@ reg-io-width = <4>; clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; resets = <&syscon ASPEED_RESET_CRT1>; + syscon = <&syscon>; status = "disabled"; interrupts = <0x19>; }; From 92e669017ff1616ba7d8ba3c65f5193bc2a7acbe Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 4 Jun 2021 15:19:25 +0200 Subject: [PATCH 307/511] dt-bindings: i2c: at91: fix example for scl-gpios The SCL gpio pin used by I2C bus for recovery needs to be configured as open drain, so fix the binding example accordingly. In relation with fix c5a283802573 ("ARM: dts: at91: Configure I2C SCL gpio as open drain"). Signed-off-by: Nicolas Ferre Fixes: 19e5cef058a0 ("dt-bindings: i2c: at91: document optional bus recovery properties") --- Documentation/devicetree/bindings/i2c/i2c-at91.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt index 96c914e048f594..2015f50aed0f9a 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt @@ -73,7 +73,7 @@ i2c0: i2c@f8034600 { pinctrl-0 = <&pinctrl_i2c0>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; wm8731: wm8731@1a { compatible = "wm8731"; From d5aede3e6dd1b8ca574600a1ecafe1e580c53f2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 12 May 2021 15:07:09 +0200 Subject: [PATCH 308/511] ARM: dts: BCM5301X: Fixup SPI binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. Reorder interrupts 2. Fix typo: s/spi_lr_overhead/spi_lr_overread/ 3. Rename node: s/spi-nor@0/flash@0/ This fixes: arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dt.yaml: spi@18029200: interrupt-names: 'oneOf' conditional failed, one must be fixed: ['spi_lr_fullness_reached', 'spi_lr_session_aborted', 'spi_lr_impatient', 'spi_lr_session_done', 'spi_lr_overhead', 'mspi_done', 'mspi_halted'] is too long Additional items are not allowed ('spi_lr_session_aborted', 'spi_lr_impatient', 'spi_lr_session_done', 'spi_lr_overhead', 'mspi_done', 'mspi_halted' were unexpected) 'mspi_done' was expected 'spi_l1_intr' was expected 'mspi_halted' was expected 'spi_lr_fullness_reached' was expected 'spi_lr_session_aborted' was expected 'spi_lr_impatient' was expected 'spi_lr_session_done' was expected 'spi_lr_overread' was expected From schema: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dt.yaml: spi-nor@0: $nodename:0: 'spi-nor@0' does not match '^flash(@.*)?$' From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 5b9723a10bd66d..f92089290ccd5b 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -520,27 +520,27 @@ <0x1811b408 0x004>, <0x180293a0 0x01c>; reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = , + interrupts = , + , + , , , , - , - , - ; - interrupt-names = "spi_lr_fullness_reached", + ; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", "spi_lr_session_aborted", "spi_lr_impatient", "spi_lr_session_done", - "spi_lr_overhead", - "mspi_done", - "mspi_halted"; + "spi_lr_overread"; clocks = <&iprocmed>; clock-names = "iprocmed"; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; - spi_nor: spi-nor@0 { + spi_nor: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; From 361a02c1e25f148b910fbfbfd77aeb51401e1ea9 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 4 Jun 2021 13:11:55 -0700 Subject: [PATCH 309/511] ARM: dts: keystone: k2g: Rename message-manager node Rename message-manager instance node name to be better aligned with current style of device tree nodes for mailboxes. Reviewed-by: Tero Kristo Acked-by: Suman Anna Signed-off-by: Nishanth Menon Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 05a75019275e26..e5c813b5556db6 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -242,7 +242,7 @@ status = "disabled"; }; - msgmgr: msgmgr@2a00000 { + msgmgr: mailbox@2a00000 { compatible = "ti,k2g-message-manager"; #mbox-cells = <2>; reg-names = "queue_proxy_region", From f594874e36fd440d75e24836615297a827900149 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 4 Jun 2021 13:12:31 -0700 Subject: [PATCH 310/511] ARM: dts: keystone: k2g: Rename the TI-SCI node Lets rename the node name of TI-SCI node to be system-controller as it is a better standardized name for the function that TI-SCI plays in the SoC. Reviewed-by: Tero Kristo Signed-off-by: Nishanth Menon Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index e5c813b5556db6..d7fc6057ca41bc 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -254,7 +254,7 @@ ; }; - pmmc: pmmc@2921c00 { + pmmc: system-controller@2921c00 { compatible = "ti,k2g-sci"; /* * In case of rare platforms that does not use k2g as From 39b73baa44e76cc9e0d805f0ee1309454652c2df Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 4 Jun 2021 13:12:59 -0700 Subject: [PATCH 311/511] ARM: dts: keystone: k2g: Rename the TI-SCI clocks node name We currently use clocks as the node name for the node representing TI-SCI clock nodes. This is better renamed to being clock-controller as that is a better representative of the system controller function as a clock controller for the SoC. Reviewed-by: Tero Kristo Signed-off-by: Nishanth Menon Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index d7fc6057ca41bc..37198294f4b26e 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -272,7 +272,7 @@ #power-domain-cells = <1>; }; - k2g_clks: clocks { + k2g_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; From 0b5194dec85b9f3971900129f9a3584a6cb5918d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 4 Jun 2021 13:32:47 -0700 Subject: [PATCH 312/511] ARM: dts: keystone: k2g-evm: Move audio oscillator assigned clock to mcasp Setting assigned clock with a dependency on itself for k2g_clks creates a circular dependency. Instead, Lets model the audio clock as a assigned-clock configuration for mcasp and set it up as the first clock assigned-clock to be satisfied. Following the standard convention, we use null entries to indicate entries that doesn't need to be programmed. Reviewed-by: Tero Kristo Signed-off-by: Nishanth Menon Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-evm.dts | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 14e26a4fd62ac9..d800f26b627511 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -544,20 +544,15 @@ }; }; -&k2g_clks { - /* on the board 22.5792MHz is connected to AUDOSC_IN */ - assigned-clocks = <&k2g_clks 0x4c 2>; - assigned-clock-rates = <22579200>; -}; - &mcasp2 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcasp2_pins>; - assigned-clocks = <&k2g_clks 0x6 1>; - assigned-clock-parents = <&k2g_clks 0x6 2>; + assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>; + assigned-clock-parents = <0>, <&k2g_clks 0x6 2>; + assigned-clock-rates = <22579200>, <0>; status = "okay"; From eb59cd3e39835d7a87d1e2cf4f5eb5f8ecd12bba Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Thu, 3 Jun 2021 08:12:34 -0700 Subject: [PATCH 313/511] arm64: dts: qcom: pm6150: Add thermal zone for PMIC on-die temperature MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a thermal zone for the pm6150 on-die temperature. The system should try to shut down orderly when the temperature reaches the critical trip point at 115°C, otherwise the PMIC will perform a HW power off at 145°C. Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20210603081215.v2.1.Id4510e9e4baaa3f6c9fdd5cdf4d8606e63c262e3@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 8ab4f1f78bbf66..8a4972e6a24c1e 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -7,6 +7,30 @@ #include #include +/ { + thermal-zones { + pm6150_thermal: pm6150-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm6150_temp>; + + trips { + pm6150_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm6150_crit: crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm6150_lsid0: pmic@0 { compatible = "qcom,pm6150", "qcom,spmi-pmic"; From 61f363a625fcbff93171a271b898fcf37dd367c3 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 4 Jun 2021 19:27:38 +0200 Subject: [PATCH 314/511] arm64: dts: qcom: msm8916-samsung-a2015: Add touch key The Samsung Galaxy A3/A5 both have two capacitive touch keys, connected to an ABOV MCU. It implements the same interface as implemented by the tm2-touchkey driver and works just fine with the coreriver,tc360-touchkey compatible. It's probably actually some Samsung-specific interface that they implement with different MCUs. Note that for some reason Samsung decided to connect this to GPIOs where no hardware I2C bus is available, so we need to fall back to software bit-banging using i2c-gpio. The vdd/vcc-supply is board-specific and will be added separately for a3u/a5u. Co-developed-by: Michael Srba Signed-off-by: Michael Srba Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210604172742.10593-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../qcom/msm8916-samsung-a2015-common.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 230ba3ce3277fa..3c77e7ef9eda47 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -95,6 +95,35 @@ pinctrl-0 = <&muic_int_default>; }; }; + + i2c-tkey { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey: touchkey@20 { + /* Note: Actually an ABOV MCU that implements same interface */ + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + + interrupt-parent = <&msmgpio>; + interrupts = <98 IRQ_TYPE_EDGE_FALLING>; + + /* vcc/vdd-supply are board-specific */ + vddio-supply = <&pm8916_l6>; + + linux,keycodes = ; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_default>; + }; + }; }; &blsp_i2c2 { @@ -333,6 +362,22 @@ bias-disable; }; + tkey_default: tkey-default { + pins = "gpio98"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_i2c_default: tkey-i2c-default { + pins = "gpio16", "gpio17"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tsp_en_default: tsp-en-default { pins = "gpio73"; function = "gpio"; From 92b5c3975b3b582c6d558f74c65e3ff8b58d9dac Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Fri, 4 Jun 2021 19:27:39 +0200 Subject: [PATCH 315/511] arm64: dts: qcom: msm8916-samsung-a3u: Add touch key regulators The touch key MCU and LED is supplied by two separate fixed regulators that can be enabled through GPIO 86 and 60. Add them to the device tree. Signed-off-by: Michael Srba [stephan: extend commit message] Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210604172742.10593-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 661f41ad978bf8..6cc2eaeb1d33d5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -20,6 +20,37 @@ pinctrl-names = "default"; pinctrl-0 = <&panel_vdd3_default>; }; + + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_en_default>; + }; + + reg_key_led: regulator-key-led { + compatible = "regulator-fixed"; + regulator-name = "key_led"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_led_en_default>; + }; +}; + +&touchkey { + vcc-supply = <®_touch_key>; + vdd-supply = <®_key_led>; }; &accelerometer { @@ -81,6 +112,22 @@ bias-disable; }; + tkey_en_default: tkey-en-default { + pins = "gpio86"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_led_en_default: tkey-led-en-default { + pins = "gpio60"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + ts_int_default: ts-int-default { pins = "gpio13"; function = "gpio"; From 410040777744aecd0b77659f43464f7ed86896a5 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 4 Jun 2021 19:27:40 +0200 Subject: [PATCH 316/511] arm64: dts: qcom: msm8916-samsung-a5u: Add touch key regulator On the Samsung Galaxy A5 the touch key is supplied by a single fixed regulator (enabled via GPIO 97) that supplies both MCU and LED. Add it to the device tree. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210604172742.10593-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index dd35c3344358ca..c2eff5aebf85af 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -7,6 +7,19 @@ / { model = "Samsung Galaxy A5U (EUR)"; compatible = "samsung,a5u-eur", "qcom,msm8916"; + + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_en_default>; + }; }; &accelerometer { @@ -42,7 +55,20 @@ }; }; +&touchkey { + vcc-supply = <®_touch_key>; + vdd-supply = <®_touch_key>; +}; + &msmgpio { + tkey_en_default: tkey-en-default { + pins = "gpio97"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + ts_int_default: ts-int-default { pins = "gpio13"; function = "gpio"; From 0c04d16f4123f5eccc9f7e0199ce2e050261fd0f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 4 Jun 2021 19:27:41 +0200 Subject: [PATCH 317/511] arm64: dts: qcom: msm8916-samsung-a2015: Add rt5033 battery The Samsung Galaxy A3/A5 use a Richtek RT5033 PMIC as battery fuel gauge, charger, flash LED and for some regulators. For now, only add the fuel gauge/battery device to the device tree, so we can check the remaining battery percentage. The other RT5033 drivers need some more work first before they can be used properly. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210604172742.10593-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../qcom/msm8916-samsung-a2015-common.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 3c77e7ef9eda47..9a6988ded29d47 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -151,6 +151,20 @@ }; }; +&blsp_i2c4 { + status = "okay"; + + battery@35 { + compatible = "richtek,rt5033-battery"; + reg = <0x35>; + interrupt-parent = <&msmgpio>; + interrupts = <121 IRQ_TYPE_EDGE_BOTH>; + + pinctrl-names = "default"; + pinctrl-0 = <&fg_alert_default>; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -313,6 +327,14 @@ bias-disable; }; + fg_alert_default: fg-alert-default { + pins = "gpio121"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default { pins = "gpio107", "gpio109"; function = "gpio"; From 5e57e5d0d62216502ce603f3399e411368e11a43 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 4 Jun 2021 19:27:42 +0200 Subject: [PATCH 318/511] arm64: dts: qcom: msm8916-samsung-a2015: Add NFC The Samsung Galaxy A3/A5 both have a Samsung S3FWRN5 NFC chip that works quite well with the s3fwrn5 driver in the Linux NFC subsystem. The clock setup for the NFC chip is a bit special (although this seems to be a common approach used for Qualcomm devices with NFC): The NFC chip has an output GPIO that is asserted whenever the clock is needed to function properly. On the A3/A5 this is wired up to PM8916 GPIO2, which is then configured with a special function (NFC_CLK_REQ or BB_CLK2_REQ). Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct PM8916 to automatically enable the clock whenever the NFC chip requests it. The advantage is that the clock is only enabled when needed and we don't need to manage it ourselves from the NFC driver. Note that for some reason Samsung decided to connect the I2C pins to GPIOs where no hardware I2C bus is available, so we need to fall back to software bit-banging with i2c-gpio. Cc: Krzysztof Kozlowski Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210604172742.10593-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../qcom/msm8916-samsung-a2015-common.dtsi | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 9a6988ded29d47..9b4b7de7cec2d6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { aliases { @@ -124,6 +125,34 @@ pinctrl-0 = <&tkey_default>; }; }; + + i2c-nfc { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + nfc@27 { + compatible = "samsung,s3fwrn5-i2c"; + reg = <0x27>; + + interrupt-parent = <&msmgpio>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + en-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_default &nfc_clk_req>; + }; + }; }; &blsp_i2c2 { @@ -384,6 +413,30 @@ bias-disable; }; + nfc_default: nfc-default { + pins = "gpio20", "gpio49"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + + irq { + pins = "gpio21"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + }; + + nfc_i2c_default: nfc-i2c-default { + pins = "gpio0", "gpio1"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tkey_default: tkey-default { pins = "gpio98"; function = "gpio"; @@ -408,3 +461,14 @@ bias-disable; }; }; + +&pm8916_gpios { + nfc_clk_req: nfc-clk-req { + pins = "gpio2"; + function = "func1"; + + input-enable; + bias-disable; + power-source = ; + }; +}; From c8d6f8e5307dd38be995648265086466bab6c397 Mon Sep 17 00:00:00 2001 From: Sujit Kautkar Date: Wed, 2 Jun 2021 12:13:39 -0700 Subject: [PATCH 319/511] arm64: dts: qcom: sc7180: Move sdc pinconf to board specific DT files Move sdc1/sdc2 pinconf from SoC specific DT file to board specific DT files Reviewed-by: Douglas Anderson Signed-off-by: Sujit Kautkar Link: https://lore.kernel.org/r/20210602121313.v3.1.Ia83c80aec3b9535f01441247b6c3fb6f80b0ec7f@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 102 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 102 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 ------------------- 3 files changed, 204 insertions(+), 102 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 52899dd4feb021..c4521ae7e4b250 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -663,4 +663,106 @@ bias-pull-up; }; }; + + sdc1_on: sdc1-on { + pinconf-clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + pinconf-cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1-off { + pinconf-clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + pinconf-cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2-on { + pinconf-clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + pinconf-cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-sd-cd { + pins = "gpio69"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2-off { + pinconf-clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + pinconf-cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-sd-cd { + pins = "gpio69"; + bias-disable; + drive-strength = <2>; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index a4cbdc36c306eb..f9f701bc7f066f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1491,4 +1491,106 @@ ap_spi_fp: &spi10 { drive-strength = <2>; }; }; + + sdc1_on: sdc1-on { + pinconf-clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + pinconf-cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1-off { + pinconf-clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + pinconf-cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2-on { + pinconf-clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + pinconf-cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-sd-cd { + pins = "gpio69"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2-off { + pinconf-clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + pinconf-cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-sd-cd { + pins = "gpio69"; + bias-disable; + drive-strength = <2>; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 295844e90dd532..52115e0359bdf8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1867,108 +1867,6 @@ function = "lpass_ext"; }; }; - - sdc1_on: sdc1-on { - pinconf-clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - pinconf-cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc1_off: sdc1-off { - pinconf-clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - pinconf-cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc2_on: sdc2-on { - pinconf-clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - pinconf-cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-sd-cd { - pins = "gpio69"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc2_off: sdc2-off { - pinconf-clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - pinconf-cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-sd-cd { - pins = "gpio69"; - bias-disable; - drive-strength = <2>; - }; - }; }; remoteproc_mpss: remoteproc@4080000 { From 71208cd4b1ff7d8275e5154723b8f4e1a514fd9b Mon Sep 17 00:00:00 2001 From: Sujit Kautkar Date: Wed, 2 Jun 2021 12:13:41 -0700 Subject: [PATCH 320/511] arm64: dts: qcom: sc7180: SD-card GPIO pin set bias-pull up Some SC7180 based boards do not have external pull-up for cd-gpio. Set this pin to internal pull-up for sleep config to avoid frequent regulator toggle events. Reviewed-by: Douglas Anderson Signed-off-by: Sujit Kautkar Link: https://lore.kernel.org/r/20210602121313.v3.2.I52f30ddfe62041b7e6c3c362f0ad8f695ac28224@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index c4521ae7e4b250..acdb36f4479fcc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -761,7 +761,7 @@ pinconf-sd-cd { pins = "gpio69"; - bias-disable; + bias-pull-up; drive-strength = <2>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index f9f701bc7f066f..5c137aa700c0d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1589,7 +1589,7 @@ ap_spi_fp: &spi10 { pinconf-sd-cd { pins = "gpio69"; - bias-disable; + bias-pull-up; drive-strength = <2>; }; }; From 636245a6b16d29202a60b8bd32b85809c5e53ab7 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Tue, 19 May 2020 07:32:58 -0500 Subject: [PATCH 321/511] arm64: dts: qcom: sdm845-mtp: enable IPA Enable IPA on the SDM845 MTP. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20200519123258.29228-1-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 1372fe8601f507..91ede9296aff0b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -448,6 +448,11 @@ clock-frequency = <400000>; }; +&ipa { + status = "okay"; + memory-region = <&ipa_fw_mem>; +}; + &mdss { status = "okay"; }; From d1f781db47a88c8889ca5c258a8f9448e201e430 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 3 Jun 2021 15:29:23 +0300 Subject: [PATCH 322/511] arm64: dts: qcom: add initial device-tree for Microsoft Surface Duo Microsoft Surface Duo is based on SM8150 chipset. This new Device Tree is a copy of sm8150-mtp with a the addition of the volume up key and relevant i2c nodes. Signed-off-by: Felipe Balbi Link: https://lore.kernel.org/r/20210603122923.1919624-1-balbi@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sm8150-microsoft-surface-duo.dts | 543 ++++++++++++++++++ 2 files changed, 544 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7f2d6e83b15852..f4276c271d66fc 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts new file mode 100644 index 00000000000000..736da9af44e082 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2021, Microsoft Corporation + */ + +/dts-v1/; + +#include +#include +#include "sm8150.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/ { + model = "Microsoft Surface Duo"; + compatible = "microsoft,surface-duo", "qcom,sm8150"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8150 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + vol_up { + label = "Volume Up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vdda_wcss_pll: + vreg_l1a_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vdd_pdphy: + vdda_usb_hs_3p1: + vreg_l2a_3p1: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p8: ldo3 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + vdd_usb_hs_core: + vdda_csi_0_0p9: + vdda_csi_1_0p9: + vdda_csi_2_0p9: + vdda_csi_3_0p9: + vdda_dsi_0_0p9: + vdda_dsi_1_0p9: + vdda_dsi_0_pll_0p9: + vdda_dsi_1_pll_0p9: + vdda_pcie_1ln_core: + vdda_pcie_2ln_core: + vdda_pll_hv_cc_ebi01: + vdda_pll_hv_cc_ebi23: + vdda_qrefs_0p875_5: + vdda_sp_sensor: + vdda_ufs_2ln_core_1: + vdda_ufs_2ln_core_2: + vdda_usb_ss_dp_core_1: + vdda_usb_ss_dp_core_2: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vreg_l5a_0p875: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l9a_1p2: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10a_2p5: ldo10 { + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l11a_0p8: ldo11 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc_cs_1p8: + vdda_gfx_cs_1p8: + vdda_usb_hs_1p8: + vdda_qrefs_vref_1p8: + vddpx_10_a: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_2p7: ldo13 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p7: ldo15 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdda_wcss_adcdac_1: + vdda_wcss_adcdac_22: + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_hv_refgen0: + vdda_qlink_hv_ck: + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vddpx_5: + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vddpx_6: + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + + vreg_l2f_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l5f_2p85: ldo5 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6f_2p85: ldo6 { + regulator-initial-mode = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <2856000>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + bq27742@55 { + compatible = "ti,bq27742"; + reg = <0x55>; + }; + + da7280@4a { + compatible = "dlg,da7280"; + reg = <0x4a>; + interrupts-extended = <&tlmm 42 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "da7280_default"; + pinctrl-0 = <&da7280_intr_default>; + + dlg,actuator-type = "LRA"; + dlg,dlg,const-op-mode = <1>; + dlg,dlg,periodic-op-mode = <1>; + dlg,nom-microvolt = <2000000>; + dlg,abs-max-microvolt = <2000000>; + dlg,imax-microamp = <129000>; + dlg,resonant-freq-hz = <180>; + dlg,impd-micro-ohms = <14300000>; + dlg,freq-track-enable; + dlg,bemf-sens-enable; + dlg,mem-array = < + 0x06 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x1c 0x2a + 0x33 0x3c 0x42 0x4b 0x4c 0x4e 0x17 0x19 0x27 0x29 + 0x17 0x19 0x03 0x84 0x5e 0x04 0x08 0x84 0x5d 0x01 + 0x84 0x5e 0x02 0x00 0xa4 0x5d 0x03 0x84 0x5e 0x06 + 0x08 0x84 0x5d 0x05 0x84 0x5d 0x06 0x84 0x5e 0x08 + 0x84 0x5e 0x05 0x8c 0x5e 0x24 0x84 0x5f 0x10 0x84 + 0x5e 0x05 0x84 0x5e 0x08 0x84 0x5f 0x01 0x8c 0x5e + 0x04 0x84 0x5e 0x08 0x84 0x5f 0x11 0x19 0x88 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + >; + }; + + /* SMB1381 @ 0x44 */ + /* MAX34417 @ 0x1c */ +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + /* SMB1355 @ 0x0c */ + /* SMB1390 @ 0x10 */ +}; + +&i2c17 { + status = "okay"; + clock-frequency = <400000>; + + bq27742@55 { + compatible = "ti,bq27742"; + reg = <0x55>; + }; +}; + +&i2c19 { + status = "okay"; + clock-frequency = <400000>; + + /* MAX34417 @ 0x12 */ + /* MAX34417 @ 0x1a */ + /* MAX34417 @ 0x1e */ +}; + +&pon { + pwrkey { + status = "okay"; + }; + + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&remoteproc_adsp { + status = "okay"; + firmware-name = "qcom/sm8150/microsoft/adsp.mdt"; +}; + +&remoteproc_cdsp { + status = "okay"; + firmware-name = "qcom/sm8150/microsoft/cdsp.mdt"; +}; + +&remoteproc_mpss { + status = "okay"; + firmware-name = "qcom/sm8150/microsoft/modem.mdt"; +}; + +&remoteproc_slpi { + status = "okay"; + firmware-name = "qcom/sm8150/microsoft/slpi.mdt"; +}; + +&tlmm { + gpio-reserved-ranges = <126 4>; + + da7280_intr_default: da7280-intr-default { + pins = "gpio42"; + function = "gpio"; + bias-pull-up; + input-enable; + }; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10a_2p5>; + vcc-max-microamp = <750000>; + vccq-supply = <&vreg_l9a_1p2>; + vccq-max-microamp = <700000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <750000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs_2ln_core_1>; + vdda-max-microamp = <90200>; + vdda-pll-supply = <&vreg_l3c_1p2>; + vdda-pll-max-microamp = <19000>; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; +}; From c1e9c4a140fce442917106710ac58540f0f19ba8 Mon Sep 17 00:00:00 2001 From: Vishwanatha Subbanna Date: Mon, 7 Jun 2021 12:42:54 +0930 Subject: [PATCH 323/511] ARM: dts: aspeed: everest: Add system level indicator leds These are the system level indicator leds that are driven by PCA9551 connected to the Operator Panel. Signed-off-by: Vishwanatha Subbanna Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20210607031259.475020-2-joel@jms.id.au --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 42 ++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 2ddd10e93a80cb..6a17b75b5d5b22 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -890,6 +890,48 @@ compatible = "atmel,24c32"; reg = <0x50>; }; + + pca_oppanel: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "front-sys-id0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "front-check-log0"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "front-enc-fault1"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "front-sys-pwron0"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; }; i2c14mux0chn3: i2c@3 { From 793de4def91c67bed48b5b17e0ffa2a8e05e6ce2 Mon Sep 17 00:00:00 2001 From: Vishwanatha Subbanna Date: Mon, 7 Jun 2021 12:42:55 +0930 Subject: [PATCH 324/511] ARM: dts: aspeed: everest: Add nvme and fan indicator leds These are the indicator leds for nvme slots and fans and are driven by PCA9552. Signed-off-by: Vishwanatha Subbanna Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20210607031259.475020-3-joel@jms.id.au --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 132 +++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 6a17b75b5d5b22..03c26812c909e1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -970,6 +970,138 @@ }; }; + pca_fan_nvme: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "nvme1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "nvme2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "nvme3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "nvme4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "nvme5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "nvme6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "nvme7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "nvme8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "nvme9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "fan0"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "fan1"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "fan2"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "fan3"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; + pca0: pca9552@61 { compatible = "nxp,pca9552"; #address-cells = <1>; From 66d8e7a296beec739a7120d6e01862eaf3660cf4 Mon Sep 17 00:00:00 2001 From: Vishwanatha Subbanna Date: Mon, 7 Jun 2021 12:42:56 +0930 Subject: [PATCH 325/511] ARM: dts: aspeed: everest: Add pcie slot indicator leds These are pcie slot indicator leds driven by PCA9552. Signed-off-by: Vishwanatha Subbanna Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20210607031259.475020-4-joel@jms.id.au --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 123 +++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 03c26812c909e1..aa960186796df1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -721,6 +721,129 @@ }; }; }; + + pca_pcie_slot: pca9552@65 { + compatible = "nxp,pca9552"; + reg = <0x65>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + led@1 { + label = "pcieslot-c01"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "pcieslot-c02"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "pcieslot-c03"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "pcieslot-c04"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "pcieslot-c05"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "pcieslot-c06"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "pcieslot-c07"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "pcieslot-c08"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "pcieslot-c09"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "pcieslot-c10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "pcieslot-c11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; }; &i2c7 { From 5b4673c847c30f5b266921daf53a9d009fca0685 Mon Sep 17 00:00:00 2001 From: Vishwanatha Subbanna Date: Mon, 7 Jun 2021 12:42:57 +0930 Subject: [PATCH 326/511] ARM: dts: aspeed: everest: Add dimm indicator leds These are dimm indicator leds driven by PIC16F882. Signed-off-by: Vishwanatha Subbanna Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20210607031259.475020-5-joel@jms.id.au --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 552 +++++++++++++++++++ 1 file changed, 552 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index aa960186796df1..db8555e7abf982 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -848,6 +848,558 @@ &i2c7 { status = "okay"; + + pic0_dimm: pca9552@31 { + compatible = "ibm,pca9552"; + reg = <0x31>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic1_dimm: pca9552@32 { + compatible = "ibm,pca9552"; + reg = <0x32>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm16"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm17"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm18"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm19"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm20"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm21"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm22"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm23"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm24"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm25"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm26"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm27"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm28"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm29"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm30"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm31"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic2_dimm: pca9552@33 { + compatible = "ibm,pca9552"; + reg = <0x33>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm32"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm33"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm34"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm35"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm36"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm37"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm38"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm39"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm40"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm41"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm42"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm43"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm44"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm45"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm46"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm47"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic3_dimm: pca9552@30 { + compatible = "ibm,pca9552"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm48"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "ddimm49"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "ddimm50"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "ddimm51"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "ddimm52"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "ddimm53"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "ddimm54"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@7 { + label = "ddimm55"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@8 { + label = "ddimm56"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "ddimm57"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "ddimm58"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "ddimm59"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "ddimm60"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "ddimm61"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "ddimm62"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "ddimm63"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; }; &i2c8 { From 2970264fb8aeb5d4e3bc02eb777c2a0e57cf063b Mon Sep 17 00:00:00 2001 From: Vishwanatha Subbanna Date: Mon, 7 Jun 2021 12:42:58 +0930 Subject: [PATCH 327/511] ARM: dts: aspeed: everest: Add vrm and other indicator leds This commit adds indicator leds for vrms, processors, opencapi connectors, tpm, planar, power distribution card and dasd backplane and are driven by PIC16F882. Signed-off-by: Vishwanatha Subbanna Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20210607031259.475020-6-joel@jms.id.au --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 270 +++++++++++++++++++ 1 file changed, 270 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index db8555e7abf982..2bac7d1f8a03b7 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -1400,6 +1400,276 @@ type = ; }; }; + + pic0_vrm_misc: pca9552@34 { + compatible = "ibm,pca9552"; + reg = <0x34>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "planar"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "tpm"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "cpu3-c61"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "cpu0-c14"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "opencapi-connector3"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "opencapi-connector4"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "opencapi-connector5"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + led@8 { + label = "vrm4"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "vrm5"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "vrm6"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "vrm7"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "vrm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "vrm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "vrm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "vrm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; + + pic1_vrm_misc: pca9552@35 { + compatible = "ibm,pca9552"; + reg = <0x35>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "dasd-backplane"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "power-distribution"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@2 { + label = "cpu1-c19"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@3 { + label = "cpu2-c56"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@4 { + label = "opencapi-connector0"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@5 { + label = "opencapi-connector1"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@6 { + label = "opencapi-connector2"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + + led@8 { + label = "vrm0"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@9 { + label = "vrm1"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@10 { + label = "vrm2"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@11 { + label = "vrm3"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@12 { + label = "vrm8"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@13 { + label = "vrm9"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@14 { + label = "vrm10"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@15 { + label = "vrm11"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + }; }; &i2c8 { From dd87684c7c9b82ad450cf063c58b4131074ad8f2 Mon Sep 17 00:00:00 2001 From: Vishwanatha Subbanna Date: Mon, 7 Jun 2021 12:42:59 +0930 Subject: [PATCH 328/511] ARM: dts: aspeed: everest: Add pcie cable card indicator leds These are leds on the IBM proprietary PCIE cards called cable cards. Cable cards have 2 ports on them and each port has an indicator led. Signed-off-by: Vishwanatha Subbanna Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20210607031259.475020-7-joel@jms.id.au --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 714 +++++++++++++++++-- 1 file changed, 665 insertions(+), 49 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 2bac7d1f8a03b7..d26a9e16ff7c30 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -508,6 +508,62 @@ compatible = "atmel,24c64"; reg = <0x52>; }; + + pca_cable_card_c01: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c01-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c01-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; }; i2c4mux0chn1: i2c@1 { @@ -518,6 +574,62 @@ compatible = "atmel,24c64"; reg = <0x50>; }; + + pca_cable_card_c02: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c02-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c02-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; }; i2c4mux0chn2: i2c@2 { @@ -528,6 +640,62 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca_cable_card_c03: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c03-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c03-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; }; }; }; @@ -636,68 +804,404 @@ compatible = "atmel,24c64"; reg = <0x50>; }; - }; - i2c5mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - }; + pca_cable_card_c04: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; - i2c5mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - }; + gpio-controller; + #gpio-cells = <2>; - i2c5mux0chn3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - eeprom@53 { - compatible = "atmel,24c64"; - reg = <0x53>; - }; - }; - }; -}; + led@0 { + label = "cablecard-c04-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; -&i2c6 { - status = "okay"; + led@1 { + label = "cablecard-c04-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; + gpio@2 { + reg = <2>; + type = ; + }; - i2c6mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; }; }; - i2c6mux0chn1: i2c@1 { + i2c5mux0chn1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; - eeprom@52 { + eeprom@51 { compatible = "atmel,24c64"; - reg = <0x52>; + reg = <0x51>; + }; + + pca_cable_card_c05: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c05-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c05-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + }; + + i2c5mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + pca_cable_card_c06: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c06-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c06-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + }; + + i2c5mux0chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; + + pca_cable_card_c07: pca9551@63 { + compatible = "nxp,pca9551"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c07-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c07-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c6mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca_cable_card_c08: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c08-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c08-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; + }; + + i2c6mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + pca_cable_card_c09: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c09-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c09-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; }; }; @@ -709,6 +1213,62 @@ compatible = "atmel,24c64"; reg = <0x53>; }; + + pca_cable_card_c10: pca9551@63 { + compatible = "nxp,pca9551"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c10-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c10-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; }; i2c6mux0chn3: i2c@3 { @@ -719,6 +1279,62 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca_cable_card_c11: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c11-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + led@1 { + label = "cablecard-c11-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + }; }; }; From 479c700c6df222056d246e9fc4eeecd8e4ed1744 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 1 Jun 2021 13:36:12 +0200 Subject: [PATCH 329/511] arm64: dts: renesas: r8a77961: Add INTC-EX device node Populate the device node for the Interrupt Controller for External Devices (INTC-EX) on R-Car M3-W+, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/6f3cc1a1b6d777e743a7a9e66a80aaf9d5232a4f.1622547125.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 3c73ee47791542..91b501e0121ef2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -560,10 +560,19 @@ }; intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77961", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; - /* placeholder */ + interrupts = , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; tmu0: timer@e61e0000 { From 1771a33b34421050c7b830f0a8af703178ba9d36 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 1 Jun 2021 17:12:50 +0200 Subject: [PATCH 330/511] arm64: dts: renesas: r8a779a0: Drop power-domains property from GIC node "make dtbs_check": arm64/boot/dts/renesas/r8a779a0-falcon.dt.yaml: interrupt-controller@f1000000: 'power-domains' does not match any of the regexes: '^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$', '^gic-its@', '^interrupt-controller@[0-9a-f]+$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml Remove the "power-domains" property, as the GIC on R-Car V3U is always-on, and not part of a clock domain. Fixes: 834c310f541839b6 ("arm64: dts: renesas: Add Renesas R8A779A0 SoC support") Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/a9ae5cbc7c586bf2c6b18ddc665ad7051bd1d206.1622560236.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index a023e094e7670e..78ca75f619f6fe 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1102,7 +1102,6 @@ <0x0 0xf1060000 0 0x110000>; interrupts = ; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; }; fcpvd0: fcp@fea10000 { From 79b08ae7c411840ea5a9fba349025d217e700576 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Sat, 29 May 2021 09:07:49 +0530 Subject: [PATCH 331/511] arm64: dts: ti: k3-am65: Add support for UHS-I modes in MMCSD1 subsystem UHS-I speed modes are supported in AM65 S.R. 2.0 SoC[1]. Add support by removing the no-1-8-v tag and including the voltage regulator device tree nodes for power cycling. However, the 4 bit interface of AM65 SR 1.0 cannot be supported at 3.3 V or 1.8 V because of erratas i2025 and i2026 [2]. As the SD card is the primary boot mode for development usecases, continue to enable SD card and disable UHS-I modes in it to minimize any ageing issues happening because of erratas. k3-am6528-iot2050-basic and k3-am6548-iot2050-advanced boards use S.R. 1.0 version of AM65 SoC. Therefore, add no-1-8-v in sdhci1 device tree node of the common iot2050 device tree file. [1] - https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf, section 12.3.6.1.1 [2] - https://www.ti.com/lit/er/sprz452e/sprz452e.pdf Signed-off-by: Aswath Govindraju Acked-by: Jan Kiszka Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210529033749.6250-1-a-govindraju@ti.com --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - .../arm64/boot/dts/ti/k3-am654-base-board.dts | 33 +++++++++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index f4ec9ed5293954..d90abda1de84b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -555,6 +555,7 @@ pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; + no-1-8-v; }; &usb0 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 6cd3131eb9ff94..f97fc00c00ca0f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -301,7 +301,6 @@ ti,otap-del-sel = <0x2>; ti,trm-icp = <0x8>; dma-coherent; - no-1-8-v; }; scm_conf: scm-conf@100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 97c3440884830d..60e43fd7af12b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -85,6 +85,38 @@ gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; }; }; + + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_io: fixedregulator-vcc3v3io { + /* Output of TPS54334 */ + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&evm_12v0>; + }; + + vdd_mmc1_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc3v3_io>; + gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; + }; }; &wkup_pmx0 { @@ -327,6 +359,7 @@ * disable sdhci1 */ &sdhci1 { + vmmc-supply = <&vdd_mmc1_sd>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; From d49a769dcddd4224bd631792a4d2e5bbb160aa20 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 1 Jun 2021 10:00:31 -0500 Subject: [PATCH 332/511] arm64: dts: ti: k3-am65-main: Add ICSSG MDIO nodes The ICSSGs on K3 AM65x SoCs contain an MDIO controller that can be used to control external PHYs associated with the Industrial Ethernet peripherals within each ICSSG instance. The MDIO module used within the ICSSG is similar to the MDIO Controller used in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the MDIO operations. The nodes are added and enabled in the common k3-am65-main.dtsi file by default, and disabled in the existing AM65 board dts files. These nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for ICSSG Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Roger Quadros [s-anna@ti.com: move the disabled status to board dts files] Signed-off-by: Suman Anna Reviewed-by: Grygorii Strashko Acked-by: Jan Kiszka Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210601150032.11432-2-s-anna@ti.com --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ++++++++ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 30 +++++++++++++++++++ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 12 ++++++++ 3 files changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index d90abda1de84b2..8c6b538c53f325 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -702,3 +702,15 @@ &mailbox0_cluster11 { status = "disabled"; }; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; + +&icssg2_mdio { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index f97fc00c00ca0f..e679394d0b7e66 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -1052,6 +1052,16 @@ reg-names = "iram", "control", "debug"; firmware-name = "am65x-txpru0_1-fw"; }; + + icssg0_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 62 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; icssg1: icssg@b100000 { @@ -1183,6 +1193,16 @@ reg-names = "iram", "control", "debug"; firmware-name = "am65x-txpru1_1-fw"; }; + + icssg1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 63 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; icssg2: icssg@b200000 { @@ -1314,5 +1334,15 @@ reg-names = "iram", "control", "debug"; firmware-name = "am65x-txpru2_1-fw"; }; + + icssg2_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 64 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 60e43fd7af12b7..fa057a85e8330b 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -539,3 +539,15 @@ &dss { status = "disabled"; }; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; + +&icssg2_mdio { + status = "disabled"; +}; From 7ce11d4704c080ab890831b8255fbba4d2b0c5ec Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 1 Jun 2021 10:00:32 -0500 Subject: [PATCH 333/511] arm64: dts: ti: k3-j721e-main: Add ICSSG MDIO nodes The ICSSGs on K3 J721E SoCs contain an MDIO controller that can be used to control external PHYs associated with the Industrial Ethernet peripherals within each ICSSG instance. The MDIO module used within the ICSSG is similar to the MDIO Controller used in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the MDIO operations. The nodes are added and enabled in the common k3-j721e-main.dtsi file by default, and disabled in the existing J721E board dts file. These nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for ICSSG Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Suman Anna Reviewed-by: Grygorii Strashko Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210601150032.11432-3-s-anna@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 +++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 351bb84db65bf9..1991f620d94b2e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -718,3 +718,11 @@ &dss { status = "disabled"; }; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 3bcafe4c1742e8..598613876b0f11 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1794,6 +1794,16 @@ reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru0_1-fw"; }; + + icssg0_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 119 1>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; icssg1: icssg@b100000 { @@ -1925,5 +1935,15 @@ reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru1_1-fw"; }; + + icssg1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 120 4>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; }; From 77daceabedb42482bb6200fa26047c5591716e45 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sat, 29 May 2021 15:02:51 +0200 Subject: [PATCH 334/511] Revert "ARM: dts: bcm283x: increase dwc2's RX FIFO size" This reverts commit 278407a53c3b33fb820332c4d39eb39316c3879a. The original change breaks USB config on Raspberry Pi Zero and Pi 4 B, because it exceeds the total fifo size of 4080. A naive attempt to reduce g-tx-fifo-size doesn't help on Raspberry Pi Zero. So better go back. Fixes: 278407a53c3b ("ARM: dts: bcm283x: increase dwc2's RX FIFO size") Signed-off-by: Stefan Wahren Cc: Pavel Hofman Link: https://lore.kernel.org/r/1622293371-5997-1-git-send-email-stefan.wahren@i2se.com Signed-off-by: Nicolas Saenz Julienne --- arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi | 2 +- arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi index 20322de2f8bf18..e2fd9610e12529 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "otg"; - g-rx-fifo-size = <558>; + g-rx-fifo-size = <256>; g-np-tx-fifo-size = <32>; /* * According to dwc2 the sum of all device EP diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi index 1409d1b559c18c..0ff0e9e2532725 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "peripheral"; - g-rx-fifo-size = <558>; + g-rx-fifo-size = <256>; g-np-tx-fifo-size = <32>; g-tx-fifo-size = <256 256 512 512 512 768 768>; }; From 7894bdc6228fa8f9d4762e54dd8ac6b888e122c6 Mon Sep 17 00:00:00 2001 From: Mateusz Kwiatkowski Date: Thu, 20 May 2021 17:03:44 +0200 Subject: [PATCH 335/511] ARM: boot: dts: bcm2711: Add BCM2711 VEC compatible The BCM2711 has a slightly different VEC than the one found in the older SoCs. Now that we support the new variant, add its compatible to the device tree. Signed-off-by: Mateusz Kwiatkowski Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210520150344.273900-5-maxime@cerno.tech Signed-off-by: Nicolas Saenz Julienne --- arch/arm/boot/dts/bcm2711.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 720beec54d6178..0b6900815d1995 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -1087,5 +1087,6 @@ }; &vec { + compatible = "brcm,bcm2711-vec"; interrupts = ; }; From f230c32349eb0a43a012a81c08a7f13859b86cbb Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 6 Jun 2021 14:16:11 +0200 Subject: [PATCH 336/511] ARM: dts: bcm283x: Fix up MMC node names Fix the node names for the MMC/SD card controller to conform to the standard node name mmc@.. Signed-off-by: Stefan Wahren Link: https://lore.kernel.org/r/1622981777-5023-2-git-send-email-stefan.wahren@i2se.com Signed-off-by: Nicolas Saenz Julienne --- arch/arm/boot/dts/bcm2711.dtsi | 2 +- arch/arm/boot/dts/bcm283x.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 0b6900815d1995..b8a4096192aa92 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -413,7 +413,7 @@ ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; - emmc2: emmc2@7e340000 { + emmc2: mmc@7e340000 { compatible = "brcm,bcm2711-emmc2"; reg = <0x0 0x7e340000 0x100>; interrupts = ; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index b83a864e2e8ba1..0f3be55201a5be 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -420,7 +420,7 @@ status = "disabled"; }; - sdhci: sdhci@7e300000 { + sdhci: mmc@7e300000 { compatible = "brcm,bcm2835-sdhci"; reg = <0x7e300000 0x100>; interrupts = <2 30>; From 9dda8d9aa86abd1d1e3128d298022c11ceab6abe Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 6 Jun 2021 14:16:13 +0200 Subject: [PATCH 337/511] ARM: dts: Move BCM2711 RPi specific into separate dtsi There is a lot of Raspberry Pi specific stuff (neither SoC or board specific) for the BCM2711 which is currently in the RPi 4 B dts. In order to avoid copy & paste for every new BCM2711 based Raspberry Pi, move it into a separate dtsi. Signed-off-by: Stefan Wahren Link: https://lore.kernel.org/r/1622981777-5023-4-git-send-email-stefan.wahren@i2se.com Signed-off-by: Nicolas Saenz Julienne --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 81 ++++----------------------- arch/arm/boot/dts/bcm2711-rpi.dtsi | 74 ++++++++++++++++++++++++ 2 files changed, 84 insertions(+), 71 deletions(-) create mode 100644 arch/arm/boot/dts/bcm2711-rpi.dtsi diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 3b4ab947492acc..c54854a1776e0d 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -1,11 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2711.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2711-rpi.dtsi" #include "bcm283x-rpi-usb-peripheral.dtsi" -#include - / { compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; model = "Raspberry Pi 4 Model B"; @@ -15,19 +13,6 @@ stdout-path = "serial1:115200n8"; }; - /* Will be filled by the bootloader */ - memory@0 { - device_type = "memory"; - reg = <0 0 0>; - }; - - aliases { - emmc2bus = &emmc2bus; - ethernet0 = &genet; - pcie0 = &pcie0; - blconfig = &blconfig; - }; - leds { act { gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; @@ -79,31 +64,15 @@ status = "okay"; }; -&firmware { - firmware_clocks: clocks { - compatible = "raspberrypi,firmware-clocks"; - #clock-cells = <1>; - }; - - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BT_ON", - "WL_ON", - "PWR_LED_OFF", - "GLOBAL_RESET", - "VDD_SD_IO_SEL", - "CAM_GPIO", - "SD_PWR_ON", - ""; - status = "okay"; - }; - - reset: reset { - compatible = "raspberrypi,firmware-reset"; - #reset-cells = <1>; - }; +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_OFF", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + ""; }; &gpio { @@ -180,23 +149,13 @@ }; &hdmi0 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - wifi-2.4ghz-coexistence; status = "okay"; }; &hdmi1 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - wifi-2.4ghz-coexistence; status = "okay"; }; -&hvs { - clocks = <&firmware_clocks 4>; -}; - &pixelvalve0 { status = "okay"; }; @@ -219,22 +178,6 @@ status = "okay"; }; -&rmem { - /* - * RPi4's co-processor will copy the board's bootloader configuration - * into memory for the OS to consume. It'll also update this node with - * its placement information. - */ - blconfig: nvram@0 { - compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x0>; - no-map; - status = "disabled"; - }; -}; - /* SDHCI is used to control the SDIO for wireless */ &sdhci { #address-cells = <1>; @@ -309,10 +252,6 @@ status = "okay"; }; -&vchiq { - interrupts = ; -}; - &vc4 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi new file mode 100644 index 00000000000000..ca266c5d9f9bb2 --- /dev/null +++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2835-rpi.dtsi" + +#include + +/ { + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0>; + }; + + aliases { + emmc2bus = &emmc2bus; + ethernet0 = &genet; + pcie0 = &pcie0; + blconfig = &blconfig; + }; +}; + +&firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; +}; + +&hdmi0 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hdmi1 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hvs { + clocks = <&firmware_clocks 4>; +}; + +&rmem { + /* + * RPi4's co-processor will copy the board's bootloader configuration + * into memory for the OS to consume. It'll also update this node with + * its placement information. + */ + blconfig: nvram@0 { + compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x0>; + no-map; + status = "disabled"; + }; +}; + +&vchiq { + interrupts = ; +}; From e1428350340d426a61df927432c8bcc2812425ac Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 May 2021 10:28:42 +0200 Subject: [PATCH 338/511] ARM: dts: imx6dl-prtvt7: add TSC2046 touchscreen node Add touchscreen support to the Protonic VT7 board. Co-Developed-by: Robin van der Gracht Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtvt7.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index ae6da241f13e5c..428ed9f6bc17ad 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -223,6 +223,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; + + touchscreen@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-0 = <&pinctrl_tsc>; + pinctrl-names ="default"; + spi-max-frequency = <100000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + touchscreen-max-pressure = <4095>; + ti,vref-delay-usecs = /bits/ 16 <100>; + ti,x-plate-ohms = /bits/ 16 <800>; + ti,y-plate-ohms = /bits/ 16 <300>; + wakeup-source; + }; }; &i2c1 { From 40610b8134888685708e135edcdbc1601afdd0cf Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 May 2021 10:28:43 +0200 Subject: [PATCH 339/511] ARM: dts: imx6dl-prtvt7: Remove backlight enable gpio The backlight power is controlled through the reg_bl_12v0 regulator. Co-Developed-by: Robin van der Gracht Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtvt7.dts | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 428ed9f6bc17ad..a8e72c7699cdfd 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -21,14 +21,11 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; pwms = <&pwm1 0 500000>; brightness-levels = <0 20 81 248 1000>; default-brightness-level = <20>; num-interpolated-steps = <21>; power-supply = <®_bl_12v0>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; keys { @@ -315,12 +312,6 @@ >; }; - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - pinctrl_can1phy: can1phy { fsl,pins = < /* CAN1_SR */ From 76c32fc24f7d68d0dbcfd02607f20779127c4222 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 May 2021 10:28:44 +0200 Subject: [PATCH 340/511] ARM: dts: imx6dl-prtvt7: fix PWM cell count for the backlight node. At some point PWM cell count was changed, but it didn't triggered any error, since this DT was overwriting "#pwm-cells". To make sure, we are in sync with the kernel driver, remove this property and fix the pwm consumer. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtvt7.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index a8e72c7699cdfd..d22ded6fc48b4f 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -21,7 +21,7 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pwms = <&pwm1 0 500000>; + pwms = <&pwm1 0 500000 0>; brightness-levels = <0 20 81 248 1000>; default-brightness-level = <20>; num-interpolated-steps = <21>; @@ -273,7 +273,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From e6d762b0a6aad7af6db436cd3932ae9b79c569ca Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 May 2021 10:28:45 +0200 Subject: [PATCH 341/511] ARM: dts: imx6dl-plym2m: remove touchscreen-size-* properties Remove touchscreen-size-* properties. This values are not correct, event if it works with ts_test tool, it fails to work properly with weston. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-plym2m.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index 4d0d3d3386afc8..c97274f0df07e4 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -138,8 +138,6 @@ interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; touchscreen-max-pressure = <4095>; From 6f64e703ce8c49b52c0149df2c0ebac8ec298f9f Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 May 2021 10:28:46 +0200 Subject: [PATCH 342/511] ARM: dts: imx6dl: enable touchscreen debounce filter on PLYM2M and PRTVT7 boards Activate low-pass/debounce filter on the touchscreen. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-plym2m.dts | 4 +++- arch/arm/boot/dts/imx6dl-prtvt7.dts | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index c97274f0df07e4..60fe5f14666eaf 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -145,7 +145,9 @@ ti,vref-delay-usecs = /bits/ 16 <100>; ti,x-plate-ohms = /bits/ 16 <800>; ti,y-plate-ohms = /bits/ 16 <300>; - + ti,debounce-max = /bits/ 16 <3>; + ti,debounce-tol = /bits/ 16 <70>; + ti,debounce-rep = /bits/ 16 <3>; wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index d22ded6fc48b4f..1626f3704f1b11 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -233,6 +233,9 @@ ti,vref-delay-usecs = /bits/ 16 <100>; ti,x-plate-ohms = /bits/ 16 <800>; ti,y-plate-ohms = /bits/ 16 <300>; + ti,debounce-max = /bits/ 16 <3>; + ti,debounce-tol = /bits/ 16 <70>; + ti,debounce-rep = /bits/ 16 <3>; wakeup-source; }; }; From 65ce746ec1dce43511209b808ba124c01fa0a84b Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Tue, 18 May 2021 10:28:47 +0200 Subject: [PATCH 343/511] ARM: dts: imx6dl-prtvt7: Enable the VPU Enable Video Processing Unit to make accelerated video decoding work. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtvt7.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 1626f3704f1b11..9b05abe3198f38 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -299,10 +299,6 @@ status = "disabled"; }; -&vpu { - status = "disabled"; -}; - &iomuxc { pinctrl_audmux: audmuxgrp { fsl,pins = < From 913dca88a15ff30ab710505d806771501bbb977e Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 May 2021 10:28:48 +0200 Subject: [PATCH 344/511] ARM: dts: imx6qdl-vicut1: add interrupt-counter nodes interrupt-counter is mainline now, so we can add missing counter nodes. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 41 ++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index eb25d21a2aceed..b9e305774fedad 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -40,6 +40,27 @@ }; }; + counter-0 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter0>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + counter-1 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + counter-2 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter2>; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -254,7 +275,7 @@ &gpio2 { gpio-line-names = - "", "", "", "", "", "", "", "", + "count0", "count1", "count2", "", "", "", "", "", "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", "", "", "", "", "", "", "", "ON_SWITCH", @@ -572,6 +593,24 @@ >; }; + pinctrl_counter0: counter0grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 + >; + }; + + pinctrl_counter1: counter1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 + >; + }; + + pinctrl_counter2: counter2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 From a616f385a1ef02870f99bffc286ceb75f33a73ff Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Tue, 18 May 2021 10:28:49 +0200 Subject: [PATCH 345/511] ARM: dts: imx6dl-prtvt7: The sgtl5000 uses i2s not ac97 According to Documentation/devicetree/bindings/sound/fsl,ssi.txt 'fsl,mode' should be specified for AC97 mode only. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtvt7.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 9b05abe3198f38..ea6719e2dff93b 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -291,7 +291,6 @@ &ssi1 { #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; status = "okay"; }; From 015511e2b69dc3060d0a92fdc762f1754743ffe8 Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Tue, 18 May 2021 10:28:50 +0200 Subject: [PATCH 346/511] ARM: dts: imx6dl-prtvt7: Remove unused 'sound-dai-cells' from ssi1 node The 'fsl,ssi' documentation doesn't say anything about specifying this. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtvt7.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index ea6719e2dff93b..190d26642bc846 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -290,7 +290,6 @@ }; &ssi1 { - #sound-dai-cells = <0>; status = "okay"; }; From ff62b09d46cffc8c43649539c304050578371de9 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Tue, 8 Jun 2021 16:19:48 +0530 Subject: [PATCH 347/511] arm64: tegra: Audio graph sound card for Jetson Xavier NX Enable support for audio-graph based sound card on Jetson Xavier NX. Following I/O interfaces are enabled. - I2S3 and I2S5 - DMIC1, DMIC2 and DMIC4 - DSPK1 and DSPK2 Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 593 ++++++++++++++++++ 1 file changed, 593 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index a717d2b6613148..836a7e0a426779 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -15,6 +15,577 @@ interrupt-controller@2a40000 { status = "okay"; }; + + ahub@2900800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + + xbar_i2s5_port: port@18 { + reg = <0x18>; + + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + + xbar_dmic4_port: port@1d { + reg = <0x1d>; + + xbar_dmic4_ep: endpoint { + remote-endpoint = <&dmic4_cif_ep>; + }; + }; + + xbar_dspk1_port: port@1e { + reg = <0x1e>; + + xbar_dspk1_ep: endpoint { + remote-endpoint = <&dspk1_cif_ep>; + }; + }; + + xbar_dspk2_port: port@1f { + reg = <0x1f>; + + xbar_dspk2_ep: endpoint { + remote-endpoint = <&dspk2_cif_ep>; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + i2s@2901200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; + }; + + i2s5_port: port@1 { + reg = <1>; + + i2s5_dap_ep: endpoint@0 { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic4_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic4_ep>; + }; + }; + + dmic4_port: port@1 { + reg = <1>; + + dmic4_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; + }; + + dspk2_port: port@1 { + reg = <1>; + + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + }; }; ddc: i2c@3190000 { @@ -265,6 +836,28 @@ regulator-boot-on; }; + sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* XBAR Ports */ + <&xbar_i2s3_port>, <&xbar_i2s5_port>, + <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>, + <&xbar_dspk1_port>, <&xbar_dspk2_port>, + /* BE I/O Ports */ + <&i2s3_port>, <&i2s5_port>, + <&dmic1_port>, <&dmic2_port>, <&dmic4_port>, + <&dspk1_port>, <&dspk2_port>; + + label = "NVIDIA Jetson Xavier NX APE"; + }; + thermal-zones { cpu { polling-delay = <0>; From 5c6d0b55b46aeb91355e6a9616decf50a3778c91 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 20:04:24 +0530 Subject: [PATCH 348/511] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Rename the external refclk inputs to the SERDES from dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1 respectively. Also move the external refclk DT nodes outside the cbass_main DT node. Since in j721e common processor board, only the cmn_refclk1 is connected to 100MHz clock, fix the clock frequency. Fixes: afd094ebe69f ("arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes") Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603143427.28735-2-kishon@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 4 ++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 58 ++++++++++--------- 2 files changed, 34 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 1991f620d94b2e..498e31052a2b40 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -635,6 +635,10 @@ status = "disabled"; }; +&cmn_refclk1 { + clock-frequency = <100000000>; +}; + &serdes0 { serdes0_pcie_link: link@0 { reg = <0>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 598613876b0f11..cc3428f99b9a38 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -8,6 +8,20 @@ #include #include +/ { + cmn_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cmn_refclk1: clock-cmnrefclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -338,24 +352,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; - dummy_cmn_refclk: dummy-cmn-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - dummy_cmn_refclk1: dummy-cmn-refclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; @@ -364,21 +366,21 @@ ranges = <0x5000000 0x0 0x5000000 0x10000>; wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll0_refclk>; assigned-clock-parents = <&k3_clks 292 11>; }; wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&k3_clks 292 0>; }; wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&k3_clks 292 11>; @@ -412,7 +414,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; @@ -421,21 +423,21 @@ ranges = <0x5010000 0x0 0x5010000 0x10000>; wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 13>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll0_refclk>; assigned-clock-parents = <&k3_clks 293 13>; }; wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&k3_clks 293 0>; }; wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&k3_clks 293 13>; @@ -469,7 +471,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; @@ -478,21 +480,21 @@ ranges = <0x5020000 0x0 0x5020000 0x10000>; wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll0_refclk>; assigned-clock-parents = <&k3_clks 294 11>; }; wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll1_refclk>; assigned-clock-parents = <&k3_clks 294 0>; }; wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_refclk_dig>; assigned-clock-parents = <&k3_clks 294 11>; @@ -526,7 +528,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; @@ -535,21 +537,21 @@ ranges = <0x5030000 0x0 0x5030000 0x10000>; wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 9>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll0_refclk>; assigned-clock-parents = <&k3_clks 295 9>; }; wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll1_refclk>; assigned-clock-parents = <&k3_clks 295 0>; }; wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_refclk_dig>; assigned-clock-parents = <&k3_clks 295 9>; From 2427bfb335eb5f291a821e91c4c520351ce933df Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 20:04:25 +0530 Subject: [PATCH 349/511] arm64: dts: ti: k3-j721e-main: Add #clock-cells property to serdes DT node Add #clock-cells property to serdes DT node since the serdes is also now modeled as a clock provider and include the input clocks "pll0_refclk" and "pll1_refclk" which are parents to the clocks modeled by serdes. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603143427.28735-3-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index cc3428f99b9a38..2ce17cafffe214 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -402,10 +402,13 @@ reg = <0x5000000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz0 0>; reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, + <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -459,10 +462,13 @@ reg = <0x5010000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz1 0>; reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, + <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -516,10 +522,13 @@ reg = <0x5020000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz2 0>; reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, + <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -573,10 +582,13 @@ reg = <0x5030000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz3 0>; reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, + <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; From f2a7657ad7a821de9cc77d071a5587b243144cd5 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 20:04:26 +0530 Subject: [PATCH 350/511] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Use external clock for all the SERDES used by PCIe controller. This will make the same clock used by the local SERDES as well as the clock provided to the PCIe connector. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603143427.28735-4-kishon@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 498e31052a2b40..8e7e013f9fffea 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -9,6 +9,7 @@ #include #include #include +#include / { chosen { @@ -639,7 +640,40 @@ clock-frequency = <100000000>; }; +&wiz0_pll1_refclk { + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz0_refclk_dig { + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_pll1_refclk { + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_refclk_dig { + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_pll1_refclk { + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_refclk_dig { + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + &serdes0 { + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz0_pll1_refclk>; + serdes0_pcie_link: link@0 { reg = <0>; cdns,num-lanes = <1>; @@ -650,6 +684,9 @@ }; &serdes1 { + assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz1_pll1_refclk>; + serdes1_pcie_link: link@0 { reg = <0>; cdns,num-lanes = <2>; @@ -660,6 +697,9 @@ }; &serdes2 { + assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz2_pll1_refclk>; + serdes2_pcie_link: link@0 { reg = <0>; cdns,num-lanes = <2>; From 02b4d9186121d842a53e347f53a86ec7f2c6b0c7 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 20:04:27 +0530 Subject: [PATCH 351/511] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") and commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") added PHY DT nodes with node name as "link" However nodes with #phy-cells should be named 'phy' as discussed in [1]. Re-name subnodes of serdes in J721E to 'phy'. [1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances") Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0") Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603143427.28735-5-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 8e7e013f9fffea..8bd02d9e28ad3c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -359,7 +359,7 @@ }; &serdes3 { - serdes3_usb_link: link@0 { + serdes3_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -674,7 +674,7 @@ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; assigned-clock-parents = <&wiz0_pll1_refclk>; - serdes0_pcie_link: link@0 { + serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -687,7 +687,7 @@ assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; assigned-clock-parents = <&wiz1_pll1_refclk>; - serdes1_pcie_link: link@0 { + serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -700,7 +700,7 @@ assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; assigned-clock-parents = <&wiz2_pll1_refclk>; - serdes2_pcie_link: link@0 { + serdes2_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; From 68fefbfed8ba67957b4ab18be4dfb8051b625321 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 19:52:47 +0530 Subject: [PATCH 352/511] arm64: dts: ti: k3-am64-main: Add SERDES DT node AM64 has one SERDES 10G instance. Add SERDES DT node for it. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603142251.14563-2-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index ca59d1f711f8ae..312fcf0f6b9836 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { oc_sram: sram@70000000 { compatible = "mmio-sram"; @@ -18,6 +29,20 @@ }; }; + main_conf: syscon@43000000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x0 0x43000000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x43000000 0x20000>; + + serdes_ln_ctrl: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -673,4 +698,40 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; }; + + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + + assigned-clocks = <&k3_clks 162 1>; + assigned-clock-parents = <&k3_clks 162 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 162 1>, + <&k3_clks 162 1>, + <&k3_clks 162 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + }; + }; }; From 4a868bffd876086d9017753a2d5c88a118fe6d5a Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 19:52:48 +0530 Subject: [PATCH 353/511] arm64: dts: ti: k3-am64-main: Add PCIe DT node AM64 has one PCIe instance which can be configured in either host mode (RC) or device mode (EP). Add PCIe DT node for host mode and device mode here. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603142251.14563-3-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 312fcf0f6b9836..effb9d2e3c25c6 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -734,4 +734,50 @@ #clock-cells = <1>; }; }; + + pcie0_rc: pcie@f102000 { + compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + max-link-speed = <2>; + num-lanes = <1>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + cdns,no-bar-match-nbits = <64>; + vendor-id = <0x104c>; + device-id = <0xb010>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; + }; + + pcie0_ep: pcie-ep@f102000 { + compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + max-link-speed = <2>; + num-lanes = <1>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <1>; + }; }; From 354065bed2d15f6ff7796c8105133ccdf3a84917 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 19:52:49 +0530 Subject: [PATCH 354/511] arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES AM642 EVM has a x4 lane PCIe connector. Enable PCIe in RC mode here. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603142251.14563-4-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index dad0efa961ed11..8c27f563a390b3 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include +#include #include #include #include @@ -466,3 +468,31 @@ &mailbox0_cluster7 { status = "disabled"; }; + +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; From 4e8aa4e3559a7f71e333b0fb8661f302aec64c5c Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 19:52:50 +0530 Subject: [PATCH 355/511] arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port Enable USB Super-Speed HOST port. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Aswath Govindraju Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603142251.14563-5-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 8424cd07195559..077b87656fbc24 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include +#include #include #include #include "k3-am642.dtsi" @@ -85,6 +87,12 @@ >; }; + main_usb0_pins_default: main-usb0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -235,6 +243,33 @@ disable-wp; }; +&serdes_ln_ctrl { + idle-states = ; +}; + +&serdes0 { + serdes0_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "host"; + maximum-speed = "super-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins_default>; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&mdio1_pins_default From c90ec93d94f2bddf3873f2dfbc7b4859e09c01ef Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 3 Jun 2021 19:52:51 +0530 Subject: [PATCH 356/511] arm64: dts: ti: k3-am642-sk: Disable PCIe AM642-SK has no PCIe slot. Disable it here. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Aswath Govindraju Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210603142251.14563-6-kishon@ti.com --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 077b87656fbc24..40124007259d2f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -367,3 +367,11 @@ &mailbox0_cluster7 { status = "disabled"; }; + +&pcie0_rc { + status = "disabled"; +}; + +&pcie0_ep { + status = "disabled"; +}; From 224bd597a4f37a918c492be35aac1ccf4b8507f4 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 6 Jun 2021 14:16:14 +0200 Subject: [PATCH 357/511] dt-bindings: arm: bcm2835: Add Raspberry Pi 400 to DT schema Add new Raspberry Pi 400 to DT schema. Signed-off-by: Stefan Wahren Acked-by: Rob Herring Link: https://lore.kernel.org/r/1622981777-5023-5-git-send-email-stefan.wahren@i2se.com Signed-off-by: Nicolas Saenz Julienne --- Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 812ae8cc595981..230b80d9d6cfc1 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -18,6 +18,7 @@ properties: - description: BCM2711 based Boards items: - enum: + - raspberrypi,400 - raspberrypi,4-model-b - const: brcm,bcm2711 From 5f30dacf37bc93308e91e4d0fc94681ca73f0f91 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 6 Jun 2021 14:16:15 +0200 Subject: [PATCH 358/511] ARM: dts: bcm283x: Fix up GPIO LED node names Fix the node names for the GPIO LEDs to conform to the standard node name led-.. Signed-off-by: Stefan Wahren Link: https://lore.kernel.org/r/1622981777-5023-6-git-send-email-stefan.wahren@i2se.com Signed-off-by: Nicolas Saenz Julienne --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-a.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-b.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi | 2 +- arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 +- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 4 ++-- arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi | 2 +- 15 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index c54854a1776e0d..f24bdd0870a521 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -14,11 +14,11 @@ }; leds { - act { + led-act { gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 6c8ce39833bf68..40b9405f1a8e43 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -14,11 +14,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 17fdd48346ffbb..11edb581dbaf0b 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -14,7 +14,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index b0355c229cdc21..1b435c64bd9c18 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -15,11 +15,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index 33b3b5c0252190..a23c25c00eea7c 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -15,7 +15,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 2b69957e0113ee..1b63d6b19750bf 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -15,7 +15,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi index 58059c2ce1294a..e4e6b6abbfc133 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi @@ -5,7 +5,7 @@ / { leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index f65448c01e317b..33b2b77aa47db3 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -23,7 +23,7 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 6dd93c6f496665..6f9b3a908f287f 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -18,7 +18,7 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index d94357b21f7e9d..87ddcad7608345 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -4,7 +4,7 @@ leds { compatible = "gpio-leds"; - act { + led-act { label = "ACT"; default-state = "keep"; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 0455a680394a22..d8af8eeac7b6f9 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -15,11 +15,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index 28be0332c1c810..77099a7871b03b 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -19,11 +19,11 @@ }; leds { - act { + led-act { gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 37343148643dbf..61010266ca9a3b 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -20,11 +20,11 @@ }; leds { - act { + led-act { gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 054ecaa355c9ab..dd4a4860409713 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -20,7 +20,7 @@ }; leds { - act { + led-act { gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 925cb37c22f06b..828a20561b9694 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -14,7 +14,7 @@ * Since there is no upstream GPIO driver yet, * remove the incomplete node. */ - /delete-node/ act; + /delete-node/ led-act; }; reg_3v3: fixed-regulator { From 1c701accecf21932ebcbd8acacb4557af3797e77 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 6 Jun 2021 14:16:16 +0200 Subject: [PATCH 359/511] ARM: dts: Add Raspberry Pi 400 support The Raspberry Pi 400 is like a Pi 4 B designed into a keyboard. But there are some minor differences: - higher CPU clock rate (1.8 GHz) - different Wifi chip (BCM43456) - power off is now handled via GPIO - no ACT LED Signed-off-by: Stefan Wahren Link: https://lore.kernel.org/r/1622981777-5023-7-git-send-email-stefan.wahren@i2se.com Signed-off-by: Nicolas Saenz Julienne --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm2711-rpi-400.dts | 45 +++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2711-rpi-400.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e750..ec00dba84f3609 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ + bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2835-rpi-zero.dtb \ bcm2835-rpi-zero-w.dtb diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts new file mode 100644 index 00000000000000..f4d2fc20397c70 --- /dev/null +++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2711-rpi-4-b.dts" + +/ { + compatible = "raspberrypi,400", "brcm,bcm2711"; + model = "Raspberry Pi 400"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + leds { + /delete-node/ led-act; + + led-pwr { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + "SD_OC_N"; +}; + +&genet_mdio { + clock-frequency = <1950000>; +}; + +&pm { + /delete-property/ system-power-controller; +}; From 21c6bf8304f0141af6460cfe404dbbdeb96bdd62 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 6 Jun 2021 14:16:17 +0200 Subject: [PATCH 360/511] arm64: dts: broadcom: Add reference to RPi 400 This adds a reference to the dts of the Raspberry Pi 400, so we don't need to maintain the content in arm64. Signed-off-by: Stefan Wahren Reviewed-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/1622981777-5023-8-git-send-email-stefan.wahren@i2se.com Signed-off-by: Nicolas Saenz Julienne --- arch/arm64/boot/dts/broadcom/Makefile | 3 ++- arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 998e240aa69874..11eae3e3a9447a 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \ +dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ + bcm2711-rpi-4-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts new file mode 100644 index 00000000000000..b9000f58beb559 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/bcm2711-rpi-400.dts" From 4fa8492d1e5b11fd810bd746c301fca39c18025d Mon Sep 17 00:00:00 2001 From: Ikjoon Jang Date: Wed, 9 Jun 2021 11:25:54 +0800 Subject: [PATCH 361/511] arm64: dts: mt8183: add cbas node under cros_ec Add a 'cbas' device node for supporting tablet mode switch in kukui devices. Kukui platforms with detacheable base have an additional input device under cros-ec, which reports SW_TABLET_MODE regarding its base state (e.g. base flipped or detached). Signed-off-by: Ikjoon Jang Reviewed-by: Enric Balletbo i Serra Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20210609032554.2443675-1-ikjn@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index ff56bcfa337036..1512605a438ef2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -816,6 +816,10 @@ compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <0>; }; + + cbas { + compatible = "google,cros-cbas"; + }; }; }; From 507b1b28129974691b95d623f78d0604fbaeea09 Mon Sep 17 00:00:00 2001 From: Michael Kao Date: Fri, 4 Jun 2021 17:37:55 +0800 Subject: [PATCH 362/511] arm64: dts: mt8183-kukui: Add tboard thermal zones Add tboard thermal zones. The tboard thermal sensors are a kind of NTC sensors which are located on PCB board to correlate the temperature of the case (Tskin). pull-up voltage: 1800 mv pull-up resistor: 75K Vsense = pull-up voltage * Rntc / ( pull-up resistor + Rntc ) AuxIn = Vsense * 4096 / 1500 Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Tested-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210604093755.13288-1-ben.tseng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 1512605a438ef2..ebcab91d219a69 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -851,6 +851,20 @@ status = "okay"; }; +&thermal_zones { + tboard1 { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&tboard_thermistor1>; + }; + + tboard2 { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&tboard_thermistor2>; + }; +}; + &u3phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index e074c0d402ff72..833955d0ea3c5c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -673,7 +673,7 @@ nvmem-cell-names = "calibration-data"; }; - thermal-zones { + thermal_zones: thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <100>; polling-delay = <500>; From 70010556b158a0fefe43415fb0c58347dcce7da0 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Tue, 8 Jun 2021 15:51:33 +0100 Subject: [PATCH 363/511] arm64: dts: juno: Update SCPI nodes as per the YAML schema The SCPI YAML schema expects standard node names for clocks and power domain controllers. Fix those as per the schema for Juno platforms. Link: https://lore.kernel.org/r/20210608145133.2088631-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 1cc7fdcec51bcc..8e7a66943b0180 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -568,13 +568,13 @@ clocks { compatible = "arm,scpi-clocks"; - scpi_dvfs: scpi-dvfs { + scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>, <1>, <2>; clock-output-names = "atlclk", "aplclk","gpuclk"; }; - scpi_clk: scpi-clk { + scpi_clk: clocks-1 { compatible = "arm,scpi-variable-clocks"; #clock-cells = <1>; clock-indices = <3>; @@ -582,7 +582,7 @@ }; }; - scpi_devpd: scpi-power-domains { + scpi_devpd: power-controller { compatible = "arm,scpi-power-domains"; num-domains = <2>; #power-domain-cells = <1>; From a8168cebf1bca1b5269e8a7eb2626fb76814d6e2 Mon Sep 17 00:00:00 2001 From: Nicolas Boichat Date: Fri, 21 May 2021 20:00:41 +0800 Subject: [PATCH 364/511] arm64: dts: mt8183: Add node for the Mali GPU Add a basic GPU node for mt8183, as well as OPP table. Note that with the current panfrost driver, devfreq is not actually functional, as the we do not have platform-specific support for >1 supplies. Also, we are missing code to handle frequency change, as the GPU frequency needs to be switched away to a stable 26Mhz clock during the transition. Signed-off-by: Nicolas Boichat Link: https://lore.kernel.org/r/20210521200038.v14.1.I9f45f5c1f975422d58b5904d11546349e9ccdc94@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 5 + .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 5 + .../boot/dts/mediatek/mt8183-pumpkin.dts | 5 + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 ++++++++++++++++++ 4 files changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index edff1e03e6fee9..7bc0a6a7fadf9c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -42,6 +42,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c_pins_0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index ebcab91d219a69..ae549d55a94fcd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -279,6 +279,11 @@ }; }; +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 0aff5eb52e8876..ee912825cfc606 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -68,6 +68,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c_pins_0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 833955d0ea3c5c..f90df6439c0880 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -197,6 +197,91 @@ }; }; + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <625000>, <850000>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + opp-microvolt = <631250>, <850000>; + }; + + opp-340000000 { + opp-hz = /bits/ 64 <340000000>; + opp-microvolt = <637500>, <850000>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + opp-microvolt = <643750>, <850000>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + opp-microvolt = <650000>, <850000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <656250>, <850000>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <662500>, <850000>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + opp-microvolt = <675000>, <850000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <687500>, <850000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <700000>, <850000>; + }; + + opp-580000000 { + opp-hz = /bits/ 64 <580000000>; + opp-microvolt = <712500>, <850000>; + }; + + opp-620000000 { + opp-hz = /bits/ 64 <620000000>; + opp-microvolt = <725000>, <850000>; + }; + + opp-653000000 { + opp-hz = /bits/ 64 <653000000>; + opp-microvolt = <743750>, <850000>; + }; + + opp-698000000 { + opp-hz = /bits/ 64 <698000000>; + opp-microvolt = <768750>, <868750>; + }; + + opp-743000000 { + opp-hz = /bits/ 64 <743000000>; + opp-microvolt = <793750>, <893750>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <825000>, <925000>; + }; + }; + pmu-a53 { compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; @@ -1118,6 +1203,26 @@ #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + interrupts = + , + , + ; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&topckgen CLK_TOP_MFGPLL_CK>; + + power-domains = + <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, + <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, + <&spm MT8183_POWER_DOMAIN_MFG_2D>; + power-domain-names = "core0", "core1", "core2"; + + operating-points-v2 = <&gpu_opp_table>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; From f07edc41220b14ce057a4e6d7161b30688ddb8a2 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sun, 6 Jun 2021 20:16:32 +0200 Subject: [PATCH 365/511] ARM: dts: rockchip: fix supply properties in io-domains nodes A test with rockchip-io-domain.yaml gives notifications for supply properties in io-domains nodes. Fix them all into ".*-supply$" format. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210606181632.13371-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 2 +- arch/arm/boot/dts/rk3288-vyasa.dts | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index 44bb5e6f83b12d..76363b8afcb9b4 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -218,7 +218,7 @@ flash0-supply = <&vcc_flash>; flash1-supply = <&vccio_pmu>; gpio30-supply = <&vccio_pmu>; - gpio1830 = <&vcc_io>; + gpio1830-supply = <&vcc_io>; lcdc-supply = <&vcc_io>; sdcard-supply = <&vccio_sd>; wifi-supply = <&vcc_18>; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index aa50f8ed4ca0a0..b156a83eb7d785 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -379,10 +379,10 @@ audio-supply = <&vcc_18>; bb-supply = <&vcc_io>; dvp-supply = <&vcc_io>; - flash0-suuply = <&vcc_18>; + flash0-supply = <&vcc_18>; flash1-supply = <&vcc_lan>; gpio30-supply = <&vcc_io>; - gpio1830 = <&vcc_io>; + gpio1830-supply = <&vcc_io>; lcdc-supply = <&vcc_io>; sdcard-supply = <&vccio_sd>; wifi-supply = <&vcc_18>; From a52c468a9526dfe2f9a5d3c99f5dd362d0b5e3f4 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:29 +0200 Subject: [PATCH 366/511] ARM: dts: stm32: update pinctrl node name on STM32 MCU to prevent warnings Update node name to avoid a DT schema validation issue seen with "make dtbs_check W=1". It also cleans picntrl dtsi files for f429/f469 MCU. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 2 +- arch/arm/boot/dts/stm32f429-pinctrl.dtsi | 72 +++++++++++------------ arch/arm/boot/dts/stm32f469-pinctrl.dtsi | 74 +++++++++++------------- arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 2 +- 4 files changed, 71 insertions(+), 79 deletions(-) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 4774163af54bb1..155d9ffacc8341 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -45,7 +45,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pin-controller@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi index 3e7a17d9112e1c..e10d7a1f320797 100644 --- a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi @@ -42,54 +42,50 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f429-pinctrl"; +&pinctrl { + compatible = "st,stm32f429-pinctrl"; - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 16>; - }; + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 0 160 8>; - }; - }; + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; }; }; diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi index fff542662eeaa3..6bf60263dff895 100644 --- a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi @@ -42,55 +42,51 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f469-pinctrl"; +&pinctrl { + compatible = "st,stm32f469-pinctrl"; - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 6>, - <&pinctrl 12 156 4>; - }; + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 6>, + <&pinctrl 12 156 4>; + }; - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 3 163 5>; - }; - }; + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 3 163 5>; }; }; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index fe4cfda72a4766..1cf8a23c264482 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pin-controller@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; From ad0ed10ba5792064fc3accbf8f0341152a57eecb Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:30 +0200 Subject: [PATCH 367/511] ARM: dts: stm32: fix i2c node name on stm32f746 to prevent warnings Replace upper case by lower case in i2c nodes name. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f746.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 72c1b76684b6a9..014b416f57e6fb 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -360,9 +360,9 @@ status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; - reg = <0x40005C00 0x400>; + reg = <0x40005c00 0x400>; interrupts = <72>, <73>; resets = <&rcc STM32F7_APB1_RESET(I2C3)>; From fb1406335c067be074eab38206cf9abfdce2fb0b Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:31 +0200 Subject: [PATCH 368/511] ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15 It fixes the following warning seen running "make dtbs_check W=1" Warning (simple_bus_reg): /soc/stmmac-axi-config: missing or empty reg/ranges property Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 3f74d13995acd1..bd289bf5d26900 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1416,12 +1416,6 @@ status = "disabled"; }; - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - ethernet0: ethernet@5800a000 { compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; @@ -1447,6 +1441,12 @@ snps,axi-config = <&stmmac_axi_config_0>; snps,tso; status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; }; usbh_ohci: usb@5800c000 { From fea99822914039c690a5322dd33d5abdc7c27ea3 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:32 +0200 Subject: [PATCH 369/511] dt-bindings: net: document ptp_ref clk in dwmac ptp_ref clk has been added in DT but not documented which makes yaml validation failed: ethernet@5800a000: clocks: [[6, 105], [6, 103], [6, 104], [6, 123], [6, 169], [6, 112]] is too long ethernet@5800a000: clock-names: ['stmmaceth', 'mac-clk-tx', 'mac-clk-rx', 'eth-ck', 'ptp_ref', 'ethstp'] is too long Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 27eb6066793f2a..a1c490f3af02d6 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -46,17 +46,18 @@ properties: clocks: minItems: 3 - maxItems: 5 + maxItems: 6 items: - description: GMAC main clock - description: MAC TX clock - description: MAC RX clock - description: For MPU family, used for power mode - description: For MPU family, used for PHY without quartz + - description: PTP clock clock-names: minItems: 3 - maxItems: 5 + maxItems: 6 contains: enum: - stmmaceth @@ -64,6 +65,7 @@ properties: - mac-clk-rx - ethstp - eth-ck + - ptp_ref st,syscon: $ref: "/schemas/types.yaml#/definitions/phandle-array" From 11aaf2a0f8f070e87833775965950157bf57e49a Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:37 +0200 Subject: [PATCH 370/511] ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7 It prevents the following warning: pin-controller@50002000: 'ltdc' does not match any of the regexes: '-[0-9]*$', '^gpio@[0-9a-f]*$', 'pinctrl-[0-9]+' Signed-off-by: Alexandre Torgue --- .../boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 674b2d330dc41f..5670b23812a216 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -89,7 +89,7 @@ }; &pinctrl { - ltdc_pins: ltdc { + ltdc_pins: ltdc-0 { pins { pinmux = , /* LTDC_B2 */ , /* LTDC_R6 */ From 305b80780879117b3448da42afe95af312393fbd Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 16:32:20 +0100 Subject: [PATCH 371/511] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC Add device tree bindings documentation for Renesas RZ/G2UL SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Chris Paterson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210609153230.6967-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 5fd0696a9f91f3..3b79108b49a083 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -302,6 +302,13 @@ properties: - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - const: renesas,r9a06g032 + - description: RZ/G2UL (R9A07G043) + items: + - enum: + - renesas,r9a07g043u11 # RZ/G2UL Type-1 + - renesas,r9a07g043u12 # RZ/G2UL Type-2 + - const: renesas,r9a07g043 + additionalProperties: true ... From 2cd22416745fe1f0f6b6fa70c09438f85e20c693 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 16:32:21 +0100 Subject: [PATCH 372/511] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants Add device tree bindings documentation for Renesas RZ/G2{L,LC} SoC variants. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Chris Paterson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210609153230.6967-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 3b79108b49a083..0f99408960d73b 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -309,6 +309,15 @@ properties: - renesas,r9a07g043u12 # RZ/G2UL Type-2 - const: renesas,r9a07g043 + - description: RZ/G2{L,LC} (R9A07G044) + items: + - enum: + - renesas,r9a07g044c1 # Single Cortex-A55 RZ/G2LC + - renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC + - renesas,r9a07g044l1 # Single Cortex-A55 RZ/G2L + - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L + - const: renesas,r9a07g044 + additionalProperties: true ... From 4affc072e4fef6d1778f957037f255a6acdd44e2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 16:32:22 +0100 Subject: [PATCH 373/511] dt-bindings: arm: renesas: Document SMARC EVK Document Renesas SMARC EVK board which are based on RZ/G2L (R9A07G044) SoC. The SMARC EVK consists of RZ/G2L SoM module and SMARC carrier board, the SoM module sits on top of carrier board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Chris Paterson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210609153230.6967-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 0f99408960d73b..a0cce4e250398b 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -311,6 +311,8 @@ properties: - description: RZ/G2{L,LC} (R9A07G044) items: + - enum: + - renesas,smarc-evk # SMARC EVK - enum: - renesas,r9a07g044c1 # Single Cortex-A55 RZ/G2LC - renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC From 972f67be8929ac095df6a8bbce738b4f39e984cb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 17:37:15 +0100 Subject: [PATCH 374/511] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller Add DT binding documentation for SYSC controller found on RZ/G2{L,LC,UL} SoC's. SYSC block contains the LSI_DEVID register which is used to retrieve SoC product information. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210609163717.3083-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../bindings/power/renesas,rzg2l-sysc.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml new file mode 100644 index 00000000000000..84ddc772b003e0 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas RZ/G2L System Controller (SYSC) + +maintainers: + - Geert Uytterhoeven + +description: + The RZ/G2L System Controller (SYSC) performs system control of the LSI and + supports following functions, + - External terminal state capture function + - 34-bit address space access function + - Low power consumption control + - WDT stop control + +properties: + compatible: + enum: + - renesas,r9a07g044-sysc # RZ/G2{L,LC} + + reg: + maxItems: 1 + + interrupts: + items: + - description: CA55/CM33 Sleep/Software Standby Mode request interrupt + - description: CA55 Software Standby Mode release request interrupt + - description: CM33 Software Standby Mode release request interrupt + - description: CA55 ACE Asynchronous Bridge Master/Slave interface deny request interrupt + + interrupt-names: + items: + - const: lpm_int + - const: ca55stbydone_int + - const: cm33stbyr_int + - const: ca55_deny + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g044-sysc"; + reg = <0x11020000 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", + "ca55_deny"; + }; From 02814a41529a55dbfb9fbb2a3728e78e70646ea6 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Thu, 3 Jun 2021 17:34:18 +0200 Subject: [PATCH 375/511] ARM: dts: stm32: add a new DCMI pins group on stm32mp15 The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output. stm32mp15-pinctrl.dtsi contained one pin state definition for the DCMI interface, dcmi-0, AKA phandle dcmi_pins_a. This definition was incompatible with the pins used on the Odyssey board, where: - there are 8 data pins instead of 12, - DCMI_HSYNC is available at PA4 instead of PH8, - DCMI_D0 is at PC6 instead of PH9, - DCMI_D3 is at PE1 instead of PH12, - DCMI_D4 is at PE11 instead of PH14, - DCMI_D5 is at PD3 instead of PI4, - DCMI_D6 is at PE13 instead of PB8, - DCMI_D7 is at PB9 instead of PE6. Add the DCMI pins used on the Odyssey board as a new DCMI pin state definition, dcmi-1, AKA phandle dcmi_pins_b. Signed-off-by: Grzegorz Szymaszek Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 060baa8b7e9d4d..5b60ecbd718f0e 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -118,6 +118,39 @@ }; }; + dcmi_pins_b: dcmi-1 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_b: dcmi-sleep-1 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ From 68a45525297b2e9afbd9bba807ddd2c9f69beee6 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 16:32:29 +0100 Subject: [PATCH 376/511] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Add initial DTSI for RZ/G2{L,LC} SoC's. File structure: r9a07g044.dtsi => RZ/G2L family SoC common parts r9a07g044l1.dtsi => RZ/G2L R9A07G044L1 SoC specific parts r9a07g044l2.dtsi => RZ/G2L R9A07G044L2 SoC specific parts Signed-off-by: Lad Prabhakar Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20210609153230.6967-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 120 +++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 25 ++++ arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi | 13 ++ 3 files changed, 158 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi new file mode 100644 index 00000000000000..6a103a62eccbf7 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a07g044"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_CLK_SCIF0>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g044-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi new file mode 100644 index 00000000000000..9d89d4590358ef --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044l1", "renesas,r9a07g044"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi new file mode 100644 index 00000000000000..91dc10b2cdbbc6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044l2", "renesas,r9a07g044"; +}; From 690ea5d394eb370973ffcb9ecda6a1855fe87d01 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 16:32:30 +0100 Subject: [PATCH 377/511] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Add basic support for RZ/G2L SMARC EVK (based on R9A07G044L2): - memory - External input clock - SCIF Signed-off-by: Lad Prabhakar Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20210609153230.6967-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 +++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 27 +++++++++++++++++++ 3 files changed, 50 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index f2de2fa0c8b890..68e30e26564b12 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -62,3 +62,5 @@ dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb + +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts new file mode 100644 index 00000000000000..d3f72ec62f0317 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044l2.dtsi" +#include "rzg2l-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g044l2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi new file mode 100644 index 00000000000000..adcd4f50519e80 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include + +/ { + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&scif0 { + status = "okay"; +}; From 42bbd003910906229cb1dc0eaa812d9cc59e4c77 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 17:37:17 +0100 Subject: [PATCH 378/511] arm64: dts: renesas: r9a07g044: Add SYSC node Add SYSC node to RZ/G2L (R9A07G044) SoC .dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210609163717.3083-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6a103a62eccbf7..734c8adeceba07 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -99,6 +99,18 @@ #power-domain-cells = <0>; }; + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g044-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From f493162319788802b6a49634f7268e691b4c10ec Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Thu, 3 Jun 2021 17:40:48 +0200 Subject: [PATCH 379/511] ARM: dts: stm32: fix the Odyssey SoM eMMC VQMMC supply MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Seeed SoM-STM32MP157C device tree had the eMMC’s (SDMMC2) VQMMC supply set to v3v3 (buck4), the same as the VMMC supply. That was incorrect, as on the SoM, the VQMMC supply is provided from vdd (buck3) instead. Signed-off-by: Grzegorz Szymaszek Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi index 6cf49a0a9e6946..b5601d270c8fb9 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -269,7 +269,7 @@ st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; mmc-ddr-3_3v; status = "okay"; }; From 5247a50c8b53ca214a488da648e1bb35c35c2597 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 10 Jun 2021 02:25:50 +0200 Subject: [PATCH 380/511] ARM: dts: stm32: Drop unused linux,wakeup from touchscreen node on DHCOM SoM Fix the following dtbs_check warning: touchscreen@38: 'linux,wakeup' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: kernel@dh-electronics.com Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index b8c8f0b284c314..c5ea08fec535f8 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -187,7 +187,6 @@ reg = <0x38>; interrupt-parent = <&gpiog>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - linux,wakeup; }; }; From b586250df24226f8a257e11e1f5953054c54fd35 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 10 Jun 2021 02:25:51 +0200 Subject: [PATCH 381/511] ARM: dts: stm32: Rename eth@N to ethernet@N on DHCOM SoM Fix the following dtbs_check warning: eth@1,0: $nodename:0: 'eth@1,0' does not match '^ethernet(@.*)?$' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: kernel@dh-electronics.com Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 31d08423a32f09..c3e3466dacaa85 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -150,7 +150,7 @@ pinctrl-1 = <&fmc_sleep_pins_b>; status = "okay"; - ksz8851: ks8851mll@1,0 { + ksz8851: ethernet@1,0 { compatible = "micrel,ks8851-mll"; reg = <1 0x0 0x2>, <1 0x2 0x20000>; interrupt-parent = <&gpioc>; From 9b8a9b389d8464e1ca5a4e92c6a4422844ad4ef3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 10 Jun 2021 02:25:52 +0200 Subject: [PATCH 382/511] ARM: dts: stm32: Rename spi-flash/mx66l51235l@N to flash@N on DHCOM SoM Fix the following dtbs_check warning: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: kernel@dh-electronics.com Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 2 +- arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index c3e3466dacaa85..8f4fd3a06a31dc 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -437,7 +437,7 @@ #size-cells = <0>; status = "okay"; - flash0: mx66l51235l@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 013ae369791d76..2b0ac605549d7d 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -198,7 +198,7 @@ #size-cells = <0>; status = "okay"; - flash0: spi-flash@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; From 4bf4abe19089245b7b12f35e5cafb5477b3e2c48 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:33 +0200 Subject: [PATCH 383/511] ARM: dts: stm32: fix stpmic node for stm32mp1 boards On some STM32 MP15 boards, stpmic node is not correct which generates warnings running "make dtbs_check W=1" command. Issues are: -"regulator-active-discharge" is not a boolean but an uint32. -"regulator-over-current-protection" is not a valid entry for vref_ddr. -LDO4 has a fixed voltage (3v3) so min/max entries are not allowed. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 7 ++----- arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 5 +---- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 5 +---- arch/arm/boot/dts/stm32mp15xx-osd32.dtsi | 7 ++----- 4 files changed, 6 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi index 113c48b2ef93d2..a4b14ef3caeeb9 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -184,8 +184,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -208,7 +206,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -219,13 +216,13 @@ vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi index b5601d270c8fb9..2d9461006810c5 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -173,8 +173,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -197,7 +195,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -213,7 +210,7 @@ vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 8f4fd3a06a31dc..2af0a675267471 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -333,8 +333,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -356,7 +354,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -372,7 +369,7 @@ vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index 713485a95795a4..6706d8311a6655 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -146,8 +146,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -171,7 +169,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -182,13 +179,13 @@ vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; From abbe13a2ffd99168592fc9d987b2427ac7484d51 Mon Sep 17 00:00:00 2001 From: Wenchao Han Date: Mon, 10 May 2021 07:53:12 -0700 Subject: [PATCH 384/511] arm64: dts: qcom: sc7180: Modify SPI_CLK voltage level for trogdor On coachz it could be observed that SPI_CLK voltage level was only 1.4V during active transfers because the drive strength was too weak. The line hadn't finished slewing up by the time we started driving it down again. Using a drive strength of 8 lets us achieve the correct voltage level of 1.8V. Though the worst problems were observed on coachz hardware, let's do this across the board for trogdor devices. Scoping other boards shows that this makes the clk line look nicer on them too and doesn't introduce any problems. Only the clk line is adjusted, not any data lines. Because SPI isn't a DDR protocol we only sample the data lines on either rising or falling edges, not both. That means the clk line needs to toggle twice as fast as data lines so having the higher drive strength is more important there. Signed-off-by: Wenchao Han [dianders: Adjust author real name; adjust commit message] Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20210510075253.1.Ib4c296d6ff9819f26bcaf91e8a08729cc203fed0@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 5c137aa700c0d8..c55ea188e5600e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -978,6 +978,7 @@ ap_spi_fp: &spi10 { &qspi_clk { pinconf { pins = "gpio63"; + drive-strength = <8>; bias-disable; }; }; From d141e0524e8e4381a4e05527e012ce798511618c Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 1 Jun 2021 11:44:17 -0700 Subject: [PATCH 385/511] arm64: dts: qcom: sc7180: Disable PON on Trogdor We don't use the PON module on Trogdor devices. Instead the reboot reason is sort of stored in the 'eventlog' and the bootloader figures out if the boot is abnormal and records that there. Disable the PON node and then drop the power key disabling because that's a child node that will no longer be enabled if the PON node is disabled. Reviewed-by: Douglas Anderson Cc: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20210601184417.3020834-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index c55ea188e5600e..5608e1d311f02c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -802,7 +802,7 @@ hp_i2c: &i2c9 { }; }; -&pm6150_pwrkey { +&pm6150_pon { status = "disabled"; }; From f298167092feb1befe68dab4e896abf9d3c64866 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 1 Jun 2021 11:59:58 -0700 Subject: [PATCH 386/511] arm64: dts: qcom: sc7180: Remove cros-pd-update on Trogdor This compatible string isn't present upstream. Let's drop the node as it isn't used. Reviewed-by: Douglas Anderson Cc: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20210601185959.3101132-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 5608e1d311f02c..797c4cb060256c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -559,10 +559,6 @@ #size-cells = <0>; }; - pdupdate { - compatible = "google,cros-ec-pd-update"; - }; - typec { compatible = "google,cros-ec-typec"; #address-cells = <1>; From 62b837469e995b5981d2842135551935cd32360c Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 1 Jun 2021 11:59:59 -0700 Subject: [PATCH 387/511] arm64: dts: qcom: sdm845: Remove cros-pd-update on Cheza This compatible string isn't present upstream. Let's drop the node as it isn't used. Reviewed-by: Douglas Anderson Cc: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20210601185959.3101132-2-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 216a74f0057c13..dfd1b42c07fd58 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -714,10 +714,6 @@ ap_ts_i2c: &i2c14 { #address-cells = <1>; #size-cells = <0>; }; - - pdupdate { - compatible = "google,cros-ec-pd-update"; - }; }; }; From ba5f9b5d7ff3452e69275080c3d59265bc1db8ea Mon Sep 17 00:00:00 2001 From: Srinivasa Rao Mandadapu Date: Thu, 13 May 2021 17:54:29 +0530 Subject: [PATCH 388/511] arm64: dts: qcom: sc7180: Add wakeup delay for adau codec Add wakeup delay for fixing PoP noise during capture begin. Reviewed-by: Douglas Anderson Signed-off-by: Judy Hsiao Signed-off-by: Srinivasa Rao Mandadapu Link: https://lore.kernel.org/r/20210513122429.25295-1-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 8c1146c5bdfee0..6f9c0714755134 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -23,6 +23,7 @@ ap_h1_spi: &spi0 {}; adau7002: audio-codec-1 { compatible = "adi,adau7002"; IOVDD-supply = <&pp1800_l15a>; + wakeup-delay-ms = <15>; #sound-dai-cells = <0>; }; From 729046d4f1abf341b94d39036ad33506ea9f2c7a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 18 May 2021 22:40:30 -0700 Subject: [PATCH 389/511] arm64: dts: qcom: sc7180-trogdor: Update flash freq to match reality This spi flash part is actually being clocked at 37.5MHz, not 25MHz, because of the way the clk driver is rounding up the rate that is requested to the nearest supported frequency. Let's update the frequency here, and remove the TODO because this is the fastest frequency we're going to be able to use here. Reviewed-by: Douglas Anderson Cc: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20210519054030.3217704-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 797c4cb060256c..77ae7561d436e3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -330,8 +330,7 @@ compatible = "jedec,spi-nor"; reg = <0>; - /* TODO: Increase frequency after testing */ - spi-max-frequency = <25000000>; + spi-max-frequency = <37500000>; spi-tx-bus-width = <2>; spi-rx-bus-width = <2>; }; From 55056b229189be2b4b8e636f0566a0b5bfd3c8f8 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 14 May 2021 12:43:24 +0200 Subject: [PATCH 390/511] arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7 The Huawei Ascend G7 is a smartphone from Huawei based on MSM8916. It's fairly similar to the other MSM8916 devices, the only notable exception are the "cd-gpios" for detecting if a SD card was inserted: It looks like Huawei forgot to re-route this to gpio38, so the correct GPIO seems to be gpio56 on this device. Note: The original firmware from Huawei can only boot 32-bit kernels. To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei forgot to set up (firmware) secure boot for some reason. Also note that Huawei no longer provides bootloader unlock codes. This can be bypassed by patching the bootloader from a custom HYP firmware, making it think the bootloader is unlocked. I use a modified version of qhypstub [1], that patches a single instruction in the Huawei bootloader. The device tree contains initial support for the Huawei Ascend G7 with: - UART (untested, probably available via some test points) - eMMC/SD card - Buttons - Notification LED (combination of 3 GPIO LEDs) - Vibrator - WiFi/Bluetooth (WCNSS) - USB [1]: https://github.com/msm8916-mainline/qhypstub Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210514104328.18756-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 279 ++++++++++++++++++ 2 files changed, 280 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f4276c271d66fc..ec3b2a33eec8a6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts new file mode 100644 index 00000000000000..d67aa7dd4a21d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2021 Stephan Gerhold + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include +#include + +/* + * Note: The original firmware from Huawei can only boot 32-bit kernels. + * To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware + * with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei + * forgot to set up (firmware) secure boot for some reason. + * + * Also note that Huawei no longer provides bootloader unlock codes. + * This can be bypassed by patching the bootloader from a custom HYP firmware, + * making it think the bootloader is unlocked. + * + * See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7) + */ + +/ { + model = "Huawei Ascend G7"; + compatible = "huawei,g7", "qcom,msm8916"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds_default>; + + led-0 { + gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + }; + + led-1 { + gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + }; + + led-2 { + gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>; + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 117 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>; + + /* + * The Huawei device tree sets cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>. + * However, gpio38 does not change its state when inserting/removing the + * SD card, it's just low all the time. The Huawei kernel seems to use + * polling for SD card detection instead. + * + * However, looking closer at the GPIO debug output it turns out that + * gpio56 switches its state when inserting/removing the SD card. + * It behaves just like gpio38 normally does. Usually GPIO56 is used as + * "UIM2_PRESENT", i.e. to check if a second SIM card is inserted. + * Maybe Huawei decided to replace the second SIM card slot with the + * SD card slot and forgot to re-route to gpio38. + */ + cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_keys_default: gpio-keys-default { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + gpio_leds_default: gpio-leds-default { + pins = "gpio8", "gpio9", "gpio10"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_cd_default: sdhc2-cd-default { + pins = "gpio56"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + usb_id_default: usb-id-default { + pins = "gpio117"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; From 918f24ae4597d5a5e3cdfca0fe7aa3ebd345a25b Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 14 May 2021 12:43:25 +0200 Subject: [PATCH 391/511] arm64: dts: qcom: msm8916-huawei-g7: Add touchscreen The Huawei Ascend G7 has a Synaptics "C199HW-006" touchscreen, supplied by pm8916_l17 and pm8916_l16. Add it to the device tree and reduce the maximum allowed voltage for pm8916_l16 to 1.8V since we really should not use more for an I/O supply. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210514104328.18756-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 43 ++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index d67aa7dd4a21d7..f928179f9ded55 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -6,6 +6,7 @@ #include "msm8916-pm8916.dtsi" #include #include +#include #include /* @@ -84,6 +85,38 @@ }; }; +&blsp_i2c5 { + status = "okay"; + + rmi4@70 { + compatible = "syna,rmi4-i2c"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8916_l17>; + vio-supply = <&pm8916_l16>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq_default>; + + syna,startup-delay-ms = <100>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; /* Allow sleeping */ + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; /* Touchscreen */ + }; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -230,7 +263,7 @@ l16 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; }; l17 { @@ -269,6 +302,14 @@ bias-disable; }; + ts_irq_default: ts-irq-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + usb_id_default: usb-id-default { pins = "gpio117"; function = "gpio"; From 3305642dc44bcb85f13129c4214f283f7c3d71a4 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 14 May 2021 12:43:26 +0200 Subject: [PATCH 392/511] arm64: dts: qcom: msm8916-huawei-g7: Add sensors The Huawei Ascend G7 has 3 sensors, all supported by existing kernel drivers: 1. Kionix KX023-1025 accelerometer (kxcjk-1023) 2. Asahi Kasei AK09911 magnetometer (ak8975) 3. Avago APDS9930 proximity/light sensor (tsl2772) Add them to the huawei-g7 device tree. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210514104328.18756-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index f928179f9ded55..3b558dc9e90fe2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -85,6 +85,58 @@ }; }; +&blsp_i2c2 { + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + + vdd-supply = <&pm8916_l17>; + vid-supply = <&pm8916_l6>; + + reset-gpios = <&msmgpio 36 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&mag_reset_default>; + }; + + accelerometer@1e { + compatible = "kionix,kx023-1025"; + reg = <0x1e>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_irq_default>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + + proximity@39 { + compatible = "avago,apds9930"; + reg = <0x39>; + + interrupt-parent = <&msmgpio>; + interrupts = <113 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + led-max-microamp = <100000>; + amstaos,proximity-diodes = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&prox_irq_default>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -278,6 +330,14 @@ }; &msmgpio { + accel_irq_default: accel-irq-default { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default { pins = "gpio107"; function = "gpio"; @@ -294,6 +354,22 @@ bias-disable; }; + mag_reset_default: mag-reset-default { + pins = "gpio36"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + prox_irq_default: prox-irq-default { + pins = "gpio113"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + sdhc2_cd_default: sdhc2-cd-default { pins = "gpio56"; function = "gpio"; From 81c3e08f726921f244e11795a415d2acb5bdf071 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 14 May 2021 12:43:27 +0200 Subject: [PATCH 393/511] arm64: dts: qcom: msm8916-huawei-g7: Add display regulator The display on the Huawei Ascend G7 is supplied by a TI TPS65132 regulator. The panel needs a driver in mainline first, but the TPS65132 is already supported in mainline by the tps65132 driver. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210514104328.18756-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 3b558dc9e90fe2..5ad4e921b11087 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -135,6 +135,30 @@ pinctrl-names = "default"; pinctrl-0 = <&prox_irq_default>; }; + + regulator@3e { + compatible = "ti,tps65132"; + reg = <0x3e>; + + pinctrl-names = "default"; + pinctrl-0 = <®_lcd_en_default>; + + reg_lcd_pos: outp { + regulator-name = "outp"; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; + enable-gpios = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + regulator-active-discharge = <1>; + }; + + reg_lcd_neg: outn { + regulator-name = "outn"; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; + enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + regulator-active-discharge = <1>; + }; + }; }; &blsp_i2c5 { @@ -370,6 +394,14 @@ bias-disable; }; + reg_lcd_en_default: reg-lcd-en-default { + pins = "gpio32", "gpio97"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + sdhc2_cd_default: sdhc2-cd-default { pins = "gpio56"; function = "gpio"; From c4e61e0af4d9f72f77462b9d6759496c6e9f4c29 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 14 May 2021 12:43:28 +0200 Subject: [PATCH 394/511] arm64: dts: qcom: msm8916-huawei-g7: Add NFC The Huawei Ascend G7 supports NFC using the NXP PN547, which is supported by the nxp-nci-i2c driver in mainline. It seems to detect NFC tags using "nfctool" just fine, although it seems like there are not really any useful applications making use of the Linux NFC subsystem. :( Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210514104328.18756-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 5ad4e921b11087..e0075b57419086 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -193,6 +193,24 @@ }; }; +&blsp_i2c6 { + status = "okay"; + + nfc@28 { + compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&msmgpio>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&msmgpio 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_default>; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -378,6 +396,14 @@ bias-disable; }; + nfc_default: nfc-default { + pins = "gpio2", "gpio20", "gpio21"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + mag_reset_default: mag-reset-default { pins = "gpio36"; function = "gpio"; From 297e6e38320f325eb6763e48847e7dd06fda694b Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 27 Apr 2021 15:20:58 +0530 Subject: [PATCH 395/511] arm64: dts: sc7280: Add interconnect provider DT nodes Add the DT nodes for the network-on-chip interconnect buses found on sc7280-based platforms. Signed-off-by: Odelu Kukatla Link: https://lore.kernel.org/r/1619517059-12109-4-git-send-email-okukatla@codeaurora.org [bjorn: Sorted nodes and dropped include] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 87 ++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0b6f119dce1055..a8c274ad74c47b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -275,6 +275,12 @@ }; }; + clk_virt: interconnect { + compatible = "qcom,sc7280-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; @@ -453,6 +459,55 @@ }; }; + cnoc2: interconnect@1500000 { + reg = <0 0x01500000 0 0x1000>; + compatible = "qcom,sc7280-cnoc2"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc3: interconnect@1502000 { + reg = <0 0x01502000 0 0x1000>; + compatible = "qcom,sc7280-cnoc3"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1580000 { + reg = <0 0x01580000 0 0x4>; + compatible = "qcom,sc7280-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + reg = <0 0x01680000 0 0x15480>; + compatible = "qcom,sc7280-system-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sc7280-aggre1-noc"; + reg = <0 0x016e0000 0 0x1c080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0 0x01700000 0 0x2b080>; + compatible = "qcom,sc7280-aggre2-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0 0x01740000 0 0x1e080>; + compatible = "qcom,sc7280-mmss-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex", "syscon"; reg = <0 0x01f40000 0 0x40000>; @@ -470,6 +525,13 @@ #clock-cells = <1>; }; + lpass_ag_noc: interconnect@3c40000 { + reg = <0 0x03c40000 0 0xf080>; + compatible = "qcom,sc7280-lpass-ag-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sc7280-gpucc"; reg = <0 0x03d90000 0 0x9000>; @@ -973,6 +1035,20 @@ }; }; + dc_noc: interconnect@90e0000 { + reg = <0 0x090e0000 0 0x5080>; + compatible = "qcom,sc7280-dc-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + reg = <0 0x9100000 0 0xe2200>; + compatible = "qcom,sc7280-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; @@ -980,6 +1056,13 @@ interrupts = ; }; + nsp_noc: interconnect@a0c0000 { + reg = <0 0x0a0c0000 0 0x10000>; + compatible = "qcom,sc7280-nsp-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; reg = <0 0xaaf0000 0 0x10000>; @@ -1294,6 +1377,10 @@ , ; + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + rpmhpd: power-controller { compatible = "qcom,sc7280-rpmhpd"; #power-domain-cells = <1>; From 2dbe13dbc15f8e452595e9d19beb70e08a7839f5 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 26 May 2021 15:14:24 +0530 Subject: [PATCH 396/511] ARM: dts: omap2/3: Drop dmas property from I2C node DMA was never supported by i2c-omap driver and the bindings were never documented. Therefore drop the entries in preparation to moving bindings to YAML schema. Signed-off-by: Vignesh Raghavendra Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm816x.dtsi | 4 ---- arch/arm/boot/dts/omap2.dtsi | 4 ---- arch/arm/boot/dts/omap3.dtsi | 6 ------ 3 files changed, 14 deletions(-) diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 1825d912b8ab45..a9e7274806f46b 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -314,8 +314,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <70>; - dmas = <&edma 58 0 &edma 59 0>; - dma-names = "tx", "rx"; }; i2c2: i2c@4802a000 { @@ -325,8 +323,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <71>; - dmas = <&edma 60 0 &edma 61 0>; - dma-names = "tx", "rx"; }; intc: interrupt-controller@48200000 { diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index f9c2a993889862..5750ca1233cc2d 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -120,8 +120,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; }; i2c2: i2c@48072000 { @@ -131,8 +129,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; }; mcspi1: spi@48098000 { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 574bda7a4afdb9..64b7e6fddd1bc8 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -403,8 +403,6 @@ compatible = "ti,omap3-i2c"; reg = <0x48070000 0x80>; interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -414,8 +412,6 @@ compatible = "ti,omap3-i2c"; reg = <0x48072000 0x80>; interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -425,8 +421,6 @@ compatible = "ti,omap3-i2c"; reg = <0x48060000 0x80>; interrupts = <61>; - dmas = <&sdma 25 &sdma 26>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; From 07168bacf81953e0f35bd6c0dc64022fe86b8ad3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 1 Jun 2021 11:10:29 +0530 Subject: [PATCH 397/511] ARM: dts: ti: drop usage of redundant compatible Commit 229110c1aa691 ("ARM: dts: am437x/am33xx/da850: Add new ECAP and EPWM bindings") added ti,am3352-ehrpwm compatible which is similar to ti,am33xx-ehrpwm but without out t,hwmod properties. But with commit 58bfbea5b1c68 ("ARM: dts: am437x/am33xx: Remove hwmod entries for ECAP and EPWM nodes") dropped support for all ti,hwmod for ehrpwm, but missed deprecating ti,am33xx-ehrpwm compatible. So drop ti,am33xx-ehrpwm from DT as it is no longer needed. ti-ehrpwn driver still support ti,am33xx-ehrpwm in order to maintain backward compatibility. Signed-off-by: Lokesh Vutla Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 9 +++------ arch/arm/boot/dts/am437x-l4.dtsi | 18 ++++++------------ arch/arm/boot/dts/da850.dtsi | 6 ++---- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 268793bd88cb77..cd716f7c59ee2e 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -2017,8 +2017,7 @@ }; ehrpwm0: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -2078,8 +2077,7 @@ }; ehrpwm1: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; @@ -2139,8 +2137,7 @@ }; ehrpwm2: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 204d3d42b09f0f..8c132cc0d29cfd 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -1760,8 +1760,7 @@ ehrpwm0: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -1812,8 +1811,7 @@ ehrpwm1: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; @@ -1864,8 +1862,7 @@ ehrpwm2: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; @@ -1905,8 +1902,7 @@ ehrpwm3: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; @@ -1946,8 +1942,7 @@ ehrpwm4: pwm@48308200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; @@ -1987,8 +1982,7 @@ ehrpwm5: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 7cf31b6e48b7be..afdf3d3747cebd 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -574,8 +574,7 @@ status = "disabled"; }; ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; @@ -584,8 +583,7 @@ status = "disabled"; }; ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; From be8c9d7957dda67379f68863f0e9f82600e0f583 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 1 Jun 2021 14:54:55 +0530 Subject: [PATCH 398/511] ARM: dts: ti: Drop usage of ti,am33xx-ecap from DT nodes ti,am33xx-ecap is used to represent device nodes using ti,hwmod data. Now that hwmod entries are entirely removed, drop usage of ti,am33xx-ecap compatible from all DT nodes. Signed-off-by: Lokesh Vutla Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 9 +++------ arch/arm/boot/dts/am437x-l4.dtsi | 9 +++------ arch/arm/boot/dts/da850.dtsi | 9 +++------ 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index cd716f7c59ee2e..1e1bd745119479 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1996,8 +1996,7 @@ ranges = <0 0 0x1000>; ecap0: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -2056,8 +2055,7 @@ ranges = <0 0 0x1000>; ecap1: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -2116,8 +2114,7 @@ ranges = <0 0 0x1000>; ecap2: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 8c132cc0d29cfd..201e4e3bd3a2d6 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -1749,8 +1749,7 @@ ecap0: ecap@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -1800,8 +1799,7 @@ ecap1: ecap@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -1851,8 +1849,7 @@ ecap2: ecap@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index afdf3d3747cebd..8e5748e6b27003 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -592,8 +592,7 @@ status = "disabled"; }; ecap0: ecap@306000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; clocks = <&psc1 20>; @@ -602,8 +601,7 @@ status = "disabled"; }; ecap1: ecap@307000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; clocks = <&psc1 20>; @@ -612,8 +610,7 @@ status = "disabled"; }; ecap2: ecap@308000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; clocks = <&psc1 20>; From 61edd91c262b4cdc92d95769509434ec24a8fe2a Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 1 Jun 2021 14:54:56 +0530 Subject: [PATCH 399/511] ARM: dts: ti: Fix node name for all ecap dt nodes dtbs_check produces the following warning for ecap node name: ecap@100: $nodename:0: 'ecap@100' does not match '^pwm(@.*|-[0-9a-f])*$' Fix this by replacing ecap with pwm in node name Signed-off-by: Lokesh Vutla Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-cm-t335.dts | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- arch/arm/boot/dts/am33xx-l4.dtsi | 6 +++--- arch/arm/boot/dts/am437x-l4.dtsi | 6 +++--- arch/arm/boot/dts/da850.dtsi | 6 +++--- arch/arm/boot/dts/dra7-l4.dtsi | 6 +++--- 7 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 36d963db402661..a306b0ccd06f14 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -333,7 +333,7 @@ status = "okay"; &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 902e295b309e9b..9cf39c93defb04 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -495,7 +495,7 @@ &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 45bf0273ecd856..001657be0381b8 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -510,7 +510,7 @@ &epwmss2 { status = "okay"; - ecap2: ecap@100 { + ecap2: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap2_pins>; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 1e1bd745119479..d86f5c3cb5339e 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1995,7 +1995,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap0: ecap@100 { + ecap0: pwm@100 { compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; @@ -2054,7 +2054,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap1: ecap@100 { + ecap1: pwm@100 { compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; @@ -2113,7 +2113,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap2: ecap@100 { + ecap2: pwm@100 { compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 201e4e3bd3a2d6..40ef3973f2a95f 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -1747,7 +1747,7 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap0: ecap@100 { + ecap0: pwm@100 { compatible = "ti,am4372-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -1797,7 +1797,7 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap1: ecap@100 { + ecap1: pwm@100 { compatible = "ti,am4372-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -1847,7 +1847,7 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap2: ecap@100 { + ecap2: pwm@100 { compatible = "ti,am4372-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 8e5748e6b27003..c3942b4e82ad1e 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -591,7 +591,7 @@ power-domains = <&psc1 17>; status = "disabled"; }; - ecap0: ecap@306000 { + ecap0: pwm@306000 { compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; @@ -600,7 +600,7 @@ power-domains = <&psc1 20>; status = "disabled"; }; - ecap1: ecap@307000 { + ecap1: pwm@307000 { compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; @@ -609,7 +609,7 @@ power-domains = <&psc1 20>; status = "disabled"; }; - ecap2: ecap@308000 { + ecap2: pwm@308000 { compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 4b336b831da25f..be63dfebabd62d 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -2561,7 +2561,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap0: ecap@100 { + ecap0: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -2607,7 +2607,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap1: ecap@100 { + ecap1: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -2653,7 +2653,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap2: ecap@100 { + ecap2: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; From 6320b2aee8b46b7a6468a02a38d1815b263ebc38 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 1 Jun 2021 14:54:57 +0530 Subject: [PATCH 400/511] ARM: dts: am33xx: Drop interrupt property from ecap nodes Interrupts were never supported by ecap driver and the bindings were never documented.Therefore drop the entries in preparation to moving bindings to YAML schema. Signed-off-by: Lokesh Vutla Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index d86f5c3cb5339e..859e760df4c8bc 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -2001,8 +2001,6 @@ reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <31>; - interrupt-names = "ecap0"; status = "disabled"; }; @@ -2060,8 +2058,6 @@ reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <47>; - interrupt-names = "ecap1"; status = "disabled"; }; @@ -2119,8 +2115,6 @@ reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <61>; - interrupt-names = "ecap2"; status = "disabled"; }; From 794fd4a55ec55b9443c143388a8addee92671157 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 1 Jun 2021 17:25:45 +0200 Subject: [PATCH 401/511] ARM: dts: dra7x-evm: Drop "ti,pcf8575" The TI part is equivalent to the NXP part and its compatible value is not documented in the DT bindings. All other users of similar I2C GPIO expanders just use the compatible values of the original NXP parts. Signed-off-by: Geert Uytterhoeven Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 6 +++--- arch/arm/boot/dts/dra72-evm-common.dtsi | 4 ++-- arch/arm/boot/dts/dra76-evm.dts | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 3dcb6e1f49bcf1..87deb6a76eff36 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -319,7 +319,7 @@ }; pcf_lcd: gpio@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; @@ -330,7 +330,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -362,7 +362,7 @@ clock-frequency = <400000>; pcf_hdmi: gpio@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index f2384277d5dcdc..f12825268188e4 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -226,7 +226,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -256,7 +256,7 @@ clock-frequency = <400000>; pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index fbe4030650b7cc..e2b7fcb061cf06 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -349,7 +349,7 @@ }; pcf_lcd: pcf8757@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; @@ -360,7 +360,7 @@ }; pcf_gpio_21: pcf8757@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; @@ -371,7 +371,7 @@ }; pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; From 414bfe1d26b60ef20b58e36efd5363188a694bab Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 8 Jun 2021 10:39:51 +0530 Subject: [PATCH 402/511] ARM: dts: am335x: align ti,pindir-d0-out-d1-in property with dt-shema ti,pindir-d0-out-d1-in property is expected to be of type boolean. Therefore, fix the property accordingly. Fixes: 444d66fafab8 ("ARM: dts: add spi wifi support to cm-t335") Signed-off-by: Aswath Govindraju Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-cm-t335.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index a306b0ccd06f14..688e14e82eba47 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -496,7 +496,7 @@ status = "okay"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; /* WLS1271 WiFi */ wlcore: wlcore@1 { compatible = "ti,wl1271"; From 9b11fec7345f21995f4ea4bafb0e108b9a620238 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 8 Jun 2021 10:39:52 +0530 Subject: [PATCH 403/511] ARM: dts: am437x: align ti,pindir-d0-out-d1-in property with dt-shema ti,pindir-d0-out-d1-in property is expected to be of type boolean. Therefore, fix the property accordingly. Fixes: b0b039515445 ("ARM: dts: am43x-epos-evm: set data pin directions for spi0 and spi1") Signed-off-by: Aswath Govindraju Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index d717d5ada81294..aae0af10a5b1f4 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -860,7 +860,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_pins_default>; pinctrl-1 = <&spi0_pins_sleep>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &spi1 { @@ -868,7 +868,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_default>; pinctrl-1 = <&spi1_pins_sleep>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &usb2_phy1 { From bb84a31bed146bb5a4dcb9eb7fc63458fdc4d6e2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 3 Jun 2021 18:46:30 +0200 Subject: [PATCH 404/511] arm64: tegra: Use correct compatible string for Tegra186 SMMU The SMMU found on Tegra186 requires interoperation with the memory controller in order to program stream ID overrides. The generic ARM SMMU 500 compatible is therefore inaccurate. Replace it with a more correct, SoC-specific compatible string. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9f75bbf00cf7a5..a173f40256ae1a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1082,7 +1082,7 @@ }; smmu: iommu@12000000 { - compatible = "arm,mmu-500"; + compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; reg = <0 0x12000000 0 0x800000>; interrupts = , , From b966d2db05a70263ddffc795eb544b94427fc327 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 3 Jun 2021 18:46:31 +0200 Subject: [PATCH 405/511] arm64: tegra: Hook up memory controller to SMMU on Tegra186 On Tegra186 and later, the memory controller needs to be programmed in coordination with any of the ARM SMMU instances to configure the stream ID used for each memory client. To support this, add a phandle reference to the memory controller to the SMMU device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index a173f40256ae1a..d02f6bf3e2ca71 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1152,6 +1152,8 @@ stream-match-mask = <0x7f80>; #global-interrupts = <1>; #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; }; host1x@13e00000 { From c7289b1c8a4e10bbbdb7097a71a90652beb767a1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 3 Jun 2021 18:46:32 +0200 Subject: [PATCH 406/511] arm64: tegra: Enable SMMU support on Tegra194 Add the device tree node for the dual-SMMU found on Tegra194 and hook up peripherals such as host1x, BPMP, HDA, SDMMC, EQOS and VIC. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 86 ++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 2e40b604728335..b7d53284139000 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -62,6 +62,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_EQOS>; status = "disabled"; snps,write-requests = <1>; @@ -733,6 +734,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_SDMMC1>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; nvidia,pad-autocal-pull-down-offset-3v3-timeout = @@ -759,6 +761,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_SDMMC3>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; @@ -790,6 +793,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_SDMMC4>; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -821,6 +825,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_HDA>; status = "disabled"; }; @@ -1300,6 +1305,84 @@ interrupt-controller; }; + smmu: iommu@12000000 { + compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; + reg = <0x12000000 0x800000>, + <0x11000000 0x800000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <2>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + host1x@13e00000 { compatible = "nvidia,tegra194-host1x"; reg = <0x13e00000 0x10000>, @@ -1319,6 +1402,7 @@ ranges = <0x15000000 0x15000000 0x01000000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnect-names = "dma-mem"; + iommus = <&smmu TEGRA194_SID_HOST1X>; display-hub@15200000 { compatible = "nvidia,tegra194-display"; @@ -1430,6 +1514,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_VIC>; }; dpaux0: dpaux@155c0000 { @@ -2136,6 +2221,7 @@ <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu TEGRA194_SID_BPMP>; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; From f1f55c6b77b6e88f8b9a95b7cb491bb619a1e6bc Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Wed, 2 Jun 2021 08:56:15 +0200 Subject: [PATCH 407/511] arm64: dts: ti: iot2050: Configure r5f cluster on basic variant in split mode Lockstep mode is not supported here. So turn it off to avoid warnings during startup. Signed-off-by: Jan Kiszka Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/3a241e50-80a3-992a-2445-345c629d7895@siemens.com --- arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts index 4f7e3f2a626551..94bb5dd3912224 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts @@ -59,3 +59,8 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; + +&mcu_r5fss0 { + /* lock-step mode not supported on this board */ + ti,cluster-mode = <0>; +}; From c016c26c1631f539c652b5d82242a3ca402545c1 Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 26 May 2021 12:53:58 +0200 Subject: [PATCH 408/511] ARM: dts: imx6q-dhcom: Fix ethernet reset time properties Fix ethernet reset time properties as described in Documentation/devicetree/bindings/net/ethernet-phy.yaml Fixes: 52c7a088badd ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2") Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index 236fc205c38903..19fc0b9af54183 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -96,8 +96,8 @@ reg = <0>; max-speed = <100>; reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - reset-post-delay-us = <1000>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; }; }; }; From e2bdd3484890441b9cc2560413a86e8f2aa04157 Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 26 May 2021 12:53:59 +0200 Subject: [PATCH 409/511] ARM: dts: imx6q-dhcom: Fix ethernet plugin detection problems To make the ethernet cable plugin detection reliable the power detection of the smsc phy has been disabled. Fixes: 52c7a088badd ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2") Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index 19fc0b9af54183..efc771f12e4f8e 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -98,6 +98,7 @@ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ }; }; }; From ddc873cd3c0af4faad6a00bffda21c3f775126dd Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 26 May 2021 12:54:00 +0200 Subject: [PATCH 410/511] ARM: dts: imx6q-dhcom: Add gpios pinctrl for i2c bus recovery The i2c bus can freeze at the end of transaction so the bus can no longer work. This scenario is improved by adding scl/sda gpios definitions to implement the i2c bus recovery mechanism. Fixes: 52c7a088badd ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2") Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 36 +++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index efc771f12e4f8e..c6ff7a111aabbd 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -105,22 +105,31 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; ltc3676: pmic@3c { @@ -286,6 +295,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + pinctrl_i2c2: i2c2-grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 @@ -293,6 +309,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + pinctrl_i2c3: i2c3-grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -300,6 +323,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + pinctrl_pmic_hw300: pmic-hw300-grp { fsl,pins = < MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0 From ab583173144a1f26daedc0caa616f397fe9ae411 Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 26 May 2021 12:54:01 +0200 Subject: [PATCH 411/511] ARM: dts: imx6q-dhcom: Add aliases for i2c, serial and rtc Add aliases for i2c and serial to match the order of the DHCOM standard [1]. Also add aliases for the two rtcs. The i2c rtc is the primary one. [1] https://wiki.dh-electronics.com/images/2/2e/DOC_DHCOM-Standard-Specification_R01_2016-11-17.pdf Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index c6ff7a111aabbd..f4f5cf75de95bb 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -12,10 +12,20 @@ / { aliases { + i2c0 = &i2c2; + i2c1 = &i2c1; + i2c2 = &i2c3; mmc0 = &usdhc2; mmc1 = &usdhc3; mmc2 = &usdhc4; mmc3 = &usdhc1; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + serial0 = &uart1; + serial1 = &uart5; + serial2 = &uart4; + serial3 = &uart2; + serial4 = &uart3; }; memory@10000000 { @@ -213,7 +223,7 @@ pagesize = <16>; }; - rtc@56 { + rtc_i2c: rtc@56 { compatible = "microcrystal,rv3029"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc_hw300>; From f4ab3f2848247caea9c760a5a598278413a0a953 Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Wed, 26 May 2021 12:54:02 +0200 Subject: [PATCH 412/511] ARM: dts: imx6q-dhcom: Add ethernet VIO regulator Add VIO regulator that supplies multiple ethernet magnetics and currently there is no upstream support for that in the networking, so just keep the regulator enabled always to emulate what other boards, which have this hard-wired, do. Until there is support. Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index f4f5cf75de95bb..6b6842bee749ac 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -33,6 +33,19 @@ reg = <0x10000000 0x40000000>; }; + reg_eth_vio: regulator-eth-vio { + compatible = "regulator-fixed"; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_vio"; + vin-supply = <&sw2_reg>; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; @@ -280,6 +293,11 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1 + >; + }; + + pinctrl_enet_vio: enet-vio-grp { + fsl,pins = < MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0 >; }; From 1fac5db35ee91b88b07f6e062b0c2355fe71b289 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 26 May 2021 17:22:43 +0200 Subject: [PATCH 413/511] ARM: dts: imx6: Add GE B1x5v2 This adds device tree files for the General Electric Healthcare (GEHC) B1x5v2 series. All models make use of Congatec's QMX6 system on module, which is described in its own device tree include, so that it can also be used by other boards. Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 5 + arch/arm/boot/dts/imx6dl-b105pv2.dts | 32 ++ arch/arm/boot/dts/imx6dl-b105v2.dts | 32 ++ arch/arm/boot/dts/imx6dl-b125pv2.dts | 30 ++ arch/arm/boot/dts/imx6dl-b125v2.dts | 30 ++ arch/arm/boot/dts/imx6dl-b155v2.dts | 32 ++ arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi | 413 +++++++++++++++++ arch/arm/boot/dts/imx6dl-b1x5v2.dtsi | 58 +++ arch/arm/boot/dts/imx6dl-qmx6.dtsi | 612 ++++++++++++++++++++++++++ 9 files changed, 1244 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-b105pv2.dts create mode 100644 arch/arm/boot/dts/imx6dl-b105v2.dts create mode 100644 arch/arm/boot/dts/imx6dl-b125pv2.dts create mode 100644 arch/arm/boot/dts/imx6dl-b125v2.dts create mode 100644 arch/arm/boot/dts/imx6dl-b155v2.dts create mode 100644 arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi create mode 100644 arch/arm/boot/dts/imx6dl-b1x5v2.dtsi create mode 100644 arch/arm/boot/dts/imx6dl-qmx6.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c17cb7e36b5c93..a2389b17026a88 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -516,6 +516,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-ds.dtb \ imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ + imx6dl-b105pv2.dtb \ + imx6dl-b105v2.dtb \ + imx6dl-b125v2.dtb \ + imx6dl-b125pv2.dtb \ + imx6dl-b155v2.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ imx6q-gw52xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/imx6dl-b105pv2.dts new file mode 100644 index 00000000000000..411aa72d344b8b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b105pv2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B105Pv2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5pv2.dtsi" + +/ { + model = "General Electric B105Pv2"; + compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g101evn010"; + }; +}; + +&i2c3 { + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/imx6dl-b105v2.dts new file mode 100644 index 00000000000000..d011127c635b5f --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b105v2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B105v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B105v2"; + compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g101evn010"; + }; +}; + +&i2c3 { + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/imx6dl-b125pv2.dts new file mode 100644 index 00000000000000..ca840fa84052ee --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b125pv2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B125Pv2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5pv2.dtsi" + +/ { + model = "General Electric B125Pv2"; + compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g121ean01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/imx6dl-b125v2.dts new file mode 100644 index 00000000000000..81e5a9cb89006d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b125v2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B125v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B125v2"; + compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g121ean01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/imx6dl-b155v2.dts new file mode 100644 index 00000000000000..c861937b30f6a7 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b155v2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B155v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B155v2"; + compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g156xtn01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h84"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi new file mode 100644 index 00000000000000..ec5b664531565a --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B1x5Pv2 +// patient monitor series +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +#include +#include "imx6dl-qmx6.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; + + /* Do not allow frequencies above 800MHz */ + cpus { + cpu@0 { + operating-points = < + /* kHz uV */ + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 792000 1175000 + 396000 1175000 + >; + }; + + cpu@1 { + operating-points = < + /* kHz uV */ + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 792000 1175000 + 396000 1175000 + >; + }; + }; + + reg_syspwr: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "SYS_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_5v_pmc: regulator-5v-pmc { + compatible = "regulator-fixed"; + regulator-name = "5V PMC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_syspwr>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_syspwr>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_syspwr>; + }; + + reg_5v0_audio: regulator-5v0-audio { + compatible = "regulator-fixed"; + regulator-name = "5V0_AUDIO"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * This must be always-on for da7212, which has some not + * properly documented dependencies for it's speaker supply + * pin. The issue manifests as speaker volume being very low. + */ + regulator-always-on; + }; + + + reg_3v3_audio: regulator-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "3V3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_3v3>; + pinctrl-0 = <&pinctrl_q7_hda_reset>; + pinctrl-names = "default"; + gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2v5_audio: regulator-2v5-audio { + compatible = "regulator-fixed"; + regulator-name = "2V5_AUDIO"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <®_3v3_audio>; + + }; + + reg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "WLAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_sdio_power>; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + }; + + reg_bl: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "LED_VCC"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_syspwr>; + pinctrl-0 = <&pinctrl_q7_lcd_power>; + pinctrl-names = "default"; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + }; + + usb_power: regulator-usb-power { + compatible = "regulator-fixed"; + regulator-name = "USB POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + }; + + charger: battery-charger { + compatible = "gpio-charger"; /* ti,bq24172 */ + charger-type = "mains"; + gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>; + charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>, + <&tca6424a 12 GPIO_ACTIVE_HIGH>; + charge-current-limit-mapping = <1300000 0x0>, + <700000 0x1>, + <0 0x2>; + charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>; + }; + + poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_spi_cs1>; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + }; + + power-button-key { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_sleep_button>; + + power-button { + label = "power button"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + rotary-encoder-key { + compatible = "gpio-keys"; + + rotary-encoder-press { + label = "rotary-encoder press"; + gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,can-disable; + }; + }; + + rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>; + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>; + rotary-encoder,relative-axis; + rotary-encoder,steps-per-period = <2>; + wakeup-source; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>; + + alarm1 { + label = "alarm:red"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + alarm2 { + label = "alarm:yellow"; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + }; + + alarm3 { + label = "alarm:blue"; + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_backlight_enable>; + power-supply = <®_bl>; + pwms = <&pwm4 0 5000000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <179>; + enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + panel { + backlight = <&backlight>; + power-supply = <®_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = "Speaker", "Ext Spk"; + simple-audio-card,audio-routing = "Ext Spk", "LINE"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; +}; + +&audmux { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + battery: battery@b { + compatible = "ti,bq20z65", "sbs,sbs-battery"; + reg = <0x0b>; + sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>; + sbs,i2c-retry-count = <5>; + power-supplies = <&charger>; + }; + + codec: audio-codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_2v5_audio>; + VDDSP-supply = <®_5v0_audio>; + VDDMIC-supply = <®_3v3_audio>; + VDDIO-supply = <®_3v3_audio>; + clocks = <&clk_ext_audio_codec>; + clock-names = "mclk"; + }; +}; + +&i2c5 { + tca6424a: gpio-controller@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN", + "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF", + "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0", + "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "", + "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL", + "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2"; + + }; + + tmp75: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + vs-supply = <®_3v3>; + interrupt-parent = <&tca6424a>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <&usb_power>; + disable-over-current; + dr_mode = "host"; + status = "okay"; + + /* + * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N. + * On QMX6 this is not connceted to the i.MX6, but to the USB Hub + * from &usbh1. This means, that we cannot easily detect and handle + * over-current events. Fortunately the regulator limits the current + * automatically, so the hardware is still protected. + */ +}; + +&usdhc4 { + /* WiFi module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + vmmc-supply = <®_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio7>; + + interrupt-parent = <&gpio4>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi new file mode 100644 index 00000000000000..a326a331508e22 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B1x5v2 +// patient monitor series +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +#include +#include "imx6dl-b1x5pv2.dtsi" + +/ { + reg_3v3_acm: regulator-3v3-acm { + compatible = "regulator-fixed"; + regulator-name = "3V3 ACM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_3v3>; + }; +}; + +&i2c1 { + tca6416: gpio-controller@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>; + vcc-supply = <®_3v3_acm>; + gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2", + "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1", + "ACM2_CL2", "", "", "", + "", "", "", ""; + + /* + * The interrupt pin is connected to &tca6424a pin 1, but the Linux + * TCA6424 driver cannot handle low type interrupts at the moment + * (and support cannot be added without some ugly hacks). Since this + * controller does not have any input type GPIOs, just pretend + * that the interrupt pin is unconnected. + */ + }; +}; + +&i2c5 { + mpl3115a2: pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + vcc-supply = <®_3v3_acm>; + + /* + * The MPL3115 interrupts are connected to pin 22 and 23 + * of &tca6424a, but the binding does not yet support + * interrupts. + */ + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/imx6dl-qmx6.dtsi new file mode 100644 index 00000000000000..150d69858255d3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-qmx6.dtsi @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for i.MX6DL based congatec QMX6 +// System on Module +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora +// Copyright 2016 congatec AG + +#include "imx6dl.dtsi" +#include +#include + +/ { + memory@10000000 { + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c2>; + + i2c5: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c6: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + + audmux_ssi1 { + fsl,audmux-port = ; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) + >; + }; + + audmux_aud6 { + fsl,audmux-port = ; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&clks { + clocks = <&rtc_sqw>; + clock-names = "ckil"; + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf032b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + + partition@0 { + label = "bootloader"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "user"; + reg = <0x0100000 0x2fc000>; + }; + + partition@3fc000 { + label = "reserved"; + reg = <0x03fc000 0x4000>; + read-only; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + fsl,magic-packet; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@6 { + reg = <6>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + rtc: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + + rtc_sqw: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&i2c6 { + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* + * keep VGEN3, VGEN4 and VGEN5 enabled in order to + * maintain backward compatibility with hw-rev. A.0 + */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* supply voltage for eMMC */ + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&pcie { + reset-gpio = <&gpio1 20 0>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */ + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; +}; + +&usdhc2 { + /* MicroSD card slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + /* eMMC module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + qmx6mux: imx6qdl-qmx6 { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ + >; + }; + + /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ + pinctrl_enet: enet { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ + >; + }; + + pinctrl_i2c1: i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ + >; + }; + + pinctrl_i2c2: i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ + >; + }; + + pinctrl_i2c3: i2c3 { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ + >; + }; + + pinctrl_phy_reset: phy-reset { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ + >; + }; + + pinctrl_pwm4: pwm4 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ + >; + }; + + pinctrl_q7_backlight_enable: q7-backlight-enable { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ + >; + }; + + pinctrl_q7_gpio0: q7-gpio0 { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ + >; + }; + + pinctrl_q7_gpio1: q7-gpio1 { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ + >; + }; + + pinctrl_q7_gpio2: q7-gpio2 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ + >; + }; + + pinctrl_q7_gpio3: q7-gpio3 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ + >; + }; + + pinctrl_q7_gpio4: q7-gpio4 { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ + >; + }; + + pinctrl_q7_gpio5: q7-gpio5 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ + >; + }; + + pinctrl_q7_gpio6: q7-gpio6 { + fsl,pins = < + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ + >; + }; + + pinctrl_q7_gpio7: q7-gpio7 { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ + >; + }; + + pinctrl_q7_hda_reset: q7-hda-reset { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ + >; + }; + + pinctrl_q7_lcd_power: lcd-power { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ + >; + }; + + pinctrl_q7_sdio_power: q7-sdio-power { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ + >; + }; + + pinctrl_q7_sleep_button: q7-sleep-button { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ + >; + }; + + pinctrl_q7_spi_cs1: spi-cs1 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ + >; + }; + + /* SPI1 bus does not leave System on Module */ + pinctrl_spi1: spi1 { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + >; + }; + + /* Debug connector on Q7 module */ + pinctrl_uart2: uart2 { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3 { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ + >; + }; + + pinctrl_usbotg: usbotg { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ + >; + }; + + /* µSD card slot on Q7 module */ + pinctrl_usdhc2: usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ + >; + }; + + /* eMMC module on Q7 module */ + pinctrl_usdhc3: usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ + >; + }; + + pinctrl_wdog: wdog { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ + >; + }; + }; +}; From a4f27c75ac41a40042a50d536052fefb35728b8b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 9 Mar 2021 06:31:16 +0100 Subject: [PATCH 414/511] arm64: dts: imx8mp-phycore-som: enable spi nor enable the mt25qu256aba spi nor on the imx8mp-phycore-som. Signed-off-by: Heiko Schocher Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-phycore-som.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index f3965ec5b31ddf..aa78e0d8c72b26 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -65,6 +65,20 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + som_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -217,6 +231,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 From 77a1aa039336312d622f66ef7ee18ea1f6bd59bc Mon Sep 17 00:00:00 2001 From: Adrien Grassein Date: Tue, 11 May 2021 21:35:58 +0200 Subject: [PATCH 415/511] arm64: dts: imx8mq-nitrogen: add USB OTG support Add the description for the USB OTG port. The OTG port uses a dedicated regulator for vbus. Signed-off-by: Adrien Grassein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-nitrogen.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts index 81d2692966103c..b46f45a82be18b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts @@ -34,6 +34,17 @@ }; }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_vref_0v9: regulator-vref-0v9 { compatible = "regulator-fixed"; regulator-name = "vref-0v9"; @@ -190,6 +201,18 @@ status = "okay"; }; +&usb_dwc3_0 { + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3_0>; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + &usdhc1 { assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; assigned-clock-rates = <400000000>; @@ -339,6 +362,12 @@ >; }; + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 @@ -353,6 +382,12 @@ >; }; + pinctrl_usb3_0: usb3-0grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 From 4a085de205292c1007681e4e077279f77a5ce2ad Mon Sep 17 00:00:00 2001 From: Adrien Grassein Date: Tue, 11 May 2021 21:35:59 +0200 Subject: [PATCH 416/511] arm64: dts: imx8mq-nitrogen: add USB HOST support Add the description for the USB host port. This port is linked to a resettable USB HUB so handle this reset signal with a GPIO hog. Signed-off-by: Adrien Grassein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-nitrogen.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts index b46f45a82be18b..5553f3c84dbc15 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts @@ -102,6 +102,15 @@ }; }; +/* Release reset of the USB Host HUB */ +&gpio1 { + usb-host-reset-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -213,6 +222,17 @@ status = "okay"; }; +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3_1>; + status = "okay"; +}; + &usdhc1 { assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; assigned-clock-rates = <400000000>; @@ -388,6 +408,12 @@ >; }; + pinctrl_usb3_1: usb3-1grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 From 4b82e1f839a255be128c89a7ee438e7b0e95c81b Mon Sep 17 00:00:00 2001 From: Adrien Grassein Date: Tue, 11 May 2021 21:36:00 +0200 Subject: [PATCH 417/511] arm64: dts: imx8mq-nitrogen: add lt8912 MIPI-DSI to HDMI Add support of the lt8912b in the DTB. This adds the support of the DB_DSIHD daugther board from Boundary Devices. Signed-off-by: Adrien Grassein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-nitrogen.dts | 121 ++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts index 5553f3c84dbc15..f70fb32b96b0c7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts @@ -34,6 +34,19 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + ddc-i2c-bus = <&ddc_i2c_bus>; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <<8912_out>; + }; + }; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -81,6 +94,9 @@ }; }; +&dphy { + status = "okay"; +}; &fec1 { pinctrl-names = "default"; @@ -194,6 +210,98 @@ }; }; +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pca9546: i2cmux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c4@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48> ; + reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_out_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8912_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + }; + + ddc_i2c_bus: i2c4@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + }; + + i2c4@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + + max7323: gpio-expander@68 { + compatible = "maxim,max7323"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max7323>; + gpio-controller; + reg = <0x68>; + #gpio-cells = <2>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&hdmi_out_in>; + }; + }; + }; +}; + &uart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -364,6 +472,19 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f + >; + }; + + pinctrl_max7323: max7323grp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 + >; + }; + pinctrl_reg_arm_dram: reg-arm-dramgrp { fsl,pins = < MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 From 292e0f487c0a18d7d35fb5acc0d5a993ed78bd3c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 5 Apr 2021 20:33:42 -0500 Subject: [PATCH 418/511] arm64: dts: imx8mn: Add spba1 bus The i.MX8MN has an SPBA bus which covers much of the audio, but there is a second SPBA bus which covers many of the serial interfaces like SPI and UARTs currently missing from the device tree. The reference manual calls the bus handling the audio peripherals SPBA2, and the bus handling the serial peripherals is called SPBA1. Rename the existing spba bus to spba2 and add spba1. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 146 ++++++++++++---------- 1 file changed, 77 insertions(+), 69 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 4dac4da38f4c05..e961acd237a873 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -255,7 +255,7 @@ #size-cells = <1>; ranges; - spba: spba-bus@30000000 { + spba2: spba-bus@30000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -681,80 +681,88 @@ #size-cells = <1>; ranges; - ecspi1: spi@30820000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + spba1: spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, - <&clk IMX8MN_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; - ecspi2: spi@30830000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, - <&clk IMX8MN_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi1: spi@30820000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, + <&clk IMX8MN_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi3: spi@30840000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, - <&clk IMX8MN_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: spi@30830000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, + <&clk IMX8MN_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART1_ROOT>, - <&clk IMX8MN_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi3: spi@30840000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, + <&clk IMX8MN_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART3_ROOT>, - <&clk IMX8MN_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_UART1_ROOT>, + <&clk IMX8MN_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART2_ROOT>, - <&clk IMX8MN_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; + uart3: serial@30880000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_UART3_ROOT>, + <&clk IMX8MN_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_UART2_ROOT>, + <&clk IMX8MN_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; }; crypto: crypto@30900000 { From 7923353b623d518e82ed5f760d38f621e36f3720 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 5 Apr 2021 20:33:43 -0500 Subject: [PATCH 419/511] arm64: dts: imx8mm: Add spba1 and spba2 buses The i.MX8MM reference manual shows there are two spba busses. SPBA1 handles much of the serial interfaces, and SPBA2 covers much of the audio. Add both of them. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 362 +++++++++++----------- 1 file changed, 189 insertions(+), 173 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index a27e02bee6b479..64aa38fd2b6e01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -271,117 +271,125 @@ #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; - sai1: sai@30010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, - <&clk IMX8MM_CLK_SAI1_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + spba2: spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + + sai1: sai@30010000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30010000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + <&clk IMX8MM_CLK_SAI1_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai2: sai@30020000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30020000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI2_IPG>, - <&clk IMX8MM_CLK_SAI2_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + sai2: sai@30020000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30020000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + <&clk IMX8MM_CLK_SAI2_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai3: sai@30030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI3_IPG>, - <&clk IMX8MM_CLK_SAI3_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + sai3: sai@30030000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30030000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + <&clk IMX8MM_CLK_SAI3_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai5: sai@30050000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, - <&clk IMX8MM_CLK_SAI5_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + sai5: sai@30050000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30050000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + <&clk IMX8MM_CLK_SAI5_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai6: sai@30060000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30060000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI6_IPG>, - <&clk IMX8MM_CLK_SAI6_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + sai6: sai@30060000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30060000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + <&clk IMX8MM_CLK_SAI6_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - micfil: audio-controller@30080000 { - compatible = "fsl,imx8mm-micfil"; - reg = <0x30080000 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX8MM_CLK_PDM_IPG>, - <&clk IMX8MM_CLK_PDM_ROOT>, - <&clk IMX8MM_AUDIO_PLL1_OUT>, - <&clk IMX8MM_AUDIO_PLL2_OUT>, - <&clk IMX8MM_CLK_EXT3>; - clock-names = "ipg_clk", "ipg_clk_app", - "pll8k", "pll11k", "clkext3"; - dmas = <&sdma2 24 25 0x80000000>; - dma-names = "rx"; - status = "disabled"; - }; + micfil: audio-controller@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>, + <&clk IMX8MM_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; - spdif1: spdif@30090000 { - compatible = "fsl,imx35-spdif"; - reg = <0x30090000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ - <&clk IMX8MM_CLK_24M>, /* rxtx0 */ - <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ - <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ - <&clk IMX8MM_CLK_DUMMY>; /* spba */ - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; - dma-names = "rx", "tx"; - status = "disabled"; + spdif1: spdif@30090000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30090000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MM_CLK_24M>, /* rxtx0 */ + <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; }; gpio1: gpio@30200000 { @@ -670,80 +678,88 @@ ranges = <0x30800000 0x30800000 0x400000>, <0x8000000 0x8000000 0x10000000>; - ecspi1: spi@30820000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + spba1: spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, - <&clk IMX8MM_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; + + ecspi1: spi@30820000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30820000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, + <&clk IMX8MM_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi2: spi@30830000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, - <&clk IMX8MM_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: spi@30830000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30830000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, + <&clk IMX8MM_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi3: spi@30840000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, - <&clk IMX8MM_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi3: spi@30840000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30840000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, + <&clk IMX8MM_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART1_ROOT>, - <&clk IMX8MM_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_UART1_ROOT>, + <&clk IMX8MM_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART3_ROOT>, - <&clk IMX8MM_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart3: serial@30880000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_UART3_ROOT>, + <&clk IMX8MM_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART2_ROOT>, - <&clk IMX8MM_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; + uart2: serial@30890000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_UART2_ROOT>, + <&clk IMX8MM_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; }; crypto: crypto@30900000 { From 9b95c44b417662327e1a2602cc6c6af8cba95825 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 14 Apr 2021 10:26:14 +0800 Subject: [PATCH 420/511] arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be turned on. Signed-off-by: Richard Zhu Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 85b045253a0ec3..4d2035e3dd7cc4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -318,6 +318,7 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vph-supply = <&vgen5_reg>; status = "okay"; }; From 88314aab231361ce8ff34ee7ca6e81c91ee33108 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 20 Apr 2021 13:54:52 +0800 Subject: [PATCH 421/511] arm64: dts: imx8mp: Remove the reference to audio ipg clock on imx8mp On i.MX8MP, there is no audio ipg clock, so remove the wrong reference to this clock in dts file. Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index dea608c8b31e9c..9f7c7f587d38bc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -408,7 +408,6 @@ <&clk IMX8MP_CLK_GIC>, <&clk IMX8MP_CLK_AUDIO_AHB>, <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, - <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, @@ -424,7 +423,6 @@ <500000000>, <400000000>, <800000000>, - <400000000>, <393216000>, <361267200>; }; From dc6d5dc89bad410cc58688f0b73452957bf95020 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 26 Apr 2021 15:06:54 +0800 Subject: [PATCH 422/511] arm64: dts: imx8mp-evk: enable EQOS ethernet Enable EQOS ethernet on i.MX8MP EVK board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9d777bc726aef4..7b99fad6e4d6ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -81,6 +81,26 @@ status = "disabled";/* can2 pin conflict with pdm */ }; +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; @@ -263,6 +283,26 @@ }; &iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 From 03ce38ca69b18c32fdb58f24184f3218efc33f34 Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Mon, 26 Apr 2021 09:52:11 +0200 Subject: [PATCH 423/511] arm64: dts: ls1012a: enable PCIe on freeway board ls1012a-freeway board contains a M.2 2230 slot. Update the status of pcei1 node to okay so that the pcie controller can be probed. Signed-off-by: Mian Yousaf Kaukab Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts index 6290e2f9de6a0b..e8562585d4ac03 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts @@ -24,6 +24,10 @@ status = "okay"; }; +&pcie1 { + status = "okay"; +}; + &qspi { status = "okay"; From 8240c972c1798ea013cbb407722295fc826b3584 Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Wed, 28 Apr 2021 14:58:07 +0200 Subject: [PATCH 424/511] arm64: dts: ls208xa: remove bus-num from dspi node On LS2088A-RDB board, if the spi-fsl-dspi driver is built as module then its probe fails with the following warning: [ 10.471363] couldn't get idr [ 10.471381] WARNING: CPU: 4 PID: 488 at drivers/spi/spi.c:2689 spi_register_controller+0x73c/0x8d0 ... [ 10.471651] fsl-dspi 2100000.spi: Problem registering DSPI ctlr [ 10.471708] fsl-dspi: probe of 2100000.spi failed with error -16 Reason for the failure is that bus-num property is set for dspi node. However, bus-num property is not set for the qspi node. If probe for spi-fsl-qspi happens first then id 0 is dynamically allocated to it. Call to spi_register_controller() from spi-fsl-dspi driver then fails. Since commit 29d2daf2c33c ("spi: spi-fsl-dspi: Make bus-num property optional") bus-num property is optional. Remove bus-num property from dspi node to fix the issue. Signed-off-by: Mian Yousaf Kaukab Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 135ac82108714f..801ba9612d361e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -929,7 +929,6 @@ QORIQ_CLK_PLL_DIV(4)>; clock-names = "dspi"; spi-num-chipselects = <5>; - bus-num = <0>; }; esdhc: esdhc@2140000 { From 1de3aa8611d21d6be546ca1cd13ee05bdd650018 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 28 Apr 2021 08:00:58 -0500 Subject: [PATCH 425/511] arm64: dts: imx8mn-beacon-som: Assign PMIC clock The PMIC throws an errors because the clock isn't assigned to it. Fix this by assigning the clocks info. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index c35eeaff958f5d..54eaf3d6055b11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -120,6 +120,9 @@ interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; regulators { buck1_reg: BUCK1 { From 6bee93d93111d7bb39105b39ed57780a097557cc Mon Sep 17 00:00:00 2001 From: Kornel Duleba Date: Wed, 7 Apr 2021 14:34:38 +0200 Subject: [PATCH 426/511] arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges Currently all PCIE windows point to bus address 0x0, which does not match the values obtained from hardware during EA. Replace those values with CPU addresses, since in reality we have a 1:1 mapping between the two. Signed-off-by: Kornel Duleba Acked-by: Claudiu Manoil Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index feecc49b7f8cb0..5b500c16c9c10c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -990,19 +990,19 @@ msi-map = <0 &its 0x17 0xe>; iommu-map = <0 &smmu 0x17 0xe>; /* PF0-6 BAR0 - non-prefetchable memory */ - ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 + ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 /* PF0-6 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 + 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 + 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 /* PF0: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 + 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 + 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 /* PF1: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 + 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 /* BAR4 (PF5) - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; + 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; enetc_port0: ethernet@0,0 { compatible = "fsl,enetc"; From 4251a3ac4de9625a284a9c046cc915487e9b2a5e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 4 May 2021 10:20:51 +0200 Subject: [PATCH 427/511] arm64: dts: imx8mm: specify dma-ranges DMA addressing capabilities on i.MX8MM are limited by the interconnect, same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let the kernel know about this. Signed-off-by: Lucas Stach Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 64aa38fd2b6e01..e7648c3b839059 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -261,6 +261,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; nvmem-cells = <&imx8mm_uid>; nvmem-cell-names = "soc_unique_id"; From 8d923cdf2ec40520f2a3f4281001d414345b3e74 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 4 May 2021 10:20:52 +0200 Subject: [PATCH 428/511] arm64: dts: imx8mn: specify dma-ranges DMA addressing capabilities on i.MX8MN are limited by the interconnect, same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let the kernel know about this. Signed-off-by: Lucas Stach Reviewed-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index e961acd237a873..d4231e061403f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -245,6 +245,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; nvmem-cells = <&imx8mn_uid>; nvmem-cell-names = "soc_unique_id"; From 15a5261e4d052bf85c7fba24dbe0e9a7c8c05925 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 8 May 2021 00:12:13 +0200 Subject: [PATCH 429/511] arm64: dts: imx8mq: assign PCIe clocks This fixes multiple issues with the current non-existent PCIe clock setup: The controller can run at up to 250MHz, so use a parent that provides this clock. The PHY needs an exact 100MHz reference clock to function if the PCIe refclock is not fed in via the refclock pads. While this mode is not supported (yet) in the driver it doesn't hurt to make sure we are providing a clock with the right rate. The AUX clock is specified to have a maximum clock rate of 10MHz. So the current setup, which drives it straight from the 25MHz oscillator is actually overclocking the AUX input. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 17c449e12c2e52..91df9c5350ae50 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1383,6 +1383,14 @@ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; status = "disabled"; }; @@ -1413,6 +1421,14 @@ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; status = "disabled"; }; From dfda1fd16aa71c839e4002109b0cd15f61105ebb Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Fri, 21 May 2021 11:12:48 +0800 Subject: [PATCH 430/511] arm64: dts: imx8: conn: fix enet clock setting enet_clk_ref actually is sourced from internal gpr clocks which needs a default rate. Also update enet lpcg clock output names to be more straightforward. Cc: Abel Vesa Cc: Stephen Boyd Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-ss-conn.dtsi | 50 ++++++++++++------- 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index e1e81ca0ca698a..a79f42a9618ec5 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -77,9 +77,12 @@ conn_subsys: bus@5b000000 { ; clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, <&enet0_lpcg IMX_LPCG_CLK_2>, - <&enet0_lpcg IMX_LPCG_CLK_1>, + <&enet0_lpcg IMX_LPCG_CLK_3>, <&enet0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; power-domains = <&pd IMX_SC_R_ENET_0>; @@ -94,9 +97,12 @@ conn_subsys: bus@5b000000 { ; clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, <&enet1_lpcg IMX_LPCG_CLK_2>, - <&enet1_lpcg IMX_LPCG_CLK_1>, + <&enet1_lpcg IMX_LPCG_CLK_3>, <&enet1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; power-domains = <&pd IMX_SC_R_ENET_1>; @@ -152,15 +158,19 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, - <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; clock-indices = , , - , , - ; - clock-output-names = "enet0_ipg_root_clk", - "enet0_tx_clk", - "enet0_ahb_clk", - "enet0_ipg_clk", - "enet0_ipg_s_clk"; + , , + , ; + clock-output-names = "enet0_lpcg_timer_clk", + "enet0_lpcg_txc_sampling_clk", + "enet0_lpcg_ahb_clk", + "enet0_lpcg_rgmii_txc_clk", + "enet0_lpcg_ipg_clk", + "enet0_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_0>; }; @@ -170,15 +180,19 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, - <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; clock-indices = , , - , , - ; - clock-output-names = "enet1_ipg_root_clk", - "enet1_tx_clk", - "enet1_ahb_clk", - "enet1_ipg_clk", - "enet1_ipg_s_clk"; + , , + , ; + clock-output-names = "enet1_lpcg_timer_clk", + "enet1_lpcg_txc_sampling_clk", + "enet1_lpcg_ahb_clk", + "enet1_lpcg_rgmii_txc_clk", + "enet1_lpcg_ipg_clk", + "enet1_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_1>; }; }; From ce87d936889bdb183590647b9827bb2ae7f674c7 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Fri, 21 May 2021 17:20:42 +0800 Subject: [PATCH 431/511] arm64: dts: freescale: Separate each group of data in the property 'reg' Do not write the 'reg' of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported by reg.yaml. arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml: soc: pcie@3400000:reg:0: \ [0, 54525952, 0, 1048576, 64, 0, 0, 8192] is too long Signed-off-by: Zhen Lei Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 14 +++++------ .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 +++---- .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 12 +++++----- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 24 +++++++++---------- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 24 +++++++++---------- .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 16 ++++++------- .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 16 ++++++------- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 +++++++++---------- 8 files changed, 69 insertions(+), 69 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 9058cfa4980f27..50a72cda472734 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -238,35 +238,35 @@ "fsl,sec-v4.0-rtic"; #address-cells = <1>; #size-cells = <1>; - reg = <0x60000 0x100 0x60e00 0x18>; + reg = <0x60000 0x100>, <0x60e00 0x18>; ranges = <0x0 0x60100 0x500>; rtic_a: rtic-a@0 { compatible = "fsl,sec-v5.4-rtic-memory", "fsl,sec-v5.0-rtic-memory", "fsl,sec-v4.0-rtic-memory"; - reg = <0x00 0x20 0x100 0x100>; + reg = <0x00 0x20>, <0x100 0x100>; }; rtic_b: rtic-b@20 { compatible = "fsl,sec-v5.4-rtic-memory", "fsl,sec-v5.0-rtic-memory", "fsl,sec-v4.0-rtic-memory"; - reg = <0x20 0x20 0x200 0x100>; + reg = <0x20 0x20>, <0x200 0x100>; }; rtic_c: rtic-c@40 { compatible = "fsl,sec-v5.4-rtic-memory", "fsl,sec-v5.0-rtic-memory", "fsl,sec-v4.0-rtic-memory"; - reg = <0x40 0x20 0x300 0x100>; + reg = <0x40 0x20>, <0x300 0x100>; }; rtic_d: rtic-d@60 { compatible = "fsl,sec-v5.4-rtic-memory", "fsl,sec-v5.0-rtic-memory", "fsl,sec-v4.0-rtic-memory"; - reg = <0x60 0x20 0x400 0x100>; + reg = <0x60 0x20>, <0x400 0x100>; }; }; }; @@ -522,8 +522,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1012a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 118 0x4>, /* controller interrupt */ <0 117 0x4>; /* PME interrupt */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 5b500c16c9c10c..2fe12454234d81 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -617,8 +617,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1028a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = , /* PME interrupt */ ; /* aer interrupt */ @@ -644,8 +644,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls1028a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = , ; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 28c51e521cb222..01b01e3204118c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -869,8 +869,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 118 0x4>, /* controller interrupt */ <0 117 0x4>; /* PME interrupt */ @@ -895,8 +895,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 128 0x4>, <0 127 0x4>; @@ -921,8 +921,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 162 0x4>, <0 161 0x4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 39458305e3334c..687fea6d8afa4b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -773,8 +773,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = , /* controller interrupt */ ; /* PME interrupt */ @@ -799,8 +799,8 @@ pcie_ep1: pcie_ep@3400000 { compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; - reg = <0x00 0x03400000 0x0 0x00100000 - 0x40 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03400000 0x0 0x00100000>, + <0x40 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <8>; @@ -809,8 +809,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = , /* controller interrupt */ ; /* PME interrupt */ @@ -835,8 +835,8 @@ pcie_ep2: pcie_ep@3500000 { compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; - reg = <0x00 0x03500000 0x0 0x00100000 - 0x48 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03500000 0x0 0x00100000>, + <0x48 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <8>; @@ -845,8 +845,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = , /* controller interrupt */ ; /* PME interrupt */ @@ -871,8 +871,8 @@ pcie_ep3: pcie_ep@3600000 { compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03600000 0x0 0x00100000 - 0x50 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03600000 0x0 0x00100000>, + <0x50 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <8>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 8ffbc9fde0415e..2fa6cfbef01f9f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -536,8 +536,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; @@ -562,8 +562,8 @@ pcie_ep1: pcie-ep@3400000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03400000 0x0 0x00100000 - 0x20 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03400000 0x0 0x00100000>, + <0x20 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <24>; num-ob-windows = <256>; @@ -573,8 +573,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; @@ -599,8 +599,8 @@ pcie_ep2: pcie-ep@3500000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03500000 0x0 0x00100000 - 0x28 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03500000 0x0 0x00100000>, + <0x28 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <6>; @@ -609,8 +609,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; @@ -635,8 +635,8 @@ pcie_ep3: pcie-ep@3600000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03600000 0x0 0x00100000 - 0x30 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03600000 0x0 0x00100000>, + <0x30 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <6>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 76ab68d2de0bfa..6f6667b70028ef 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -120,32 +120,32 @@ }; &pcie1 { - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x10 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; &pcie2 { - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x12 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; &pcie3 { - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x14 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; &pcie4 { - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ + <0x16 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index da24dc12769839..c3dc38188c17ca 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -121,8 +121,8 @@ &pcie1 { compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; @@ -130,8 +130,8 @@ &pcie2 { compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; @@ -139,8 +139,8 @@ &pcie3 { compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; @@ -148,8 +148,8 @@ &pcie4 { compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ + <0x38 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 0551f6f4c313cb..c4b1a59ba424b2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1089,8 +1089,8 @@ pcie1: pcie@3400000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = , /* AER interrupt */ , /* PME interrupt */ @@ -1117,8 +1117,8 @@ pcie2: pcie@3500000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = , /* AER interrupt */ , /* PME interrupt */ @@ -1145,8 +1145,8 @@ pcie3: pcie@3600000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = , /* AER interrupt */ , /* PME interrupt */ @@ -1173,8 +1173,8 @@ pcie4: pcie@3700000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ + <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = , /* AER interrupt */ , /* PME interrupt */ @@ -1201,8 +1201,8 @@ pcie5: pcie@3800000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ - 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ + <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = , /* AER interrupt */ , /* PME interrupt */ @@ -1229,8 +1229,8 @@ pcie6: pcie@3900000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ - 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ + <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = , /* AER interrupt */ , /* PME interrupt */ From 7ef9a86dfc5092d8873b04ce10846110eeb68d0f Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 26 May 2021 17:22:41 +0200 Subject: [PATCH 432/511] dt-bindings: vendor-prefixes: add congatec Document binding for congatec. Acked-by: Rob Herring Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 71ca69ca91426c..fa951ba1c738c1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -249,6 +249,8 @@ patternProperties: description: Colorful GRP, Shenzhen Xueyushi Technology Ltd. "^compulab,.*": description: CompuLab Ltd. + "^congatec,.*": + description: congatec GmbH "^coreriver,.*": description: CORERIVER Semiconductor Co.,Ltd. "^corpro,.*": From cd044eafd7105275220f6b7140a8a8fb64e0e5af Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 26 May 2021 17:22:42 +0200 Subject: [PATCH 433/511] dt-bindings: arm: fsl: add GE B1x5pv2 boards Document the compatible for GE B1x5pv2 boards. Acked-by: Rob Herring Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index fce2a8670b4925..1c827c1954dc0d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -401,6 +401,17 @@ properties: - const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM - const: fsl,imx6dl + - description: i.MX6DL based congatec QMX6 Boards + items: + - enum: + - ge,imx6dl-b105v2 # General Electric B105v2 + - ge,imx6dl-b105pv2 # General Electric B105Pv2 + - ge,imx6dl-b125v2 # General Electric B125v2 + - ge,imx6dl-b125pv2 # General Electric B125Pv2 + - ge,imx6dl-b155v2 # General Electric B155v2 + - const: congatec,qmx6 + - const: fsl,imx6dl + - description: i.MX6DL based DFI FS700-M60-6DL Board items: - const: dfi,fs700-m60-6dl From 4616c395be9d8d66ed63a3569a527ce4a07071fc Mon Sep 17 00:00:00 2001 From: Li Jun Date: Fri, 28 May 2021 19:29:58 +0800 Subject: [PATCH 434/511] arm64: dts: imx8mm-evk: disable over current for usb1 imx8mm evk board usb1 port does not support over current detection, so disable it. Signed-off-by: Li Jun Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6518f088b2c276..e033d0257b5a13 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -314,6 +314,7 @@ srp-disable; adp-disable; usb-role-switch; + disable-over-current; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; From 21cc1f222e890fa989d1395e47b16777fea46e5f Mon Sep 17 00:00:00 2001 From: Li Jun Date: Fri, 28 May 2021 19:29:59 +0800 Subject: [PATCH 435/511] arm64: dts: imx8mn-evk: disable over current for usb imx8mn evk board usb port does not support over current detection, so disable it. Signed-off-by: Li Jun Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index a0dddba2e5614c..85e65f8719ea59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -193,6 +193,7 @@ srp-disable; adp-disable; usb-role-switch; + disable-over-current; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; From 388b7e223985f64c322619a1c75be4b0a49623d3 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 4 May 2021 19:34:55 +0000 Subject: [PATCH 436/511] dt-bindings: add vendor prefix for welltech Add vendor prefix for Welltech computer Co Ld. Link: https://lore.kernel.org/r/20210504193457.4008384-4-clabbe@baylibre.com Signed-off-by: Corentin Labbe Acked-by: Rob Herring Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b868cefc7c5500..5ff8ec97bd8678 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1244,6 +1244,8 @@ patternProperties: description: Western Digital Corp. "^we,.*": description: Würth Elektronik GmbH. + "^welltech,.*": + description: Welltech Computer Co., Limited. "^wetek,.*": description: WeTek Electronics, limited. "^wexler,.*": From b0a2fbd2a6fcb8dccd88363fc8e2163fd92cd102 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 4 May 2021 19:34:56 +0000 Subject: [PATCH 437/511] dt-bindings: arm: intel-ixp4xx: add welltech,epbx100 Adds welltech,epbx100 as a valid intel-ixp4xx board. Link: https://lore.kernel.org/r/20210504193457.4008384-5-clabbe@baylibre.com Signed-off-by: Corentin Labbe Acked-by: Rob Herring Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml index d72e92bdf7c14e..230bffeec0e50a 100644 --- a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -17,6 +17,7 @@ properties: - items: - enum: - linksys,nslu2 + - welltech,epbx100 - const: intel,ixp42x - items: - enum: From 9321a97c8c1cf76ae315cae5fd4c140bc65e2449 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Tue, 4 May 2021 19:34:57 +0000 Subject: [PATCH 438/511] ARM: dts: add intel-ixp42x-welltech-epbx100 This patch adds devicetree for intel-ixp42x-welltech-epbx100. Link: https://lore.kernel.org/r/20210504193457.4008384-6-clabbe@baylibre.com Signed-off-by: Corentin Labbe Signed-off-by: Olof Johansson --- arch/arm/boot/dts/Makefile | 1 + .../dts/intel-ixp42x-welltech-epbx100.dts | 76 +++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e750..72338df6663a1a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -240,6 +240,7 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorcp.dtb dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-linksys-nslu2.dtb \ + intel-ixp42x-welltech-epbx100.dtb \ intel-ixp43x-gateworks-gw2358.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ keystone-k2hk-evm.dtb \ diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts new file mode 100644 index 00000000000000..84158503be2ac0 --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Corentin Labbe + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" + +/ { + model = "Welltech EPBX100"; + compatible = "welltech,epbx100", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + flash@50000000 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 16 MB of Flash + */ + reg = <0x50000000 0x1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + partition@80000 { + label = "zImage"; + reg = <0x00080000 0x00100000>; + read-only; + }; + partition@180000 { + label = "ramdisk"; + reg = <0x00180000 0x00300000>; + read-only; + }; + partition@480000 { + label = "User"; + reg = <0x00480000 0x00b60000>; + read-only; + }; + partition@fe0000 { + label = "FIS directory"; + reg = <0x00fe0000 0x001f000>; + read-only; + }; + partition@fff000 { + label = "RedBoot config"; + reg = <0x00fff000 0x0001000>; + read-only; + }; + }; + }; +}; From e6f600e72edc723e9c34df09d6efea6334181ec0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 5 Jun 2021 18:10:07 +0200 Subject: [PATCH 439/511] ARM: dts: ixp4xx: Add crypto engine Add the crypto engine as a child of the NPE. Link: https://lore.kernel.org/r/20210605161007.3397216-1-linus.walleij@linaro.org Cc: Corentin Labbe Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/boot/dts/intel-ixp4xx.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index 528d5dc09cfca3..a50427ad05e748 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -113,6 +113,14 @@ npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + + /* NPE-C contains a crypto accelerator */ + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; }; /* This is known as EthB */ From 83107b24c351391dd0a492fc9940d05c14cab0d0 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Sat, 12 Jun 2021 00:05:01 +0200 Subject: [PATCH 440/511] ARM: dts: gemini: add crypto node The SL3516 SoC has a crypto offloader IP. This patch adds it on the gemini SoC Device-tree. Link: https://lore.kernel.org/r/20210611220501.684997-1-linus.walleij@linaro.org Signed-off-by: Corentin Labbe Cc: Herbert Xu Signed-off-by: Linus Walleij Signed-off-by: Olof Johansson --- arch/arm/boot/dts/gemini.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index e5c15fe71a3560..cc053af3c3472d 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -357,6 +357,14 @@ }; }; + crypto: crypto@62000000 { + compatible = "cortina,sl3516-crypto"; + reg = <0x62000000 0x10000>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_SECURITY>; + clocks = <&syscon GEMINI_CLK_GATE_SECURITY>; + }; + ide@63000000 { compatible = "cortina,gemini-pata", "faraday,ftide010"; reg = <0x63000000 0x1000>; From 3fedcc636e28f6188b6bb126199eda031bc707f3 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 12 Jun 2021 20:47:33 +0200 Subject: [PATCH 441/511] ARM: dts: rockchip: add labels to the timer nodes on rk3066a While the kernel doesn't care so much right now, boot loaders like u-boot need to refine the node on their side, so to make life easier for everyone add the labels to the timer nodes on rk3066a. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210612184733.2331-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 511311d257bdbc..b15cbbe23ffc57 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -217,7 +217,7 @@ <150000000>, <75000000>; }; - timer@2000e000 { + timer2: timer@2000e000 { compatible = "snps,dw-apb-timer-osc"; reg = <0x2000e000 0x100>; interrupts = ; @@ -238,7 +238,7 @@ }; }; - timer@20038000 { + timer0: timer@20038000 { compatible = "snps,dw-apb-timer-osc"; reg = <0x20038000 0x100>; interrupts = ; @@ -246,7 +246,7 @@ clock-names = "timer", "pclk"; }; - timer@2003a000 { + timer1: timer@2003a000 { compatible = "snps,dw-apb-timer-osc"; reg = <0x2003a000 0x100>; interrupts = ; From 51094deb330623a172b80f7f1cb43f2d6e165c4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 11 Jun 2021 10:14:14 +0200 Subject: [PATCH 442/511] arm64: dts: rockchip: Add support for USB on helios64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This enables the USB hardware needed to access devices on the sockets J1 and J13. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20210611081414.1448786-1-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-kobol-helios64.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 037dc5cdc3f358..738cfd21df3efb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -155,6 +155,20 @@ }; }; + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_en>; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_perdev>; + }; + vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -407,6 +421,12 @@ }; }; + power { + vcc5v0_usb_en: vcc5v0-usb-en { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc3v0-sd { sdmmc0_pwr_h: sdmmc0-pwr-h { rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; @@ -449,6 +469,30 @@ status = "okay"; }; +&tcphy1 { + /* phy for &usbdrd_dwc3_1 */ + status = "okay"; +}; + +&u2phy1 { + status = "okay"; + + otg-port { + /* phy for &usbdrd_dwc3_1 */ + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + &uart2 { status = "okay"; }; + +&usbdrd3_1 { + status = "okay"; + + usb@fe900000 { + dr_mode = "host"; + status = "okay"; + }; +}; From 1a4eb37f3174d3a54e40392abcfbb9b3949948bb Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 27 May 2021 17:44:51 +0200 Subject: [PATCH 443/511] ARM: dts: rockchip: add power controller for RK3036 Add the power controller node and the correspondending qos nodes for RK3036. Also add the power-domain property to the nodes that are already present. Note: Since the regiser offsets of the axi interconnect QoS are missing in the TRM (RK3036 TRM V1.0), they have been taken from vendor kernel. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210527154455.358869-9-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 9ccefa8282babc..33019d2a22332a 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -111,6 +112,7 @@ assigned-clock-rates = <100000000>; clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; clock-names = "bus", "core"; + power-domains = <&power RK3036_PD_GPU>; resets = <&cru SRST_GPU>; status = "disabled"; }; @@ -124,6 +126,7 @@ resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; reset-names = "axi", "ahb", "dclk"; iommus = <&vop_mmu>; + power-domains = <&power RK3036_PD_VIO>; status = "disabled"; vop_out: port { @@ -142,10 +145,26 @@ interrupts = ; clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; clock-names = "aclk", "iface"; + power-domains = <&power RK3036_PD_VIO>; #iommu-cells = <0>; status = "disabled"; }; + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_vio: qos@1012f000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + gic: interrupt-controller@10139000 { compatible = "arm,gic-400"; interrupt-controller; @@ -301,6 +320,37 @@ compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; reg = <0x20008000 0x1000>; + power: power-controller { + compatible = "rockchip,rk3036-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3036_PD_VIO { + reg = ; + clocks = <&cru ACLK_LCDC>, + <&cru HCLK_LCDC>, + <&cru SCLK_LCDC>; + pm_qos = <&qos_vio>; + #power-domain-cells = <0>; + }; + + power-domain@RK3036_PD_VPU { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3036_PD_GPU { + reg = ; + clocks = <&cru SCLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x1d8>; From 623ba75a5d6b8e196a21f3ed36d26a5f6db459ce Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 27 May 2021 17:44:52 +0200 Subject: [PATCH 444/511] ARM: dts: rockchip: add power controller for RK322x Add the power controller node and the correspondending qos nodes for RK322x. Also add the power-domain property to the nodes that are already present. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210527154455.358869-10-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 111 ++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index cffd7acfb94fc6..ea8ceeb09c0b3e 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -190,6 +191,64 @@ status = "disabled"; }; + power: power-controller { + compatible = "rockchip,rk3228-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3228_PD_VIO { + reg = ; + clocks = <&cru ACLK_HDCP>, + <&cru SCLK_HDCP>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru SCLK_RGA>; + pm_qos = <&qos_hdcp>, + <&qos_iep>, + <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VOP { + reg = ; + clocks =<&cru ACLK_VOP>, + <&cru DCLK_VOP>, + <&cru HCLK_VOP>; + pm_qos = <&qos_vop>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_RKVDEC { + reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + pm_qos = <&qos_rkvdec_r>, + <&qos_rkvdec_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + u2phy0: usb2phy@760 { compatible = "rockchip,rk3228-usb2phy"; reg = <0x0760 0x0c>; @@ -546,6 +605,7 @@ "ppmmu1"; clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; clock-names = "bus", "core"; + power-domains = <&power RK3228_PD_GPU>; resets = <&cru SRST_GPU_A>; status = "disabled"; }; @@ -556,6 +616,7 @@ interrupts = ; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VPU>; #iommu-cells = <0>; status = "disabled"; }; @@ -566,6 +627,7 @@ interrupts = ; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_RKVDEC>; #iommu-cells = <0>; status = "disabled"; }; @@ -579,6 +641,7 @@ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; reset-names = "axi", "ahb", "dclk"; iommus = <&vop_mmu>; + power-domains = <&power RK3228_PD_VOP>; status = "disabled"; vop_out: port { @@ -598,6 +661,7 @@ interrupts = ; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VOP>; #iommu-cells = <0>; status = "disabled"; }; @@ -608,6 +672,7 @@ interrupts = ; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3228_PD_VIO>; resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; reset-names = "core", "axi", "ahb"; }; @@ -618,6 +683,7 @@ interrupts = ; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VIO>; #iommu-cells = <0>; status = "disabled"; }; @@ -792,6 +858,51 @@ status = "disabled"; }; + qos_iep: qos@31030080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030080 0x20>; + }; + + qos_rga_w: qos@31030100 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030100 0x20>; + }; + + qos_hdcp: qos@31030180 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030180 0x20>; + }; + + qos_rga_r: qos@31030200 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030200 0x20>; + }; + + qos_vpu: qos@31040000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31040000 0x20>; + }; + + qos_gpu: qos@31050000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31050000 0x20>; + }; + + qos_vop: qos@31060000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31060000 0x20>; + }; + + qos_rkvdec_r: qos@31070000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070000 0x20>; + }; + + qos_rkvdec_w: qos@31070080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070080 0x20>; + }; + gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; From 1f80a5cf74a60997b92d2cde772edec093bec4d9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Jun 2021 08:54:29 +0200 Subject: [PATCH 445/511] arm64: dts: meson-sm1-odroid: add missing enable gpio and supply for tf_io regulator As described in the schematics of Odroid-C4 and Odroid-HC4, the TF_IO regulator is enabled by the GPIOE_2 GPIO and gets it's supply from VCC_5V. Signed-off-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210607065435.577334-2-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index d14716b3d0f1ea..af40ba461074ad 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -46,6 +46,11 @@ regulator-name = "TF_IO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v>; + + enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; gpios-states = <0>; From 7881df51368027b2d3fed3dcd43b480f45157d81 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Jun 2021 08:54:30 +0200 Subject: [PATCH 446/511] arm64: dts: meson-sm1-odroid: set tf_io regulator gpio as open source According to Odroid-C4 & HC4 Schematics, the TF_3V3N_1V8_EN can be in Hi-Z for 3v3, and since it's the default GPIOAO_6 mode at reset, let switch this GPIO as Open-Source to drive for 1, and input for 0. Signed-off-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210607065435.577334-3-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index af40ba461074ad..e643591633318f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -52,7 +52,7 @@ enable-active-high; regulator-always-on; - gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; + gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; gpios-states = <0>; states = <3300000 0>, From 45d736ab17b44257e15e75e0dba364139fdb0983 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Jun 2021 08:54:31 +0200 Subject: [PATCH 447/511] arm64: dts: meson-sm1-odroid: add 5v regulator gpio As described in the Odroid-C4 & Odroid-HC4 schematics, the 5V regulator is controlled by GPIOH_8 and in Open Drain since this GPIO doesn't support Push-Pull. Signed-off-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210607065435.577334-4-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index e643591633318f..fd0ad85c165bad 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -83,6 +83,8 @@ regulator-max-microvolt = <5000000>; regulator-always-on; vin-supply = <&main_12v>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; }; vcc_1v8: regulator-vcc_1v8 { From 703e84d6615a4a95fb504c8f2e4c9426b86f3930 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Jun 2021 08:54:32 +0200 Subject: [PATCH 448/511] arm64: dts: meson-sm1-odroid-hc4: disable unused USB PHY0 As described in the HC4 schematics, only the USB port B is used, port A is left unconnected. Thus disable PHY0 and remove it from PHYs list. Signed-off-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210607065435.577334-5-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index bf15700c4b153d..0a34b658f9944b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -91,6 +91,10 @@ }; &usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; +}; + +&usb2_phy0 { + status = "disabled"; }; From 164147f094ec5d0fc2c2098a888f4b50cf3096a7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Jun 2021 08:54:33 +0200 Subject: [PATCH 449/511] arm64: dts: meson-sm1-odroid-hc4: add regulators controlled by GPIOH_8 As described in the HC4 schematics, GPIOH_8 controls the USB 5V and 12V regulators used to power the SATA drives. And is set as Open Drain since this GPIO doesn't support Push-Pull. Signed-off-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210607065435.577334-6-narmstrong@baylibre.com --- .../boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index 0a34b658f9944b..fdad6b994c8894 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -44,6 +44,32 @@ }; }; + /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ + p12v_0: regulator-p12v_0 { + compatible = "regulator-fixed"; + regulator-name = "P12V_0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + + /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ + p12v_1: regulator-p12v_1 { + compatible = "regulator-fixed"; + regulator-name = "P12V_1"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + sound { model = "ODROID-HC4"; }; From 7178f340e9299dc886e6ddf6e938f09967902109 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 7 Jun 2021 08:54:34 +0200 Subject: [PATCH 450/511] arm64: dts: meson-sm1-odroid-hc4: add spifc node to ODROID-HC4 Add a node for the XT25F128B SPI-NOR flash to make it accessible from Linux. Signed-off-by: Christian Hewitt Signed-off-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210607065435.577334-7-narmstrong@baylibre.com --- .../boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index fdad6b994c8894..f3f953225bf5ba 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -116,6 +116,20 @@ status = "disabled"; }; +&spifc { + status = "okay"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + }; +}; + &usb { phys = <&usb2_phy1>; phy-names = "usb2-phy1"; From 303d2af21aedeaebe824411fbff912dfcdb48de5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Jun 2021 08:54:35 +0200 Subject: [PATCH 451/511] arm64: dts: meson-sm1-odroid-c4: remove invalid hub_5v regulator Drop the hub_5v regulator which controls the HUB Reset line with GPIOH_4 which is already controlled by a GPIO HOG. Until we can properly describe how to control USB HUBs reset lines, keeping the GPIO HOG is an acceptable solution we use on multiple boards. Signed-off-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210607065435.577334-8-narmstrong@baylibre.com --- .../boot/dts/amlogic/meson-sm1-odroid-c4.dts | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts index 8c327c03d84503..8c30ce63686e33 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts @@ -23,18 +23,6 @@ }; }; - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - sound { model = "ODROID-C4"; }; @@ -58,8 +46,3 @@ &ir { linux,rc-map-name = "rc-odroid"; }; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; -}; From 7db3cde5123e2acdd65ff7458628a9835c804b27 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 4 Jun 2021 19:08:44 +0200 Subject: [PATCH 452/511] ARM: dts: meson: Set the fifo-size of uart_A to 128 bytes The first UART controller in the "Everything-Else" power domain is called uart_A. Unlike all other UARTs (which use a 64 byte fifo-size in hardware) uart_A has a fifo-size of 128 bytes. This UART controller is typically used for Bluetooth HCI. The fifo-size of 128 bytes is valid from all SoCs from Meson6 (or possibly even earlier) all the way up to the latest 64-bit ones. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20210604170844.2201229-1-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 8bae6ed0abb205..bd0e864964e986 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -50,6 +50,7 @@ compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; reg = <0x84c0 0x18>; interrupts = ; + fifo-size = <128>; status = "disabled"; }; From 50c9bfca1bfe9ffd56d8c5deecf9204d14e20bfd Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Tue, 8 Jun 2021 21:49:40 +0300 Subject: [PATCH 453/511] arm64: dts: ti: k3-am642-main: fix ports mac properties The current device tree CPSW3g node adds non-zero "mac-address" property to the ports, which prevents random MAC address assignment to network devices if bootloader failed to update DT. This may cause more then one host to have the same MAC in the network. mac-address = [00 00 de ad be ef]; mac-address = [00 01 de ad be ef]; In addition, there is one MAC address available in eFuse registers which can be used for default port 1. Hence, fix ports MAC properties by: - resetting "mac-address" property to 0 - adding ti,syscon-efuse = <&main_conf 0x200> to Port 1 Fixes: 3753b12877b6 ("arm64: dts: ti: k3-am64-main: Add CPSW DT node") Signed-off-by: Grygorii Strashko Reviewed-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210608184940.25934-1-grygorii.strashko@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index effb9d2e3c25c6..7f7178a7a0558c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -514,7 +514,8 @@ ti,mac-only; label = "port1"; phys = <&phy_gmii_sel 1>; - mac-address = [00 00 de ad be ef]; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&main_conf 0x200>; }; cpsw_port2: port@2 { @@ -522,7 +523,7 @@ ti,mac-only; label = "port2"; phys = <&phy_gmii_sel 2>; - mac-address = [00 01 de ad be ef]; + mac-address = [00 00 00 00 00 00]; }; }; From 4f76ea7b4da1cce9a9bda1fa678ef8036584c66b Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 8 Jun 2021 10:44:13 +0530 Subject: [PATCH 454/511] arm64: dts: ti: am65: align ti,pindir-d0-out-d1-in property with dt-shema ti,pindir-d0-out-d1-in property is expected to be of type boolean. Therefore, fix the property accordingly. Fixes: e180f76d0641 ("arm64: dts: ti: Add support for Siemens IOT2050 boards") Fixes: 5da94b50475a ("arm64: dts: ti: k3-am654: Enable main domain McSPI0") Signed-off-by: Aswath Govindraju Acked-by: Jan Kiszka Reviewed-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210608051414.14873-2-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 8c6b538c53f325..1008e9162ba202 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -576,7 +576,7 @@ #address-cells = <1>; #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index fa057a85e8330b..cfbcebfa37c1df 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -331,7 +331,7 @@ pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>; #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; flash@0{ compatible = "jedec,spi-nor"; From d3f1b155c04d949c843e6028034766aba1e0f8bf Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 8 Jun 2021 10:44:14 +0530 Subject: [PATCH 455/511] arm64: dts: ti: k3-am642-evm: align ti,pindir-d0-out-d1-in property with dt-shema ti,pindir-d0-out-d1-in property is expected to be of type boolean. Therefore, fix the property accordingly. Fixes: 4fb6c04683aa ("arm64: dts: ti: k3-am642-evm: Add support for SPI EEPROM") Signed-off-by: Aswath Govindraju Reviewed-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210608051414.14873-3-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 8c27f563a390b3..dc69db2d10c347 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -336,7 +336,7 @@ &main_spi0 { pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; eeprom@0 { compatible = "microchip,93lc46b"; reg = <0>; From d65f069e50a3f69c3196251bb770b1308c7686e6 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 7 Jun 2021 19:15:58 +0530 Subject: [PATCH 456/511] arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes 8250_omap compatible UART IPs on all SoCs have registers aligned at 4 byte address boundary and constant byte addressability. Thus there is no need for reg-io-width or reg-shift DT properties. These properties are not used by 8250_omap driver nor documented as part of binding document. Therefore drop them. This is in preparation to move omap-serial.txt to YAML format. Signed-off-by: Vignesh Raghavendra Reviewed-by: Lokesh Vutla Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 14 ------------- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 4 ---- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ------ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 20 ------------------- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 4 ---- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 ------------------- .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 4 ---- 9 files changed, 76 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 7f7178a7a0558c..dec54243f45465 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -214,8 +214,6 @@ main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -227,8 +225,6 @@ main_uart1: serial@2810000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -240,8 +236,6 @@ main_uart2: serial@2820000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -253,8 +247,6 @@ main_uart3: serial@2830000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -266,8 +258,6 @@ main_uart4: serial@2840000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -279,8 +269,6 @@ main_uart5: serial@2850000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -292,8 +280,6 @@ main_uart6: serial@2860000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index eaf7edb2ef4dd0..59cc58f7d0c879 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -9,8 +9,6 @@ mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -22,8 +20,6 @@ mcu_uart1: serial@4a10000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index e679394d0b7e66..ba4e5d3e1ed7a6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -84,8 +84,6 @@ main_uart0: serial@2800000 { compatible = "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -95,8 +93,6 @@ main_uart1: serial@2810000 { compatible = "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; @@ -105,8 +101,6 @@ main_uart2: serial@2820000 { compatible = "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index f5b8ef2f5f773a..c93ff1520a0e28 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -23,8 +23,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <96000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 7cb864b4d74a83..9d21cdf6fce8fa 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -50,8 +50,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,am654-uart"; reg = <0x42300000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index a4b4b17a6ad74a..e8a41d09b45f21 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -301,8 +301,6 @@ main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -314,8 +312,6 @@ main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -327,8 +323,6 @@ main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -340,8 +334,6 @@ main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -353,8 +345,6 @@ main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -366,8 +356,6 @@ main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -379,8 +367,6 @@ main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -392,8 +378,6 @@ main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -405,8 +389,6 @@ main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -418,8 +400,6 @@ main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 343449af53fb90..1044ec6c4b0d4b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -73,8 +73,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -86,8 +84,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <96000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 2ce17cafffe214..cf3482376c1e61 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -789,8 +789,6 @@ main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -802,8 +800,6 @@ main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -815,8 +811,6 @@ main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -828,8 +822,6 @@ main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -841,8 +833,6 @@ main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -854,8 +844,6 @@ main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -867,8 +855,6 @@ main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -880,8 +866,6 @@ main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -893,8 +877,6 @@ main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -906,8 +888,6 @@ main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 5e825e4d0306d1..d2dceda72fe977 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -73,8 +73,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; @@ -86,8 +84,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = ; clock-frequency = <96000000>; current-speed = <115200>; From 81cfa462e458405f58b23f45ddd9439c70bf5347 Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Thu, 10 Jun 2021 12:41:47 +0530 Subject: [PATCH 457/511] arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card The calculations for the DLL register values are based on the clock rate of the reference clock. Provide the reference clock in the definition of the two SDHCI controllers to not rely on the default values. Reviewed-by: Konrad Dybcio Signed-off-by: Shaik Sajida Bhanu Link: https://lore.kernel.org/r/1623309107-27833-1-git-send-email-sbhanu@codeaurora.org [bjorn: Rewrote commit message] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 52115e0359bdf8..fb1d9ad8bf6c8d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -701,8 +701,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -2564,8 +2565,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; From 172cdcaefea5c297fdb3d20b7d5aff60ae4fbce6 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 8 Jun 2021 09:52:06 +0900 Subject: [PATCH 458/511] arm64: dts: visconti: Add PWM support for TMPV7708 SoC Add PWM node in TMPV7708's dtsi, and tmpv7708-rm-mbrc boards's dts. Signed-off-by: Nobuhiro Iwamatsu --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 8 ++++++++ arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 9 +++++++++ arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 5 +++++ 3 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index bf0620afe117bb..29a4d9fc1e4719 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -68,3 +68,11 @@ &gpio { status = "okay"; }; + +&pwm_mux { + groups = "pwm0_gpio16_grp", "pwm1_gpio17_grp", "pwm2_gpio18_grp", "pwm3_gpio19_grp"; +}; + +&pwm { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 17934fd9a14c6b..4b4231ff43cfd2 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -432,6 +432,15 @@ reg = <0 0x28330000 0 0x1000>; status = "disabled"; }; + + pwm: pwm@241c0000 { + compatible = "toshiba,visconti-pwm"; + reg = <0 0x241c0000 0 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_mux>; + #pwm-cells = <2>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi index 34de00015a7f80..a480c6ba5f5d7b 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi @@ -90,4 +90,9 @@ groups = "i2c8_grp"; bias-pull-up; }; + + pwm_mux: pwm_mux { + function = "pwm"; + }; + }; From c2d0501cdc6c54d3711f230572935a492317a232 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 14 Jun 2021 21:33:08 +0200 Subject: [PATCH 459/511] arm64: dts: exynos: enable PMIC wakeup from suspend on TM2 The RTC on S2MPS13 PMIC can wakeup the system from suspend to RAM. Add a generic property for this. Link: https://lore.kernel.org/r/20210614193309.20248-2-krzysztof.kozlowski@canonical.com Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210420164943.11152-11-krzysztof.kozlowski@canonical.com Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 773d9abe3a4491..cbcc01a66aab75 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -391,6 +391,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; reg = <0x66>; samsung,s2mps11-wrstbi-ground; + wakeup-source; s2mps13_osc: clocks { compatible = "samsung,s2mps13-clk"; From 8f610169a2865f6c6383d966ebbd6814c79d0116 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Fri, 11 Jun 2021 22:08:01 +0200 Subject: [PATCH 460/511] ARM: dts: mstar: Add watchdog device node This adds the definition of both an oscillator at 12Mhz required by the the watchdog and the watchdog device node. Signed-off-by: Romain Perier Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 075d583d6f40c5..2273295e140f1d 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -60,6 +60,14 @@ clock-frequency = <32768>; status = "disabled"; }; + + xtal_div2: xtal_div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&xtal>; + clock-div = <2>; + clock-mult = <1>; + }; }; soc: soc { @@ -101,6 +109,12 @@ mask = <0x79>; }; + watchdog@6000 { + compatible = "mstar,msc313e-wdt"; + reg = <0x6000 0x1f>; + clocks = <&xtal_div2>; + }; + intc_fiq: interrupt-controller@201310 { compatible = "mstar,mst-intc"; reg = <0x201310 0x40>; From 1534fac32fc6a4320c54b2007e2f5b6f9a8ff336 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 15 Jun 2021 13:15:36 +0530 Subject: [PATCH 461/511] dt-bindings: arm: qcom: Add compatible for sm8150-mtp board sm8150-mtp board is based on Qualcomm Snapdragon sm8150 SoC. Add support for the same in dt-bindings. Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210615074543.26700-4-bhupesh.sharma@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2babb95de35448..5567029044cb18 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -42,6 +42,7 @@ description: | sdm660 sdm845 sdx55 + sm8150 sm8250 sm8350 @@ -199,6 +200,11 @@ properties: - qcom,ipq6018-cp01-c1 - const: qcom,ipq6018 + - items: + - enum: + - qcom,sm8150-mtp + - const: qcom,sm8150 + - items: - enum: - qcom,qrb5165-rb5 From 0bc14d4ad3a7646052b98e9e332a514167a7052f Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 15 Jun 2021 13:15:37 +0530 Subject: [PATCH 462/511] dt-bindings: arm: qcom: Add compatible for SA8155p-adp board SA8155p-adp board is based on Qualcomm Snapdragon sa8155p SoC which is similar to the sm8150 SoC. Add support for the same in dt-bindings. Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210615074543.26700-5-bhupesh.sharma@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 5567029044cb18..9720b00c41d200 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -36,6 +36,7 @@ description: | msm8992 msm8994 msm8996 + sa8155p sc7180 sc7280 sdm630 @@ -48,6 +49,7 @@ description: | The 'board' element must be one of the following strings: + adp cdp cp01-c1 dragonboard @@ -200,6 +202,11 @@ properties: - qcom,ipq6018-cp01-c1 - const: qcom,ipq6018 + - items: + - enum: + - qcom,sa8155p-adp + - const: qcom,sa8155p + - items: - enum: - qcom,sm8150-mtp From 0c25dad9f2a74f63986edcca9001a1269f744916 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 13 Jun 2021 13:06:35 +0200 Subject: [PATCH 463/511] arm64: dts: qcom: sm8250: Don't disable MDP explicitly DPU/MDSS is borderline useless without MDP, so disabling both of them makes little sense. With this change, enabling mdss will be enough. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210613110635.46537-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 75f9476109e69c..b47446b512b558 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2424,8 +2424,6 @@ interrupt-parent = <&mdss>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ports { #address-cells = <1>; #size-cells = <0>; From 40f7d36db8fdad23561f9e587595a5be99e2aa5d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 13 Jun 2021 13:43:56 +0200 Subject: [PATCH 464/511] arm64: dts: qcom: sm8250: Add size/address-cells to dsi[01] Add the aforementioned properties in the SoC DTSI so that everybody doesn't have to copy that into their device DTs, effectively reducing code duplication. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210613114356.82358-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index b47446b512b558..d40f0b4035c6b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2497,6 +2497,9 @@ status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -2564,6 +2567,9 @@ status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + ports { #address-cells = <1>; #size-cells = <0>; From dc2f86369b157dfe4dccd31497d2e3c541e7239d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 13 Jun 2021 20:53:34 +0200 Subject: [PATCH 465/511] arm64: dts: qcom: sm8250: Fix pcie2_lane unit address The previous one was likely a mistaken copy from pcie1_lane. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210613185334.306225-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d40f0b4035c6b8..f087f8837a5ea0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1470,7 +1470,7 @@ status = "disabled"; - pcie2_lane: lanes@1c0e200 { + pcie2_lane: lanes@1c16200 { reg = <0 0x1c16200 0 0x170>, /* tx0 */ <0 0x1c16400 0 0x200>, /* rx0 */ <0 0x1c16a00 0 0x1f0>, /* pcs */ From 15049bb59732e530ca92767d051e38714174c0a2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 15 Jun 2021 01:56:30 +0200 Subject: [PATCH 466/511] arm64: dts: qcom: sm8250: Add GPI DMA nodes Add and configure GPI DMA nodes to enable the way for peripherals to make DMA transfers. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210614235630.445501-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 64 ++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f087f8837a5ea0..12217b3ce6b65d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -519,6 +520,26 @@ }; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8250-gpi-dma"; + reg = <0 0x00800000 0 0x70000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x76 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -714,6 +735,29 @@ }; }; + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8250-gpi-dma"; + reg = <0 0x00900000 0 0x70000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <15>; + dma-channel-mask = <0x7ff>; + iommus = <&apps_smmu 0x5b6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; @@ -961,6 +1005,26 @@ }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8250-gpi-dma"; + reg = <0 0x00a00000 0 0x70000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x56 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; From ece28cb5ed729c66ed8bfff79f4fff4302d3d8b8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 12 Jun 2021 21:23:56 +0200 Subject: [PATCH 467/511] arm64: dts: qcom: sm8250: Disable Adreno and Venus by default Components that rely on proprietary (not to mention signed!) firmware should not be enabled by default, as lack of the aforementioned firmware could cause various issues, from random errors to straight-up failing to boot. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210612192358.62602-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 10 ++++++++++ arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 12 ++++++++++++ arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 10 ++++++++++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 4 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 5f41de20aa22d6..a5b742325261ad 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -552,7 +552,13 @@ vdds-supply = <&vreg_l5a_0p88>; }; +&gmu { + status = "okay"; +}; + &gpu { + status = "okay"; + zap-shader { memory-region = <&gpu_mem>; firmware-name = "qcom/sm8250/a650_zap.mbn"; @@ -1352,6 +1358,10 @@ qcom,dmic-sample-rate = <600000>; }; +&venus { + status = "okay"; +}; + /* PINCTRL - additions to nodes defined in sm8250.dtsi */ &qup_spi0_cs_gpio { drive-strength = <6>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index c3a2c5aa6fe9c8..397359ee2f8538 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -365,6 +365,14 @@ }; }; +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; @@ -452,3 +460,7 @@ &usb_2_dwc3 { dr_mode = "host"; }; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index cfc4d1febe0f9f..062b944be91d87 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -465,7 +465,13 @@ firmware-name = "qcom/sm8250/cdsp.mbn"; }; +&gmu { + status = "okay"; +}; + &gpu { + status = "okay"; + zap-shader { memory-region = <&gpu_mem>; firmware-name = "qcom/sm8250/a650_zap.mbn"; @@ -691,3 +697,7 @@ vdda-phy-supply = <&vreg_l9a_1p2>; vdda-pll-supply = <&vreg_l18a_0p9>; }; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 12217b3ce6b65d..995e93d3b78a7f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1810,6 +1810,8 @@ qcom,gmu = <&gmu>; + status = "disabled"; + zap-shader { memory-region = <&gpu_mem>; }; @@ -1883,6 +1885,8 @@ operating-points-v2 = <&gmu_opp_table>; + status = "disabled"; + gmu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2387,6 +2391,8 @@ <&videocc VIDEO_CC_MVS0C_CLK_ARES>; reset-names = "bus", "core"; + status = "disabled"; + video-decoder { compatible = "venus-decoder"; }; From b1dc3c6b3dabbedaf896a3c1a998da191c311c70 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Jun 2021 22:33:00 +0200 Subject: [PATCH 468/511] arm64: dts: qcom: sm8150: Disable Adreno and modem by default Components that rely on proprietary (not to mention signed!) firmware should not be enabled by default, as lack of the aforementioned firmware could cause various issues, from random errors to straight-up failing to boot. Not enabling modem back on the HDK, as it uses a sa8150. Also fixed a sorting mistake in both boards' dt while at it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210611203301.101067-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 10 +++++++++- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 10 +++++++++- arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 ++++++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index fb2cf3d987a180..50ee3bb97325ac 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -354,7 +354,11 @@ }; }; -&qupv3_id_1 { +&gmu { + status = "okay"; +}; + +&gpu { status = "okay"; }; @@ -372,6 +376,10 @@ }; }; +&qupv3_id_1 { + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 3774f8e6341640..7de54b2e497e82 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -349,7 +349,11 @@ }; }; -&qupv3_id_1 { +&gmu { + status = "okay"; +}; + +&gpu { status = "okay"; }; @@ -367,6 +371,10 @@ }; }; +&qupv3_id_1 { + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8150/adsp.mdt"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 142cf786c6cf16..612dda0fef4385 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1152,6 +1152,8 @@ qcom,gmu = <&gmu>; + status = "disabled"; + zap-shader { memory-region = <&gpu_mem>; }; @@ -1219,6 +1221,8 @@ operating-points-v2 = <&gmu_opp_table>; + status = "disabled"; + gmu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -1566,6 +1570,8 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + status = "disabled"; + glink-edge { interrupts = ; label = "modem"; From d0a6ce59ea4e529e30df950e3f0f61533be5301c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Jun 2021 22:33:01 +0200 Subject: [PATCH 469/511] arm64: dts: qcom: sm8150: Add support for SONY Xperia 1 / 5 (Kumano platform) Add support for SONY Xperia 1 and 5 smartphones, both based on the Qualcomm SM8150 chipset. There also exist 5G-capable versions of these devices, but they weren't sold much (if at all) outside Japan. The devices are affected by a scary UFS behaviour where sending a certain UFS command (which is worked around on downstream) renders the device unbootable, by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly disabled for now. Downstream workaround: https://github.com/kholk/kernel/commit/2e7a9ee1c91a016baa0b826a7752ec45663a0561 Reviewed-by: AngeloGioacchino Del Regno Tested-by: Marijn Suijten (On Bahamut) Tested-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210611203301.101067-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/pm8150.dtsi | 3 +- .../sm8150-sony-xperia-kumano-bahamut.dts | 19 + .../sm8150-sony-xperia-kumano-griffin.dts | 13 + .../dts/qcom/sm8150-sony-xperia-kumano.dtsi | 452 ++++++++++++++++++ 5 files changed, 488 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ec3b2a33eec8a6..b8e0af7cf75724 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -77,6 +77,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index fa4ea7ded0ab9d..35ddac1ccd46e8 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -50,7 +50,8 @@ pon: power-on@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; - pwrkey { + + pon_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts new file mode 100644 index 00000000000000..3b55fdda767a1e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8150-sony-xperia-kumano.dtsi" + +/ { + model = "Sony Xperia 5"; + compatible = "sony,bahamut-generic", "qcom,sm8150"; +}; + +&framebuffer { + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts new file mode 100644 index 00000000000000..6f490ec284bd45 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8150-sony-xperia-kumano.dtsi" + +/ { + model = "Sony Xperia 1"; + compatible = "sony,griffin-generic", "qcom,sm8150"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi new file mode 100644 index 00000000000000..014fe3a315489b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include +#include +#include "sm8150.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/delete-node/ &cdsp_mem; +/delete-node/ &gpu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &mpss_mem; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &venus_mem; + +/ { + qcom,msm-id = <339 0x20000>; /* SM8150 v2 */ + qcom,board-id = <8 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x9c000000 0 0x2300000>; + width = <1644>; + height = <3840>; + stride = <(1644 * 4)>; + format = "a8r8g8b8"; + /* + * That's (going to be) a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet (& no dispcc either).. + */ + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8150 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + mpss_mem: memory@8dc00000 { + reg = <0x0 0x8dc00000 0x0 0x9600000>; + no-map; + }; + + venus_mem: memory@97200000 { + reg = <0x0 0x97200000 0x0 0x500000>; + no-map; + }; + + slpi_mem: memory@97700000 { + reg = <0x0 0x97700000 0x0 0x1400000>; + no-map; + }; + + ipa_fw_mem: memory@98b00000 { + reg = <0x0 0x98b00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@98b10000 { + reg = <0x0 0x98b10000 0x0 0x5000>; + no-map; + }; + + gpu_mem: memory@98b15000 { + reg = <0x0 0x98b15000 0x0 0x2000>; + no-map; + }; + + spss_mem: memory@98c00000 { + reg = <0x0 0x98c00000 0x0 0x100000>; + no-map; + }; + + cdsp_mem: memory@98d00000 { + reg = <0x0 0x98d00000 0x0 0x1400000>; + no-map; + }; + + cont_splash_mem: memory@9c000000 { + reg = <0x0 0x9c000000 0x0 0x2400000>; + no-map; + }; + + cdsp_sec_mem: memory@a4c00000 { + reg = <0x0 0xa4c00000 0x0 0x3c00000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x1000>; + console-size = <0x40000>; + msg-size = <0x20000 0x20000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&adsp_mem { + reg = <0x0 0x8be00000 0x0 0x1e00000>; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s2a_0p6: smps2 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-initial-mode = ; + }; + + vreg_s5a_1p9: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s6a_0p9: smps6 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + vreg_l1a_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vreg_l2a_3p1: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p8: ldo3 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p875: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p2: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10a_2p5: ldo10 { + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l11a_0p8: ldo11 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + /* L13 is unused. */ + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p7: ldo15 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l18a_0p8: ldo18 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + vreg_bob: bob { + regulator-min-microvolt = <3350000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + + vreg_s1c_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; + + /* PM8009 is not present on these boards, even if downstream sources suggest so. */ +}; + +&i2c4 { + status = "okay"; + + /* Qcom SMB1355 @ c */ + /* Qcom SMB1390 @ 10 */ + /* NXP PN553 NFC @ 28 */ + /* Qcom FSA4480 USB-C audio switch @ 43 */ +}; + +&i2c7 { + status = "okay"; + + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&i2c10 { + status = "okay"; + + /* Samsung touchscreen @ 48 */ +}; + +&pon_pwrkey { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <126 4>; +}; + +&uart2 { + status = "okay"; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l5a_0p875>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l18a_0p8>; +}; From 8eaa6501ef2671daba3a595852ec453fe5a7d34c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 02:23:19 +0200 Subject: [PATCH 470/511] arm64: dts: qcom: sm8250: Add SDHCI2 sleep mode pinctrl Add required pins for SDHCI2, so that the interface can work reliably. This commit adds sleep_state setup to the SoC DTSI, as it is common for all boards. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616002321.74155-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 995e93d3b78a7f..29107c380271ee 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3469,6 +3469,26 @@ output-high; }; }; + + sdc2_sleep_state: sdc2-sleep { + clk { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { From 759488004ffb7f3b3190677bc7ddc1d8137974aa Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 02:23:20 +0200 Subject: [PATCH 471/511] arm64: dts: qcom: sm8250: Move gpio.h inclusion to SoC DTSI Almost any board that boots and has a way to interact with it (say for the rare cases of just-pstore or let's-rely-on-bootloader-setup) needs to set some GPIOs, so it makes no sense to include gpio.h separately each time. Hence move it to SoC DTSI. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616002321.74155-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 1 - arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index a5b742325261ad..d5a4f5a27da68b 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -5,7 +5,6 @@ /dts-v1/; -#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 397359ee2f8538..bc6f81254ef766 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -6,7 +6,6 @@ /dts-v1/; #include -#include #include "sm8250.dtsi" #include "pm8150.dtsi" #include "pm8150b.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 29107c380271ee..b8d76b37928bbc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include From 69cdb97ef6529b6b23c81da37bab7b183af7b8ee Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 02:23:21 +0200 Subject: [PATCH 472/511] arm64: dts: qcom: sm8250: Add support for SONY Xperia 1 II / 5 II (Edo platform) Add support for SONY Xperia 1 II and 5 II smartphones (read one/five mark two). They are based on the Qualcomm SM8250 chipset and both feature 5G modems. There also exists a third Edo board, namely the Xperia PRO (PDX204), but it's $2500 and no developers have obtained it so far (to my knowledge). The devices are affected by a scary UFS behaviour where sending a certain UFS command (which is worked around on downstream) renders the device unbootable, by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly disabled for now. Downstream workaround: https://github.com/kholk/kernel/commit/2e7a9ee1c91a016baa0b826a7752ec45663a0561 Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616002321.74155-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/sm8250-sony-xperia-edo-pdx203.dts | 15 + .../qcom/sm8250-sony-xperia-edo-pdx206.dts | 24 + .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 525 ++++++++++++++++++ 4 files changed, 566 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b8e0af7cf75724..9ea7f50364acf3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -81,5 +81,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts new file mode 100644 index 00000000000000..79afeb07f4a247 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8250-sony-xperia-edo.dtsi" + +/ { + model = "Sony Xperia 1 II"; + compatible = "sony,pdx203-generic", "qcom,sm8250"; +}; + +/delete-node/ &vreg_l7f_1p8; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts new file mode 100644 index 00000000000000..999b662f46799a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +/dts-v1/; + +#include "sm8250-sony-xperia-edo.dtsi" + +/ { + model = "Sony Xperia 5 II"; + compatible = "sony,pdx206-generic", "qcom,sm8250"; +}; + +&framebuffer { + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; +}; + +&vreg_l2f_1p3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi new file mode 100644 index 00000000000000..0db63eb08c60df --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -0,0 +1,525 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include +#include "sm8250.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" +#include "pm8009.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &spss_mem; +/delete-node/ &cdsp_secure_heap; + +/ { + qcom,msm-id = <356 0x20001>; /* SM8250 v2.1 */ + qcom,board-id = <0x10008 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x9c000000 0 0x2300000>; + width = <1644>; + height = <3840>; + stride = <(1644 * 4)>; + format = "a8r8g8b8"; + /* + * That's a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet.. + */ + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + power-domains = <&dispcc MDSS_GDSC>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* S6c is really ebi.lvl but it's there for supply map completeness sake. */ + vreg_s6c_0p88: smpc6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s6c_0p88"; + + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + adsp_mem: memory@8a100000 { + reg = <0x0 0x8a100000 0x0 0x2500000>; + no-map; + }; + + spss_mem: memory@8c600000 { + reg = <0x0 0x8c600000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: memory@8c700000 { + reg = <0x0 0x8c700000 0x0 0x4600000>; + no-map; + }; + + cont_splash_mem: memory@9c000000 { + reg = <0x0 0x9c000000 0x0 0x2300000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x1000>; + console-size = <0x40000>; + msg-size = <0x20000 0x20000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p6>; + vdd-l6-l9-supply = <&vreg_s8c_1p2>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + /* (S1+S2+S3) - cx.lvl (ARC) */ + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1920000>; + regulator-initial-mode = ; + }; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s6a_0p6: smps6 { + regulator-name = "vreg_s6a_0p6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + /* L4 - lmx.lvl (ARC) */ + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + /* L7 is unused. */ + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + /* L10 is unused, L11 - lcx.lvl (ARC) */ + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + /* L13 is unused. */ + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + }; + + /* L15 & L16 are unused. */ + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l18a_0p9: ldo18 { + regulator-name = "vreg_l18a_0p9"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + /* + * Remaining regulators that are not yet supported: + * OLEDB: 4925000-8100000 + * ab: 4600000-6100000 + * ibb: 800000-5400000 + */ + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p2>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3350000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + /* + * S1-S6 are ARCs: + * (S1+S2) - gfx.lvl, + * S3 - mx.lvl, + * (S4+S5) - mmcx.lvl, + * S6 - ebi.lvl + */ + + vreg_s7c_0p35: smps7 { + regulator-name = "vreg_s7c_0p35"; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s8c_1p2: smps8 { + regulator-name = "vreg_s8c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + /* L2-4 are unused. */ + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p9: ldo6 { + regulator-name = "vreg_l6c_2p9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + vreg_l7c_2p85: ldo7 { + regulator-name = "vreg_l7c_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-name = "vreg_l9c_2p9"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + vreg_l10c_3p3: ldo10 { + regulator-name = "vreg_l10c_3p3"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3296000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p0: ldo11 { + regulator-name = "vreg_l11c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + vdd-l2-supply = <&vreg_s8c_1p2>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_s1f_1p2: smps1 { + regulator-name = "vreg_s1f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s2f_0p5: smps2 { + regulator-name = "vreg_s2f_0p5"; + regulator-min-microvolt = <512000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + /* L1 is unused. */ + + vreg_l2f_1p3: ldo2 { + regulator-name = "vreg_l2f_1p3"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + /* L3 & L4 are unused. */ + + vreg_l5f_2p8: ldo5 { + regulator-name = "vreg_l5f_2p85"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6f_2p8: ldo6 { + regulator-name = "vreg_l6f_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* NXP PN553 NFC @ 28 */ +}; + +&i2c2 { + status = "okay"; + clock-frequency = <1000000>; + + /* Dual Cirrus Logic CS35L41 amps @ 40, 41 */ +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + /* Dialog SLG51000 CMIC @ 75 */ +}; + +&i2c9 { + status = "okay"; + clock-frequency = <400000>; + + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&i2c13 { + status = "okay"; + clock-frequency = <400000>; + + /* Samsung touchscreen @ 48 */ +}; + +&i2c15 { + status = "okay"; + clock-frequency = <400000>; + + /* Qcom SMB1390 @ 10 */ + /* Silicon Labs SI4704 FM Radio Receiver @ 11 */ + /* Qcom SMB1390_slave @ 18 */ + /* HALO HL6111R Qi charger @ 25 */ + /* Richwave RTC6226 FM Radio Receiver @ 64 */ +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + bus-width = <4>; + no-sdio; + no-emmc; +}; + +&tlmm { + gpio-reserved-ranges = <40 4>, <52 4>; + + sdc2_default_state: sdc2-default { + clk { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sd-card-det-n { + pins = "gpio77"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&uart12 { + status = "okay"; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l2a_3p1>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p9>; +}; From b135d097eb1a2586ee2c0ebcc0d0aa4a9b641b68 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 13 Jun 2021 14:48:22 +0200 Subject: [PATCH 473/511] arm64: dts: qcom: sm8[12]50-pm8150: Move RESIN to pm8150 dtsi It's not worth duplicating the same node over and over and over and over again, so let's keep the common bits in the pm8150 DTSI, making only changing the status and keycode necessary. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210613124822.124039-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 9 +++++++++ arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 18 +++++++----------- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 18 +++++++----------- arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 20 ++++++++------------ 4 files changed, 31 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 35ddac1ccd46e8..c566a64b1373fc 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -60,6 +60,15 @@ status = "disabled"; }; + + pon_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + + status = "disabled"; + }; }; pm8150_temp: temp-alarm@2400 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 50ee3bb97325ac..335aa0753fc023 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -362,18 +362,14 @@ status = "okay"; }; -&pon { - pwrkey { - status = "okay"; - }; +&pon_pwrkey { + status = "okay"; +}; - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; +&pon_resin { + status = "okay"; + + linux,code = ; }; &qupv3_id_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 7de54b2e497e82..53edf754116926 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -357,18 +357,14 @@ status = "okay"; }; -&pon { - pwrkey { - status = "okay"; - }; +&pon_pwrkey { + status = "okay"; +}; - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; +&pon_resin { + status = "okay"; + + linux,code = ; }; &qupv3_id_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index bc6f81254ef766..47742816ac2fe0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -372,22 +372,18 @@ status = "okay"; }; -&qupv3_id_1 { +&pon_pwrkey { status = "okay"; }; -&pon { - pwrkey { - status = "okay"; - }; +&pon_resin { + status = "okay"; - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; + linux,code = ; +}; + +&qupv3_id_1 { + status = "okay"; }; &tlmm { From 263820efa3fb08cc606736b68290d9be9c46e2e5 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Wed, 16 Jun 2021 22:42:22 +0530 Subject: [PATCH 474/511] arm64: dts: ti: k3-am64-main: Update TF-A's maximum size and node name The maximum size of TF-A 2.5 has been increased to 0x1c000 [1]. In order to account for future expansions too, increase the allocated size for TF-A to 0x20000, in the device tree node. Also, update the node name to "tfa-sram". [1] - https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=2fb5312f61a7de8b7a70e1639199c4f14a10b6f9 Signed-off-by: Aswath Govindraju Reviewed-by: Suman Anna Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210616171224.24635-2-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index dec54243f45465..e918afc2298ee9 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -24,8 +24,8 @@ #size-cells = <1>; ranges = <0x0 0x00 0x70000000 0x200000>; - atf-sram@0 { - reg = <0x0 0x1a000>; + tfa-sram@0 { + reg = <0x0 0x20000>; }; }; From 454a9d4aaacb89daea350d21628992bb83de649f Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Wed, 16 Jun 2021 22:42:23 +0530 Subject: [PATCH 475/511] arm64: dts: ti: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication The final 128KB in SRAM is reserved by default for DMSC-lite code and secure proxy communication buffer. The memory region used for DMSC-lite code can be optionally freed up by secure firmware API[1]. However, the buffer for secure proxy communication is not configurable. This default hardware configuration is unique for AM64. Therefore, indicate the area reserved for DMSC-lite code and secure proxy communication buffer in the oc_sram device tree node. [1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover Signed-off-by: Aswath Govindraju Reviewed-by: Suman Anna Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210616171224.24635-3-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index e918afc2298ee9..27888ee6f039c8 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -27,6 +27,14 @@ tfa-sram@0 { reg = <0x0 0x20000>; }; + + dmsc-sram@1e0000 { + reg = <0x1e0000 0x1c000>; + }; + + sproxy-sram@1fc000 { + reg = <0x1fc000 0x4000>; + }; }; main_conf: syscon@43000000 { From 3de27ef12ccb50205e602d92f29d082429aa2964 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Wed, 16 Jun 2021 22:42:24 +0530 Subject: [PATCH 476/511] arm64: dts: ti: k3-am64-main: Update TF-A load address to workaround USB DFU limitation Due to a limitation for USB DFU boot mode, SPL load address has to be less than or equal to 0x70001000. So, load address of SPL and TF-A have been moved to 0x70000000 and 0x701c0000 respectively, in U-Boot version 2021.10. Therefore, update TF-A's location in the device tree node. Signed-off-by: Aswath Govindraju Reviewed-by: Suman Anna Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210616171224.24635-4-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 27888ee6f039c8..62d2b8fff67dff 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -24,8 +24,8 @@ #size-cells = <1>; ranges = <0x0 0x00 0x70000000 0x200000>; - tfa-sram@0 { - reg = <0x0 0x20000>; + tfa-sram@1c0000 { + reg = <0x1c0000 0x20000>; }; dmsc-sram@1e0000 { From e3211e414d26cda43f3093fd09e5d8d0a797648f Mon Sep 17 00:00:00 2001 From: Hao Fang Date: Sat, 22 May 2021 18:20:32 +0800 Subject: [PATCH 477/511] arm64: dts: hisilicon: use the correct HiSilicon copyright s/Hisilicon/HiSilicon/. It should use capital S, according to the official website https://www.hisilicon.com/en. Signed-off-by: Hao Fang Acked-by: Rob Herring Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts | 2 +- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 2 +- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 2 +- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 2 +- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 2 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 2 +- include/dt-bindings/pinctrl/hisi.h | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi index d607f2f6698ca3..79a55a0fa2f1a3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi @@ -3,7 +3,7 @@ /* * dtsi for Hisilicon Hi3660 Coresight * - * Copyright (C) 2016-2018 Hisilicon Ltd. + * Copyright (C) 2016-2018 HiSilicon Ltd. * * Author: Wanglai Shi * diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 963300eede1775..f68580dc87d8b2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -2,7 +2,7 @@ /* * dts file for Hisilicon HiKey960 Development Board * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. * */ diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index cab89dc6f59612..f1ec87c058421d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -2,7 +2,7 @@ /* * dts file for Hisilicon Hi3660 SoC * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. */ #include diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index 7f9f9886c3497c..d8abf442ee7e15 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -2,7 +2,7 @@ /* * dts file for Hisilicon HiKey970 Development Board * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. * Copyright (C) 2018, Linaro Ltd. * */ diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 8830795c8efc5a..20698cfd06379c 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -2,7 +2,7 @@ /* * dts file for Hisilicon Hi3670 SoC * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. * Copyright (C) 2018, Linaro Ltd. */ diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 7b3010f448c5c2..3f387f4cf5e023 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -2,7 +2,7 @@ /* * dtsi file for Hisilicon Hi6220 coresight * - * Copyright (C) 2017 Hisilicon Ltd. + * Copyright (C) 2017 HiSilicon Ltd. * * Author: Pengcheng Li * Leo Yan diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 91d08673c02eff..3df2afb2f63796 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -2,7 +2,7 @@ /* * dts file for Hisilicon HiKey Development Board * - * Copyright (C) 2015, Hisilicon Ltd. + * Copyright (C) 2015, HiSilicon Ltd. * */ diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index d426c6c8722b30..dde9371dc54510 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -2,7 +2,7 @@ /* * dts file for Hisilicon Hi6220 SoC * - * Copyright (C) 2015, Hisilicon Ltd. + * Copyright (C) 2015, HiSilicon Ltd. */ #include diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index 369b69b17b916e..40f3e00ac83266 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D02 Development Board * - * Copyright (C) 2014,2015 Hisilicon Ltd. + * Copyright (C) 2014,2015 HiSilicon Ltd. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 4aed8d440b3aa5..7b2abd10d3d680 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D02 Development Board * - * Copyright (C) 2014,2015 Hisilicon Ltd. + * Copyright (C) 2014,2015 HiSilicon Ltd. */ #include diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts index 9f4a930e734db9..35af5d3821e8e6 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts +++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D03 Development Board * - * Copyright (C) 2016 Hisilicon Ltd. + * Copyright (C) 2016 HiSilicon Ltd. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 7deca5f763d503..70d7732dd34855 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D03 Development Board * - * Copyright (C) 2016 Hisilicon Ltd. + * Copyright (C) 2016 HiSilicon Ltd. */ #include diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts index 81a2312c8a2675..c3df67845f0313 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D05 Development Board * - * Copyright (C) 2016 Hisilicon Ltd. + * Copyright (C) 2016 HiSilicon Ltd. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 2172d807118143..6baf6a686450ee 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D05 Development Board * - * Copyright (C) 2016 Hisilicon Ltd. + * Copyright (C) 2016 HiSilicon Ltd. */ #include diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h index 0359bfdc911972..93064c750c8c1b 100644 --- a/include/dt-bindings/pinctrl/hisi.h +++ b/include/dt-bindings/pinctrl/hisi.h @@ -1,7 +1,7 @@ /* * This header provides constants for hisilicon pinctrl bindings. * - * Copyright (c) 2015 Hisilicon Limited. + * Copyright (c) 2015 HiSilicon Limited. * Copyright (c) 2015 Linaro Limited. * * This program is free software; you can redistribute it and/or modify From da1eab9e15ef96c10e5cadd73ebe113e7947f8f7 Mon Sep 17 00:00:00 2001 From: Hao Fang Date: Sat, 22 May 2021 18:21:57 +0800 Subject: [PATCH 478/511] ARM: dts: hisilicon: use the correct HiSilicon copyright s/Hisilicon/HiSilicon/. It should use capital S, according to the official website https://www.hisilicon.com/en. Signed-off-by: Hao Fang Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3620.dtsi | 4 ++-- arch/arm/boot/dts/hip01-ca9x2.dts | 4 ++-- arch/arm/boot/dts/hip01.dtsi | 4 ++-- arch/arm/boot/dts/hip04.dtsi | 4 ++-- arch/arm/boot/dts/hisi-x5hd2-dkb.dts | 2 +- arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +- arch/arm/boot/dts/sd5203.dts | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 905900bf3e8204..cf48ec14af434f 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. Hi3620 SoC + * HiSilicon Ltd. Hi3620 SoC * - * Copyright (C) 2012-2013 Hisilicon Ltd. + * Copyright (C) 2012-2013 HiSilicon Ltd. * Copyright (C) 2012-2013 Linaro Ltd. * * Author: Haojian Zhuang diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts index 031476304d9461..f3faf247cd6115 100644 --- a/arch/arm/boot/dts/hip01-ca9x2.dts +++ b/arch/arm/boot/dts/hip01-ca9x2.dts @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP01 SoC + * HiSilicon Ltd. HiP01 SoC * - * Copyright (C) 2014 Hisilicon Ltd. + * Copyright (C) 2014 HiSilicon Ltd. * Copyright (C) 2014 Huawei Ltd. * * Author: Wang Long diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 2a796360539002..e17f36bd9006a2 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP01 SoC + * HiSilicon Ltd. HiP01 SoC * - * Copyright (c) 2014 Hisilicon Ltd. + * Copyright (c) 2014 HiSilicon Ltd. * Copyright (c) 2014 Huawei Ltd. * * Author: Wang Long diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index bccf5ba3d8553c..2424cc545c9ce4 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP04 SoC + * HiSilicon Ltd. HiP04 SoC * - * Copyright (C) 2013-2014 Hisilicon Ltd. + * Copyright (C) 2013-2014 HiSilicon Ltd. * Copyright (C) 2013-2014 Linaro Ltd. * * Author: Haojian Zhuang diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index 22b122d3f514e4..7758c19038f0ee 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. + * Copyright (c) 2013-2014 HiSilicon Limited. */ /dts-v1/; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 97211385dc89cb..dc991ba2a9fb76 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. + * Copyright (c) 2013-2014 HiSilicon Limited. */ #include diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts index 3cc9a23910be62..a61a078ea042e6 100644 --- a/arch/arm/boot/dts/sd5203.dts +++ b/arch/arm/boot/dts/sd5203.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2020 Hisilicon Limited. + * Copyright (c) 2020 HiSilicon Limited. * * DTS file for Hisilicon SD5203 Board */ From 3a52a48973b355b3aac5add92ef50650ae37c2bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 20 May 2021 13:38:44 +0200 Subject: [PATCH 479/511] arm64: dts: marvell: armada-37xx: move firmware node to generic dtsi file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the turris-mox-rwtm firmware node from Turris MOX' device tree into the generic armada-37xx.dtsi file and use the generic compatible string 'marvell,armada-3700-rwtm-firmware' instead of the current one. Turris MOX DTS file contains also old compatible string for backward compatibility. The Turris MOX rWTM firmware can be used on any Armada 37xx device, giving them access to the rWTM hardware random number generator, which is otherwise unavailable. This change allows Linux to load the turris-mox-rwtm.ko module on these boards. Tested on ESPRESSObin v5 with both default Marvell WTMI firmware and CZ.NIC's firmware. With default WTMI firmware the turris-mox-rwtm fails to probe, while with CZ.NIC's firmware it registers the HW random number generator. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 6 ++---- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 8 ++++++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 53e817c5f6f36b..ce2bcddf396f8a 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -109,10 +109,8 @@ }; firmware { - turris-mox-rwtm { - compatible = "cznic,turris-mox-rwtm"; - mboxes = <&rwtm 0>; - status = "okay"; + armada-3700-rwtm { + compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 456dcd4a7793f5..950eac5814b13e 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -504,4 +504,12 @@ }; }; }; + + firmware { + armada-3700-rwtm { + compatible = "marvell,armada-3700-rwtm-firmware"; + mboxes = <&rwtm 0>; + status = "okay"; + }; + }; }; From f2c6d6b271e44ccc738a8966cb65ba68b56bde59 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Mon, 22 Mar 2021 01:39:15 +0100 Subject: [PATCH 480/511] arm64: dts: ensure backward compatibility of the AP807 Xenon A recent switch to a dedicated AP807 compatible string for the Xenon SD/MMC controller result in the driver not being probed when using updated device tree with the older kernel revisions. It may also be problematic for other OSs/firmware that use Linux device tree sources as a reference. Resolve the problem with backward compatibility by restoring a previous compatible string as secondary one. Signed-off-by: Marcin Wojtas Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap807.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi index d9bbbfa4b4eb21..4a23f65d475fc0 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi @@ -29,6 +29,7 @@ }; &ap_sdhci0 { - compatible = "marvell,armada-ap807-sdhci"; + compatible = "marvell,armada-ap807-sdhci", + "marvell,armada-ap806-sdhci"; /* Backward compatibility */ }; From 3a0dc9fbe2b24a620e41d62cfe852e53b55f0bd8 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Tue, 9 Feb 2021 15:46:06 +0200 Subject: [PATCH 481/511] Documentation/bindings: phy: update references to cp11x The cp11x references in dts has changed, reflect it in comphy documentation. Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Konstantin Porotchkin Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/phy/phy-mvebu-comphy.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt index 8c60e69859505b..5ffd0f55d0102c 100644 --- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt @@ -42,22 +42,22 @@ Required properties (child nodes): Examples: - cpm_comphy: phy@120000 { + CP11X_LABEL(comphy): phy@120000 { compatible = "marvell,comphy-cp110"; reg = <0x120000 0x6000>; - marvell,system-controller = <&cpm_syscon0>; - clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, - <&CP110_LABEL(clk) 1 18>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, + <&CP11X_LABEL(clk) 1 18>; clock-names = "mg_clk", "mg_core_clk", "axi_clk"; #address-cells = <1>; #size-cells = <0>; - cpm_comphy0: phy@0 { + CP11X_LABEL(comphy0): phy@0 { reg = <0>; #phy-cells = <1>; }; - cpm_comphy1: phy@1 { + CP11X_LABEL(comphy1): phy@1 { reg = <1>; #phy-cells = <1>; }; From e3850467bf8c82de4a052619136839fe8054b774 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Tue, 9 Feb 2021 15:46:07 +0200 Subject: [PATCH 482/511] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme Eliminate 1MB gap between Linux and filesystem partitions. Signed-off-by: Konstantin Porotchkin Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-db.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts index 2c2af001619b0e..9758609541c7bc 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dts +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts @@ -260,7 +260,7 @@ }; partition@200000 { label = "Linux"; - reg = <0x200000 0xd00000>; + reg = <0x200000 0xe00000>; }; partition@1000000 { label = "Filesystem"; From f515dcce2d1860c622e982f501d080c7f2fee27e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 18:15:36 +0200 Subject: [PATCH 483/511] arm64: dts: qcom: sm8250-edo: Fix up double "pinctrl-1" When bringing the SDC pins back to edo.dtsi I managed to define and overwrite pinctrl-1 instead of defining pinctrl-0 and 1. Fix it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616161536.206044-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 0db63eb08c60df..bbc9b380b166fa 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -453,7 +453,7 @@ cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; - pinctrl-1 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; vmmc-supply = <&vreg_l9c_2p9>; vqmmc-supply = <&vreg_l6c_2p9>; From a4f221cd68b306d6311237e47b531d21fab8dfa4 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 15 Jun 2021 14:57:16 -0500 Subject: [PATCH 484/511] arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes The AM64x SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. Both the R5F clusters are present within the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a new "Single-CPU" mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. The mode is restricted to "Single-CPU" on some devices with the appropriate eFuse bit set, but the most common devices support both modes. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in Single-CPU mode to provide a larger 128 KB of memory. The other notable difference is that the TCMs are spaced 1 MB apart on these SoCs unlike the existing SoCs. Add the DT nodes for both these MAIN domain R5F cluster/subsystems, the two R5F cores are added as child nodes to each of the corresponding R5F cluster node. Both the clusters are configured to run in Split mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: MAIN R5FSS0 Core0: am64-main-r5f0_0-fw (both in Single-CPU & Split modes) MAIN R5FSS0 Core1: am64-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: am64-main-r5f1_0-fw (both in Single-CPU & Split modes) MAIN R5FSS1 Core1: am64-main-r5f1_1-fw (needed only in Split mode) NOTE: A R5FSS cluster can be configured in "Single-CPU" mode by using a value of 2 for the "ti,cluster-mode" property. Value of 1 is not permitted (fails the dtbs_check). Signed-off-by: Suman Anna Reviewed-by: Praneeth Bajjuri Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210615195718.15898-2-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 62d2b8fff67dff..02c3fdf9cc46ba 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -694,6 +694,90 @@ ti,mbox-num-fifos = <16>; }; + main_r5fss0: r5fss@78000000 { + compatible = "ti,am64-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x10000>, + <0x78100000 0x00 0x78100000 0x10000>, + <0x78200000 0x00 0x78200000 0x08000>, + <0x78300000 0x00 0x78300000 0x08000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@78000000 { + compatible = "ti,am64-r5f"; + reg = <0x78000000 0x00010000>, + <0x78100000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am64-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@78200000 { + compatible = "ti,am64-r5f"; + reg = <0x78200000 0x00008000>, + <0x78300000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <122>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 122 1>; + firmware-name = "am64-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@78400000 { + compatible = "ti,am64-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78400000 0x00 0x78400000 0x10000>, + <0x78500000 0x00 0x78500000 0x10000>, + <0x78600000 0x00 0x78600000 0x08000>, + <0x78700000 0x00 0x78700000 0x08000>; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@78400000 { + compatible = "ti,am64-r5f"; + reg = <0x78400000 0x00010000>, + <0x78500000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <123>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 123 1>; + firmware-name = "am64-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@78600000 { + compatible = "ti,am64-r5f"; + reg = <0x78600000 0x00008000>, + <0x78700000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <124>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 124 1>; + firmware-name = "am64-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + serdes_wiz0: wiz@f000000 { compatible = "ti,am64-wiz-10g"; #address-cells = <1>; From 0afadba435892c8d330e3238b9cc7f9ee8b20e90 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 15 Jun 2021 14:57:17 -0500 Subject: [PATCH 485/511] arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs Add the required 'mboxes' property to all the R5F processors for the TI AM642 EVM and SK boards. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the R5Fs. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Note that any R5F Core1 resources are needed and used only when that R5F cluster is configured for Split-mode. Signed-off-by: Suman Anna Reviewed-by: Praneeth Bajjuri Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210615195718.15898-3-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 16 ++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index dc69db2d10c347..2e75cd68f8b75e 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -469,6 +469,22 @@ status = "disabled"; }; +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; +}; + &serdes_ln_ctrl { idle-states = ; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 40124007259d2f..4abddea92cf598 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -368,6 +368,22 @@ status = "disabled"; }; +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; +}; + &pcie0_rc { status = "disabled"; }; From d71abfcc6c050b72ba735b74f3e3848ce07ddd15 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 15 Jun 2021 14:57:18 -0500 Subject: [PATCH 486/511] arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs Two carveout reserved memory nodes each have been added for each of the R5F remote processor devices within the MAIN domain on the TI AM642 EVM and SK boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc devices, and the second region will furnish the static carveout regions for the firmware memory. An additional reserved memory node is also added to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the remote processors running RTOS or baremetal firmwares. 8 MB of memory is reserved for this purpose, and this accounts for all the vrings and vring buffers between all the possible pairs of remote processors. The current carveout addresses and sizes are defined statically for each rproc device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables to allocate the memory for firmware memory segments. NOTE: 1. The R5F1 carveouts are needed only if the R5F cluster is running in Split (non Single-CPU) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. 2. The AM64x SoCs do not have any DSPs and one less R5F cluster compared to J721E SoCs. So, while the carveout memories reserved for the R5F clusters present on the SoC match to those on J721E, the overall memory map reserved for firmwares is quite different. The number of R5F clusters on AM64x SoCs are same as on J7200 SoCs, but the AM64x SoCs also have an additional M4F core, so the RTOS IPC memory region is 1 MB higher than on J7200 SoCs. Signed-off-by: Suman Anna Reviewed-by: Praneeth Bajjuri Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20210615195718.15898-4-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 62 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 62 +++++++++++++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 2e75cd68f8b75e..0307122211889c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -38,6 +38,60 @@ alignment = <0x1000>; no-map; }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; evm_12v0: fixedregulator-evm12v0 { @@ -471,18 +525,26 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; }; &serdes_ln_ctrl { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 4abddea92cf598..d3aa2901e6fdae 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -37,6 +37,60 @@ alignment = <0x1000>; no-map; }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; vusb_main: fixed-regulator-vusb-main5v0 { @@ -370,18 +424,26 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; }; &pcie0_rc { From 10489ef12feddd7e663851fc45aeb65855dcf2a8 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 17 Jun 2021 11:15:46 +0530 Subject: [PATCH 487/511] arm64: dts: qcom: pmm8155au_1: Add base dts file Add base DTS file for pmm8155au_1 along with GPIOs, power-on, rtc and vadc nodes. Cc: Mark Brown Cc: Vinod Koul Reviewed-by: Bjorn Andersson Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210617054548.353293-4-bhupesh.sharma@linaro.org [bjorn: Added gpio-ranges to pmm8155au_1_gpios] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 135 ++++++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi new file mode 100644 index 00000000000000..7072e5a2e73f5e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include +#include + +/ { + thermal-zones { + pmm8155au-1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmm8155au_1_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@0 { + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon: power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + + status = "disabled"; + }; + }; + + pmm8155au_1_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmm8155au_1_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmm8155au_1_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmm8155au_1_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmm8155au_1_rtc: rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + + status = "disabled"; + }; + + pmm8155au_1_gpios: gpio@c000 { + compatible = "qcom,pmm8155au-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm8155au_1_gpios 0 0 10>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; From b557471bb286b5df7eda477041d58b12d4b44219 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 17 Jun 2021 11:15:47 +0530 Subject: [PATCH 488/511] arm64: dts: qcom: pmm8155au_2: Add base dts file Add base DTS file for pmm8155au_2 along with GPIOs, power-on, rtc and vadc nodes. Cc: Mark Brown Cc: Vinod Koul Reviewed-by: Bjorn Andersson Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210617054548.353293-5-bhupesh.sharma@linaro.org [bjorn: Added gpio-ranges to pmm8155au_2_gpios] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi | 108 ++++++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi new file mode 100644 index 00000000000000..72075964fbb910 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include + +/ { + thermal-zones { + pmm8155au-2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmm8155au_2_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@4 { + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + + status = "disabled"; + }; + + pmm8155au_2_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmm8155au_2_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmm8155au_2_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmm8155au_2_gpios: gpio@c000 { + compatible = "qcom,pmm8155au-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm8155au_2_gpios 0 0 10>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@5 { + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; From 5b85e8f2225c21b68eb93c1c9e071fc3f989de1d Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 17 Jun 2021 11:15:48 +0530 Subject: [PATCH 489/511] arm64: dts: qcom: sa8155p-adp: Add base dts file Add base DTS file for SA8155p Automotive Development Platform. It enables boot to console, adds tlmm reserved range and ufs flash. It also includes pmic file. SA8155p-adp board is based on sa8155p Qualcomm Snapdragon SoC. SA8155p platform is similar to the SM8150, so use this as base for now. Cc: Vinod Koul Reviewed-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20210617054548.353293-6-bhupesh.sharma@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 360 +++++++++++++++++++++++ 2 files changed, 361 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8155p-adp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 9ea7f50364acf3..4f05970919763c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts new file mode 100644 index 00000000000000..0da7a3b8d1bf31 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include "sm8150.dtsi" +#include "pmm8155au_1.dtsi" +#include "pmm8155au_2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P ADP"; + compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vreg_3p3: vreg_3p3_regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* + * S4A is always on and not controllable through RPMh. + * So model it as a fixed regulator. + */ + vreg_s4a_1p8: smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + + vin-supply = <&vreg_3p3>; + }; +}; + +&apps_rsc { + pmm8155au-1-rpmh-regulators { + compatible = "qcom,pmm8155au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vreg_3p3>; + vdd-s2-supply = <&vreg_3p3>; + vdd-s3-supply = <&vreg_3p3>; + vdd-s4-supply = <&vreg_3p3>; + vdd-s5-supply = <&vreg_3p3>; + vdd-s6-supply = <&vreg_3p3>; + vdd-s7-supply = <&vreg_3p3>; + vdd-s8-supply = <&vreg_3p3>; + vdd-s9-supply = <&vreg_3p3>; + vdd-s10-supply = <&vreg_3p3>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; + vdd-l2-l10-supply = <&vreg_3p3>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; + vdd-l6-l9-supply = <&vreg_s6a_0p92>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l13-l16-l17-supply = <&vreg_3p3>; + + vreg_s5a_2p04: smps5 { + regulator-name = "vreg_s5a_2p04"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p92: smps6 { + regulator-name = "vreg_s6a_0p92"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_l1a_0p752: ldo1 { + regulator-name = "vreg_l1a_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vdda_usb_hs_3p1: + vreg_l2a_3p072: ldo2 { + regulator-name = "vreg_l2a_3p072"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p8: ldo3 { + regulator-name = "vreg_l3a_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vdd_usb_hs_core: + vdda_usb_ss_dp_core_1: + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10a_2p96: ldo10 { + regulator-name = "vreg_l10a_2p96"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + vreg_l11a_0p8: ldo11 { + regulator-name = "vreg_l11a_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vdda_usb_hs_1p8: + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_2p7: ldo13 { + regulator-name = "vreg_l13a_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p7: ldo15 { + regulator-name = "vreg_l15a_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l17a_2p96: ldo17 { + regulator-name = "vreg_l17a_2p96"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + pmm8155au-2-rpmh-regulators { + compatible = "qcom,pmm8155au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vreg_3p3>; + vdd-s2-supply = <&vreg_3p3>; + vdd-s3-supply = <&vreg_3p3>; + vdd-s4-supply = <&vreg_3p3>; + vdd-s5-supply = <&vreg_3p3>; + vdd-s6-supply = <&vreg_3p3>; + vdd-s7-supply = <&vreg_3p3>; + vdd-s8-supply = <&vreg_3p3>; + vdd-s9-supply = <&vreg_3p3>; + vdd-s10-supply = <&vreg_3p3>; + + vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; + vdd-l2-l10-supply = <&vreg_3p3>; + vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; + vdd-l6-l9-supply = <&vreg_s6c_1p128>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; + vdd-l13-l16-l17-supply = <&vreg_3p3>; + + vreg_s4c_1p352: smps4 { + regulator-name = "vreg_s4c_1p352"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5c_2p04: smps5 { + regulator-name = "vreg_s5c_2p04"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6c_1p128: smps6 { + regulator-name = "vreg_s6c_1p128"; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_l1c_1p304: ldo1 { + regulator-name = "vreg_l1c_1p304"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p808: ldo2 { + regulator-name = "vreg_l2c_1p808"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p2: ldo5 { + regulator-name = "vreg_l5c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + vreg_l7c_1p8: ldo7 { + regulator-name = "vreg_l7c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p2: ldo8 { + regulator-name = "vreg_l8c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + vreg_l10c_3p3: ldo10 { + regulator-name = "vreg_l10c_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_0p8: ldo11 { + regulator-name = "vreg_l11c_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p808: ldo12 { + regulator-name = "vreg_l12c_1p808"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l13c_2p96: ldo13 { + regulator-name = "vreg_l13c_2p96"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l15c_1p9: ldo15 { + regulator-name = "vreg_l15c_1p9"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l16c_3p008: ldo16 { + regulator-name = "vreg_l16c_3p008"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l18c_0p88: ldo18 { + regulator-name = "vreg_l18c_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10a_2p96>; + vcc-max-microamp = <750000>; + vccq-supply = <&vreg_l5c_1p2>; + vccq-max-microamp = <700000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <750000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l8c_1p2>; + vdda-max-microamp = <87100>; + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda-pll-max-microamp = <18300>; +}; + + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l8c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; From 46e14907c71628ea82daea8911b9f449f478f9b4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 14:27:03 +0200 Subject: [PATCH 490/511] arm64: dts: qcom: sm8250-edo: Add hardware keys Volume Down, GAssist (pdx206 only) and camera keys live on PMIC pins, with the latter kind being broken for now.. Add these and PON-connected Volume Up & PWR. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616122708.144770-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../qcom/sm8250-sony-xperia-edo-pdx206.dts | 11 +++++++ .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 30 +++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts index 999b662f46799a..16c96e8385348f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -18,6 +18,17 @@ stride = <(1080 * 4)>; }; +&gpio_keys { + g-assist-key { + label = "Google Assistant Key"; + linux,code = ; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; +}; + &vreg_l2f_1p3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index bbc9b380b166fa..1a08712b88df41 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -47,6 +47,26 @@ }; }; + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + /* + * Camera focus (light press) and camera snapshot (full press) + * seem not to work properly.. Adding the former one stalls the CPU + * and the latter kills the volume down key for whatever reason. In any + * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1). + */ + + vol-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -436,6 +456,16 @@ /* Richwave RTC6226 FM Radio Receiver @ 64 */ }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; +}; + &qupv3_id_0 { status = "okay"; }; From 13e948a36db782a57a92570bbd60702587624727 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 14:27:04 +0200 Subject: [PATCH 491/511] arm64: dts: qcom: sm8250: Commonize PCIe pins Commonize PCIe pins, as the configuration is SoC-common and doesn't change (or at least doesn't change much) between boards. While at it, remove "output-low" from the RB5 board, as it's not necessary - we already explicitly pull the perst pin low. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616122708.144770-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 87 ------------------------ arch/arm64/boot/dts/qcom/sm8250.dtsi | 87 ++++++++++++++++++++++++ 2 files changed, 87 insertions(+), 87 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index d5a4f5a27da68b..8ac96f8e79d42b 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -669,10 +669,6 @@ &pcie0 { status = "okay"; - perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; }; &pcie0_phy { @@ -683,10 +679,6 @@ &pcie1 { status = "okay"; - perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; }; &pcie1_phy { @@ -697,10 +689,6 @@ &pcie2 { status = "okay"; - perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_default_state>; }; &pcie2_phy { @@ -1178,81 +1166,6 @@ bias-disable; }; - pcie0_default_state: pcie0-default { - clkreq { - pins = "gpio80"; - function = "pci_e0"; - bias-pull-up; - }; - - reset-n { - pins = "gpio79"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio81"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default { - clkreq { - pins = "gpio83"; - function = "pci_e1"; - bias-pull-up; - }; - - reset-n { - pins = "gpio82"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio84"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie2_default_state: pcie2-default { - clkreq { - pins = "gpio86"; - function = "pci_e2"; - bias-pull-up; - }; - - reset-n { - pins = "gpio85"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio87"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - sdc2_default_state: sdc2-default { clk { pins = "sdc2_clk"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index b8d76b37928bbc..4798368b02efb9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1314,6 +1314,12 @@ phys = <&pcie0_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + status = "disabled"; }; @@ -1412,6 +1418,12 @@ phys = <&pcie1_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + status = "disabled"; }; @@ -1512,6 +1524,12 @@ phys = <&pcie2_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_default_state>; + status = "disabled"; }; @@ -3490,6 +3508,75 @@ bias-pull-up; }; }; + + pcie0_default_state: pcie0-default { + perst { + pins = "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio80"; + function = "pci_e0"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio81"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + perst { + pins = "gpio82"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio83"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio84"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_default_state: pcie2-default { + perst { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio86"; + function = "pci_e2"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { From db92d8cdde33a862fe43b0b7d5a802ad24bfa8b9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 14:27:05 +0200 Subject: [PATCH 492/511] arm64: dts: qcom: sm8250-edo: Enable PCIe Enable PCIe0 (Wi-Fi) and 2 (SDX55m) interfaces and PHYs and assign relevant pins and regulators. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616122708.144770-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 1a08712b88df41..36ff9998a4c6a0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -456,6 +456,30 @@ /* Richwave RTC6226 FM Radio Receiver @ 64 */ }; +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; +}; + +&pcie2 { + status = "okay"; + + pinctrl-0 = <&pcie2_default_state &mdm2ap_default &ap2mdm_default>; +}; + +&pcie2_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; +}; + &pon_pwrkey { status = "okay"; }; @@ -515,6 +539,20 @@ }; }; + mdm2ap_default: mdm2ap-default { + pins = "gpio1", "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + ap2mdm_default: ap2mdm-default { + pins = "gpio56", "gpio57"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + sdc2_card_det_n: sd-card-det-n { pins = "gpio77"; function = "gpio"; From f0cedfc398813aa404a235d5684676056eeb160d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 14:27:06 +0200 Subject: [PATCH 493/511] arm64: dts: qcom: sm8250-edo: Enable ADSP/CDSP/SLPI Enabling the hardware thankfully comes down to a simple status = "okay". We assume that the firmware is provided by the Linux distribution, as it's signed and needs to come from the stock Android. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616122708.144770-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 36ff9998a4c6a0..98e5f971ee0f75 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -118,6 +118,10 @@ }; }; +&adsp { + status = "okay"; +}; + &apps_rsc { pm8150-rpmh-regulators { compatible = "qcom,pm8150-rpmh-regulators"; @@ -410,6 +414,10 @@ }; }; +&cdsp { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -516,6 +524,10 @@ no-emmc; }; +&slpi { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <40 4>, <52 4>; From 4a62a824282e245e6429c0f40c66931430d2fce5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 14:27:07 +0200 Subject: [PATCH 494/511] arm64: dts: qcom: sm8250-edo: Enable GPI DMA Enable GPI DMA for Edo devices. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616122708.144770-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 98e5f971ee0f75..a789e991b49c4a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -418,6 +418,18 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; From e76c7e1f15fe48996ca3ecfd6f2a21a67d07f9b7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jun 2021 14:27:08 +0200 Subject: [PATCH 495/511] arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen Add Samsung touchscreen node and relevant pin configuration to make the phones actually interactable with. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210616122708.144770-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index a789e991b49c4a..d63f7a9bc4e9ac 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -462,7 +462,18 @@ status = "okay"; clock-frequency = <400000>; - /* Samsung touchscreen @ 48 */ + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <39 0x2008>; + /* It's "vddio" downstream but it works anyway! */ + vdd-supply = <&vreg_l1c_1p8>; + avdd-supply = <&vreg_l10c_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + }; }; &i2c15 { @@ -570,6 +581,14 @@ bias-disable; }; + ts_int_default: ts-int-default { + pins = "gpio39"; + function = "gpio"; + drive-strength = <2>; + bias-disabled; + input-enable; + }; + ap2mdm_default: ap2mdm-default { pins = "gpio56", "gpio57"; function = "gpio"; From 77b7cfd0dc6842d7babe8def776e92b135db7faf Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Wed, 16 Jun 2021 14:52:24 +0530 Subject: [PATCH 496/511] arm64: dts: qcom: sc7180: bus votes for eMMC and SD card Update peak bandwidth and average bandwidth vote values for eMMC and SDCard. This patch calculates the new votes as per the comments from https://lore.kernel.org/patchwork/patch/1399453/#1619566. Signed-off-by: Shaik Sajida Bhanu Link: https://lore.kernel.org/r/1623835344-29607-1-git-send-email-sbhanu@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index fb1d9ad8bf6c8d..a5d58eb928960b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -727,15 +727,15 @@ opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <100000 100000>; - opp-avg-kBps = <100000 50000>; + opp-peak-kBps = <1800000 600000>; + opp-avg-kBps = <100000 0>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - opp-peak-kBps = <600000 900000>; - opp-avg-kBps = <261438 300000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <390000 0>; }; }; }; @@ -2585,15 +2585,15 @@ opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <160000 100000>; - opp-avg-kBps = <80000 50000>; + opp-peak-kBps = <1800000 600000>; + opp-avg-kBps = <100000 0>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - opp-peak-kBps = <200000 120000>; - opp-avg-kBps = <100000 60000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <200000 0>; }; }; }; From edb39de5d731f147c7b08c4a5eb246ae1dbdd947 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 14 Jun 2021 11:18:49 -0500 Subject: [PATCH 497/511] arm64: dts: rockchip: Add Rotation Property for OGA Panel Add rotation property for Odroid Go Advance panel to note that it is rotated 270 degrees. Rotation affects DRM connector after this patch: https://cgit.freedesktop.org/drm/drm/commit/drivers/gpu/drm/panel/panel-elida-kd35t133.c?id=610d9c311b1387f8c4ac602fee1f2a1cb0508707 Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20210614161849.332-1-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index 017c1a76d9aae0..7fc674a99a6ca9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -264,6 +264,7 @@ backlight = <&backlight>; iovcc-supply = <&vcc_lcd>; reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + rotation = <270>; vdd-supply = <&vcc_lcd>; port { From ba2401ab87bc2049a49d45f75013f6faebd120f1 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 13 Jun 2021 22:52:34 +0100 Subject: [PATCH 498/511] arm64: dts: rockchip: add SPDIF node for rk3399-firefly This patch adds the SPDIF sound node and related settings for rk3399-firefly. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20210613215237.830160-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-firefly.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index 45254be1350dec..6bbf79a370df27 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -151,6 +151,23 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + sound-dit { + compatible = "audio-graph-card"; + label = "SPDIF"; + dais = <&spdif_p0>; + }; + + spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port { + dit_p0_0: endpoint { + remote-endpoint = <&spdif_p0_0>; + }; + }; + }; + /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -710,6 +727,17 @@ status = "okay"; }; +&spdif { + pinctrl-0 = <&spdif_bus_1>; + status = "okay"; + + spdif_p0: port { + spdif_p0_0: endpoint { + remote-endpoint = <&dit_p0_0>; + }; + }; +}; + &tcphy0 { status = "okay"; }; From 4fab8e3655e476170281884d999c4d758d405fac Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 13 Jun 2021 22:52:35 +0100 Subject: [PATCH 499/511] arm64: dts: rockchip: add infrared receiver node to RK3399 Firefly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the RK3399 Firefly’s infrared receiver to its dts. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20210613215237.830160-2-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index 6bbf79a370df27..ca85890824e43f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -94,6 +94,13 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -595,6 +602,12 @@ }; }; + ir { + ir_int: ir-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd-panel { lcd_panel_reset: lcd-panel-reset { rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; From 5768c5ff0709aeea40fbdc8e362733f5a99fc458 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 13 Jun 2021 22:52:36 +0100 Subject: [PATCH 500/511] arm64: dts: rockchip: Sort rk3399 firefly pinmux entries Sort the rk3399 firefly pinmux entries in alphabetical order and de-dupe the pmic entries. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20210613215237.830160-3-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-firefly.dts | 36 +++++++++---------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index ca85890824e43f..e6e91162d06927 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -614,6 +614,16 @@ }; }; + leds { + work_led_pin: work-led-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_pin: diy-led-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; @@ -625,6 +635,10 @@ }; pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; }; @@ -634,21 +648,15 @@ }; }; - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - rt5640 { rt5640_hpcon: rt5640-hpcon { rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -663,16 +671,6 @@ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - leds { - work_led_pin: work-led-pin { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_pin: diy-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; }; &pwm0 { From a406bfda89c78a75327f8b6a0281b5d3bed493a1 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 13 Jun 2021 22:52:37 +0100 Subject: [PATCH 501/511] arm64: dts: rockchip: Add USB-C port details for rk3399 Firefly Add the initial details for the USB-C port. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20210613215237.830160-4-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-firefly.dts | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index e6e91162d06927..c4dd2a6b483683 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -6,6 +6,7 @@ /dts-v1/; #include #include +#include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -220,6 +221,17 @@ vin-supply = <&vcc_sys>; }; + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -545,6 +557,53 @@ i2c-scl-falling-time-ns = <20>; status = "okay"; + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + data-role = "host"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc_hs: endpoint { + remote-endpoint = + <&u2phy0_typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usbc_ss: endpoint { + remote-endpoint = + <&tcphy0_typec_ss>; + }; + }; + }; + }; + }; + accelerometer@68 { compatible = "invensense,mpu6500"; reg = <0x68>; @@ -602,6 +661,12 @@ }; }; + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + ir { ir_int: ir-int { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; @@ -660,6 +725,12 @@ }; }; + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + usb2 { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -753,6 +824,14 @@ status = "okay"; }; +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&usbc_ss>; + }; + }; +}; + &tcphy1 { status = "okay"; }; @@ -776,6 +855,12 @@ phy-supply = <&vcc5v0_host>; status = "okay"; }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&usbc_hs>; + }; + }; }; &u2phy1 { From e1d635bc94bce69e45a2d4e93c94178613e01229 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 19 Jun 2021 14:16:42 +0200 Subject: [PATCH 502/511] arm64: dts: rockchip: add ir-receiver for rk3399-roc-pc Like some other RK3399 boards RK3399-ROC-PC has an ir receiver connected to pwm3 which can be used as gpio-ir-receiver. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210619121642.7892-1-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index c172f5a803e7b1..ac441fd5f9814c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -63,6 +63,13 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -601,6 +608,12 @@ }; }; + ir { + ir_int: ir-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd-panel { lcd_panel_reset: lcd-panel-reset { rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; From 06b2818678d9b35102c9816ffaf6893caf306ed0 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 19 Jun 2021 14:14:46 +0200 Subject: [PATCH 503/511] arm64: dts: rockchip: Re-add regulator-boot-on, regulator-always-on for vdd_gpu on rk3399-roc-pc This might be a limitation of either the current panfrost driver devfreq implementation or how the gpu is implemented in RK3399 SoC. The gpu regulator must never get disabled or the registers get (randomly?) inaccessable by the driver. (see all other RK3399 boards) Fixes: ec7d731d81e7 ("arm64: dts: rockchip: Add node for gpu on rk3399-roc-pc") Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210619121446.7802-1-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index ac441fd5f9814c..353089000deec9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -500,6 +500,8 @@ regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc3v3_sys>; regulator-state-mem { From eb607cd4957fb0ef97beb2a8293478be6a54240a Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 19 Jun 2021 14:13:06 +0200 Subject: [PATCH 504/511] arm64: dts: rockchip: Re-add regulator-always-on for vcc_sdio for rk3399-roc-pc Re-add the regulator-always-on property for vcc_sdio which supplies sdmmc, since it gets disabled during reboot now and the bootrom expects it to be enabled when booting from SD card. This makes rebooting impossible in that case and requires a hard reset to boot again. Fixes: 04a0077fdb19 ("arm64: dts: rockchip: Remove always-on properties from regulator nodes on rk3399-roc-pc.") Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210619121306.7740-1-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index 353089000deec9..d1aaf8e83391ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -396,6 +396,7 @@ vcc_sdio: LDO_REG4 { regulator-name = "vcc_sdio"; + regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; From abe66bb7a2f6e308f2fb059d60b1076df84306ad Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sat, 19 Jun 2021 18:27:51 +0200 Subject: [PATCH 505/511] arm64: dts: ipq8074: Add QUP6 I2C node Add node to support the QUP6 I2C controller inside of IPQ8074. It is exactly the same as QUP2 and QUP3 controllers. Some routers like Xiaomi AX9000 and Netgear RBK850 use this bus. Signed-off-by: Robert Marko Link: https://lore.kernel.org/r/20210619162751.2336974-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 7542d1eee62cd9..95d6cb8cd4c0c1 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -373,6 +373,21 @@ status = "disabled"; }; + blsp1_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x078ba000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <100000>; + dmas = <&blsp_dma 23>, <&blsp_dma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07984000 0x1a000>; From 9d34d4aa896d00d398d799caa839a1494ba7c018 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 27 May 2021 17:44:53 +0200 Subject: [PATCH 506/511] ARM: dts: rockchip: add vpu node for RK3036 Add the vpu node and the node for the attached iommu for RK3036. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210527154455.358869-11-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 33019d2a22332a..ffa9bc7ed3d04e 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -117,6 +117,27 @@ status = "disabled"; }; + vpu: video-codec@10108000 { + compatible = "rockchip,rk3036-vpu"; + reg = <0x10108000 0x800>; + interrupts = ; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3036_PD_VPU>; + }; + + vpu_mmu: iommu@10108800 { + compatible = "rockchip,iommu"; + reg = <0x10108800 0x100>; + interrupts = ; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3036_PD_VPU>; + #iommu-cells = <0>; + }; + vop: vop@10118000 { compatible = "rockchip,rk3036-vop"; reg = <0x10118000 0x19c>; From db3fc8fa0fcfa481cd8087c2ee068d1d1988c3a2 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 27 May 2021 17:44:54 +0200 Subject: [PATCH 507/511] ARM: dts: rockchip: add vpu nodes for RK3066 and RK3188 Add the vpu node to the common rk3xxx.dtsi and only the powerdomain property to the SoC specific device trees. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210527154455.358869-12-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 4 ++++ arch/arm/boot/dts/rk3188.dtsi | 5 +++++ arch/arm/boot/dts/rk3xxx.dtsi | 12 ++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index b15cbbe23ffc57..f5a665b5d209ff 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -868,6 +868,10 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + power-domains = <&power RK3066_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index b36fcdd9a51602..793a1b9117fea5 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -801,6 +801,11 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; + power-domains = <&power RK3188_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index f9bbc242444486..616a828e0c6e4c 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -47,6 +47,18 @@ status = "disabled"; }; + vpu: video-codec@10104000 { + compatible = "rockchip,rk3066-vpu"; + reg = <0x10104000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk_vdpu", "hclk_vdpu", + "aclk_vepu", "hclk_vepu"; + }; + L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; From 36e9534dfcb5b09b919d2831d6a19aa3856b95a1 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 27 May 2021 17:44:55 +0200 Subject: [PATCH 508/511] ARM: dts: rockchip: add vpu and vdec node for RK322x The VPU and the VDEC IP block of RK322x are the same as RK3399 has and the drivers can be used as-is. Add the respective nodes to the device tree. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20210527154455.358869-13-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index ea8ceeb09c0b3e..75af99c76d7ea2 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -610,6 +610,18 @@ status = "disabled"; }; + vpu: video-codec@20020000 { + compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; + reg = <0x20020000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3228_PD_VPU>; + }; + vpu_mmu: iommu@20020800 { compatible = "rockchip,iommu"; reg = <0x20020800 0x100>; @@ -618,7 +630,19 @@ clock-names = "aclk", "iface"; power-domains = <&power RK3228_PD_VPU>; #iommu-cells = <0>; - status = "disabled"; + }; + + vdec: video-codec@20030000 { + compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; + reg = <0x20030000 0x480>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <300000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3228_PD_RKVDEC>; }; vdec_mmu: iommu@20030480 { @@ -629,7 +653,6 @@ clock-names = "aclk", "iface"; power-domains = <&power RK3228_PD_RKVDEC>; #iommu-cells = <0>; - status = "disabled"; }; vop: vop@20050000 { From ef0bff8ba8dfa53780fca0fd5c369f9c78fc30cf Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 22 Jun 2021 10:05:15 +0800 Subject: [PATCH 509/511] arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs The pinconfig settings for Rockchip SoCs are pretty similar on all socs, so move them to a shared dtsi to be included, instead of redefining them for each soc. Signed-off-by: Liang Chen Link: https://lore.kernel.org/r/20210622020517.13100-3-cl@rock-chips.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rockchip-pinconf.dtsi | 344 ++++++++++++++++++ 1 file changed, 344 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi new file mode 100644 index 00000000000000..5c645437b50723 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; +}; From a3adc0b9071d880dcceb78b5e921843502f272bd Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 22 Jun 2021 10:05:16 +0800 Subject: [PATCH 510/511] arm64: dts: rockchip: add core dtsi for RK3568 SoC RK3568 is a high-performance and low power quad-core application processor designed for personal mobile internet device and AIoT equipment. This patch add basic core dtsi file for it. We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will enalbe a special high-performance PLL when high frequency is required. The smci_clk code is in ATF, and clkid for cpu is 0, as below: cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; clocks = <&scmi_clk 0>; }; Signed-off-by: Liang Chen Link: https://lore.kernel.org/r/20210622020517.13100-4-cl@rock-chips.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3111 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 593 ++++ 2 files changed, 3704 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi new file mode 100644 index 00000000000000..a588ca95ace2cf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi @@ -0,0 +1,3111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + acodec { + /omit-if-no-ref/ + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_sync */ + <1 RK_PB1 5 &pcfg_pull_none>, + /* acodec_adcclk */ + <1 RK_PA1 5 &pcfg_pull_none>, + /* acodec_adcdata */ + <1 RK_PA0 5 &pcfg_pull_none>, + /* acodec_dac_datal */ + <1 RK_PA7 5 &pcfg_pull_none>, + /* acodec_dac_datar */ + <1 RK_PB0 5 &pcfg_pull_none>, + /* acodec_dacclk */ + <1 RK_PA3 5 &pcfg_pull_none>, + /* acodec_dacsync */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + audiopwm { + /omit-if-no-ref/ + audiopwm_lout: audiopwm-lout { + rockchip,pins = + /* audiopwm_lout */ + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutn: audiopwm-loutn { + rockchip,pins = + /* audiopwm_loutn */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutp: audiopwm-loutp { + rockchip,pins = + /* audiopwm_loutp */ + <1 RK_PA0 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_rout: audiopwm-rout { + rockchip,pins = + /* audiopwm_rout */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routn: audiopwm-routn { + rockchip,pins = + /* audiopwm_routn */ + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routp: audiopwm-routp { + rockchip,pins = + /* audiopwm_routp */ + <1 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + bt656 { + /omit-if-no-ref/ + bt656m0_pins: bt656m0-pins { + rockchip,pins = + /* bt656_clkm0 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* bt656_d0m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* bt656_d1m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* bt656_d2m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* bt656_d3m0 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* bt656_d4m0 */ + <2 RK_PD4 2 &pcfg_pull_none>, + /* bt656_d5m0 */ + <2 RK_PD5 2 &pcfg_pull_none>, + /* bt656_d6m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* bt656_d7m0 */ + <2 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656m1_pins: bt656m1-pins { + rockchip,pins = + /* bt656_clkm1 */ + <4 RK_PB4 5 &pcfg_pull_none>, + /* bt656_d0m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* bt656_d1m1 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* bt656_d2m1 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* bt656_d3m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* bt656_d4m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* bt656_d5m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* bt656_d6m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* bt656_d7m1 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clk */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <3 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + cam { + /omit-if-no-ref/ + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clkout1: cam-clkout1 { + rockchip,pins = + /* cam_clkout1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxm0 */ + <0 RK_PB4 2 &pcfg_pull_none>, + /* can0_txm0 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxm1 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can0_txm1 */ + <2 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxm0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* can1_txm0 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxm1 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* can1_txm1 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rxm0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* can2_txm0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rxm1 */ + <2 RK_PB1 4 &pcfg_pull_none>, + /* can2_txm1 */ + <2 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PC1 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* cif_d10 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d11 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d12 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d13 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d14 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d15 */ + <4 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d5 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* cif_d6 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* cif_d7 */ + <3 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + ebc { + /omit-if-no-ref/ + ebc_extern: ebc-extern { + rockchip,pins = + /* ebc_sdce1 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* ebc_sdce2 */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* ebc_sdce3 */ + <4 RK_PB1 2 &pcfg_pull_none>, + /* ebc_sdshr */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* ebc_vcom */ + <4 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ebc_pins: ebc-pins { + rockchip,pins = + /* ebc_gdclk */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* ebc_gdoe */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* ebc_gdsp */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* ebc_sdce0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* ebc_sdclk */ + <4 RK_PC1 2 &pcfg_pull_none>, + /* ebc_sddo0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* ebc_sddo1 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* ebc_sddo2 */ + <3 RK_PD0 2 &pcfg_pull_none>, + /* ebc_sddo3 */ + <3 RK_PD1 2 &pcfg_pull_none>, + /* ebc_sddo4 */ + <3 RK_PD2 2 &pcfg_pull_none>, + /* ebc_sddo5 */ + <3 RK_PD3 2 &pcfg_pull_none>, + /* ebc_sddo6 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* ebc_sddo7 */ + <3 RK_PD5 2 &pcfg_pull_none>, + /* ebc_sddo8 */ + <3 RK_PD6 2 &pcfg_pull_none>, + /* ebc_sddo9 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* ebc_sddo10 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* ebc_sddo11 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* ebc_sddo12 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* ebc_sddo13 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* ebc_sddo14 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* ebc_sddo15 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* ebc_sdle */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* ebc_sdoe */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + edpdp { + /omit-if-no-ref/ + edpdpm0_pins: edpdpm0-pins { + rockchip,pins = + /* edpdp_hpdinm0 */ + <4 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + edpdpm1_pins: edpdpm1-pins { + rockchip,pins = + /* edpdp_hpdinm1 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_datastrobe: emmc-datastrobe { + rockchip,pins = + /* emmc_datastrobe */ + <1 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko25m */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1m0_pins: eth1m0-pins { + rockchip,pins = + /* eth1_refclko25mm0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth1m1_pins: eth1m1-pins { + rockchip,pins = + /* eth1_refclko25mm1 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + flash { + /omit-if-no-ref/ + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PD0 2 &pcfg_pull_none>, + /* flash_cle */ + <1 RK_PC6 3 &pcfg_pull_none>, + /* flash_cs0n */ + <1 RK_PD3 2 &pcfg_pull_none>, + /* flash_cs1n */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* flash_d0 */ + <1 RK_PB4 2 &pcfg_pull_none>, + /* flash_d1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* flash_d2 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* flash_d3 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* flash_d4 */ + <1 RK_PC0 2 &pcfg_pull_none>, + /* flash_d5 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* flash_d6 */ + <1 RK_PC2 2 &pcfg_pull_none>, + /* flash_d7 */ + <1 RK_PC3 2 &pcfg_pull_none>, + /* flash_dqs */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* flash_rdy */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* flash_volsel */ + <0 RK_PA7 1 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PC7 3 &pcfg_pull_none>, + /* flash_wrn */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs1: fspi-cs1 { + rockchip,pins = + /* fspi_cs1n */ + <1 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* gmac0_mdio */ + <2 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_er: gmac0-rx-er { + rockchip,pins = + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_er: gmac1m0-rx-er { + rockchip,pins = + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_miim: gmac1m1-miim { + rockchip,pins = + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_clkinout: gmac1m1-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_er: gmac1m1-rx-er { + rockchip,pins = + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_bus2: gmac1m1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2: gmac1m1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* gpu_pwren */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + hdmitx { + /omit-if-no-ref/ + hdmitxm0_cec: hdmitxm0-cec { + rockchip,pins = + /* hdmitxm0_cec */ + <4 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitxm1_cec: hdmitxm1-cec { + rockchip,pins = + /* hdmitxm1_cec */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_scl: hdmitx-scl { + rockchip,pins = + /* hdmitx_scl */ + <4 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_sda: hdmitx-sda { + rockchip,pins = + /* hdmitx_sda */ + <4 RK_PD0 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_sclm0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_sclm1 */ + <4 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam1 */ + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_sclm0 */ + <1 RK_PA1 1 &pcfg_pull_none_smt>, + /* i2c3_sdam0 */ + <1 RK_PA0 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_sclm1 */ + <3 RK_PB5 4 &pcfg_pull_none_smt>, + /* i2c3_sdam1 */ + <3 RK_PB6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_sclm0 */ + <4 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c4_sdam0 */ + <4 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_sclm1 */ + <2 RK_PB2 2 &pcfg_pull_none_smt>, + /* i2c4_sdam1 */ + <2 RK_PB1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_sclm0 */ + <3 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c5_sdam0 */ + <3 RK_PB4 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_sclm1 */ + <4 RK_PC7 2 &pcfg_pull_none_smt>, + /* i2c5_sdam1 */ + <4 RK_PD0 2 &pcfg_pull_none_smt>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <1 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrckrx: i2s1m1-lrckrx { + rockchip,pins = + /* i2s1m1_lrckrx */ + <4 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrcktx: i2s1m1-lrcktx { + rockchip,pins = + /* i2s1m1_lrcktx */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclkrx: i2s1m1-sclkrx { + rockchip,pins = + /* i2s1m1_sclkrx */ + <4 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclktx: i2s1m1-sclktx { + rockchip,pins = + /* i2s1m1_sclktx */ + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <4 RK_PB0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrckrx: i2s1m2-lrckrx { + rockchip,pins = + /* i2s1m2_lrckrx */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrcktx: i2s1m2-lrcktx { + rockchip,pins = + /* i2s1m2_lrcktx */ + <2 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_mclk: i2s1m2-mclk { + rockchip,pins = + /* i2s1m2_mclk */ + <2 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclkrx: i2s1m2-sclkrx { + rockchip,pins = + /* i2s1m2_sclkrx */ + <3 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclktx: i2s1m2-sclktx { + rockchip,pins = + /* i2s1m2_sclktx */ + <2 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi0: i2s1m2-sdi0 { + rockchip,pins = + /* i2s1m2_sdi0 */ + <2 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi1: i2s1m2-sdi1 { + rockchip,pins = + /* i2s1m2_sdi1 */ + <2 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi2: i2s1m2-sdi2 { + rockchip,pins = + /* i2s1m2_sdi2 */ + <2 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi3: i2s1m2-sdi3 { + rockchip,pins = + /* i2s1m2_sdi3 */ + <2 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo0: i2s1m2-sdo0 { + rockchip,pins = + /* i2s1m2_sdo0 */ + <2 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo1: i2s1m2-sdo1 { + rockchip,pins = + /* i2s1m2_sdo1 */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo2: i2s1m2-sdo2 { + rockchip,pins = + /* i2s1m2_sdo2 */ + <3 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo3: i2s1m2-sdo3 { + rockchip,pins = + /* i2s1m2_sdo3 */ + <3 RK_PC2 5 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + /* i2s2m0_lrckrx */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + /* i2s2m0_lrcktx */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclkrx: i2s2m0-sclkrx { + rockchip,pins = + /* i2s2m0_sclkrx */ + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclktx: i2s2m0-sclktx { + rockchip,pins = + /* i2s2m0_sclktx */ + <2 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrckrx: i2s2m1-lrckrx { + rockchip,pins = + /* i2s2m1_lrckrx */ + <4 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + /* i2s2m1_lrcktx */ + <4 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclkrx: i2s2m1-sclkrx { + rockchip,pins = + /* i2s2m1_sclkrx */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclktx: i2s2m1-sclktx { + rockchip,pins = + /* i2s2m1_sclktx */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <4 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <4 RK_PB3 5 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3m0_lrck: i2s3m0-lrck { + rockchip,pins = + /* i2s3m0_lrck */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_mclk: i2s3m0-mclk { + rockchip,pins = + /* i2s3m0_mclk */ + <3 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sclk: i2s3m0-sclk { + rockchip,pins = + /* i2s3m0_sclk */ + <3 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdi: i2s3m0-sdi { + rockchip,pins = + /* i2s3m0_sdi */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdo: i2s3m0-sdo { + rockchip,pins = + /* i2s3m0_sdo */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_lrck: i2s3m1-lrck { + rockchip,pins = + /* i2s3m1_lrck */ + <4 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_mclk: i2s3m1-mclk { + rockchip,pins = + /* i2s3m1_mclk */ + <4 RK_PC2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sclk: i2s3m1-sclk { + rockchip,pins = + /* i2s3m1_sclk */ + <4 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdi: i2s3m1-sdi { + rockchip,pins = + /* i2s3m1_sdi */ + <4 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdo: i2s3m1-sdo { + rockchip,pins = + /* i2s3m1_sdo */ + <4 RK_PC5 5 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flashtrigin */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* isp_flashtrigout */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* isp_prelighttrig */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtag_pins: jtag-pins { + rockchip,pins = + /* jtag_tck */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* jtag_tms */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + lcdc { + /omit-if-no-ref/ + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_d0 */ + <2 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d1 */ + <2 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PA1 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtagtck */ + <0 RK_PB4 4 &pcfg_pull_none>, + /* mcu_jtagtdi */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* mcu_jtagtdo */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* mcu_jtagtms */ + <0 RK_PC2 4 &pcfg_pull_none>, + /* mcu_jtagtrstn */ + <0 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqnm0 */ + <0 RK_PA5 3 &pcfg_pull_none>, + /* pcie20_perstnm0 */ + <0 RK_PB6 3 &pcfg_pull_none>, + /* pcie20_wakenm0 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqnm1 */ + <2 RK_PD0 4 &pcfg_pull_none>, + /* pcie20_perstnm1 */ + <3 RK_PC1 4 &pcfg_pull_none>, + /* pcie20_wakenm1 */ + <2 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m2_pins: pcie20m2-pins { + rockchip,pins = + /* pcie20_clkreqnm2 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_perstnm2 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie20_wakenm2 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_clkreqnm0 */ + <0 RK_PA4 3 &pcfg_pull_none>, + /* pcie30x1_perstnm0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* pcie30x1_wakenm0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_clkreqnm1 */ + <2 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x1_perstnm1 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* pcie30x1_wakenm1 */ + <2 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_clkreqnm2 */ + <1 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_perstnm2 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_wakenm2 */ + <1 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_buttonrstn: pcie30x1-buttonrstn { + rockchip,pins = + /* pcie30x1_buttonrstn */ + <0 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqnm0 */ + <0 RK_PA6 2 &pcfg_pull_none>, + /* pcie30x2_perstnm0 */ + <0 RK_PC6 3 &pcfg_pull_none>, + /* pcie30x2_wakenm0 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqnm1 */ + <2 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_perstnm1 */ + <2 RK_PD6 4 &pcfg_pull_none>, + /* pcie30x2_wakenm1 */ + <2 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqnm2 */ + <4 RK_PC2 4 &pcfg_pull_none>, + /* pcie30x2_perstnm2 */ + <4 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x2_wakenm2 */ + <4 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_buttonrstn: pcie30x2-buttonrstn { + rockchip,pins = + /* pcie30x2_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0m0 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdmm0_clk1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdmm0_sdi0 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdmm0_sdi1 */ + <1 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdmm0_sdi2 */ + <1 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdmm0_sdi3 */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0m1 */ + <3 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdmm1_clk1 */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdmm1_sdi0 */ + <3 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdmm1_sdi1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdmm1_sdi2 */ + <4 RK_PA2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdmm1_sdi3 */ + <4 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_clk1: pdmm2-clk1 { + rockchip,pins = + /* pdmm2_clk1 */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi0: pdmm2-sdi0 { + rockchip,pins = + /* pdmm2_sdi0 */ + <3 RK_PB3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi1: pdmm2-sdi1 { + rockchip,pins = + /* pdmm2_sdi1 */ + <3 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi2: pdmm2-sdi2 { + rockchip,pins = + /* pdmm2_sdi2 */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi3: pdmm2-sdi3 { + rockchip,pins = + /* pdmm2_sdi3 */ + <3 RK_PC0 5 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_sleep */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug0 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* pmu_debug1 */ + <0 RK_PA6 3 &pcfg_pull_none>, + /* pmu_debug2 */ + <0 RK_PC4 4 &pcfg_pull_none>, + /* pmu_debug3 */ + <0 RK_PC5 4 &pcfg_pull_none>, + /* pmu_debug4 */ + <0 RK_PC6 4 &pcfg_pull_none>, + /* pmu_debug5 */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <0 RK_PB5 4 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <0 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3_pins: pwm3-pins { + rockchip,pins = + /* pwm3_ir */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4_pins: pwm4-pins { + rockchip,pins = + /* pwm4 */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5_pins: pwm5-pins { + rockchip,pins = + /* pwm5 */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6_pins: pwm6-pins { + rockchip,pins = + /* pwm6 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7_pins: pwm7-pins { + rockchip,pins = + /* pwm7_ir */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_irm0 */ + <3 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_irm1 */ + <4 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_irm0 */ + <3 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_irm1 */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_ou */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cpdet */ + <0 RK_PA4 2 &pcfg_pull_none>, + /* sata_cppod */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* sata_mpswitch */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0_pins: sata0-pins { + rockchip,pins = + /* sata0_actled */ + <4 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1_pins: sata1-pins { + rockchip,pins = + /* sata1_actled */ + <4 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2_pins: sata2-pins { + rockchip,pins = + /* sata2_actled */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scr_pins: scr-pins { + rockchip,pins = + /* scr_clk */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_det */ + <1 RK_PA7 3 &pcfg_pull_up>, + /* scr_io */ + <1 RK_PA3 3 &pcfg_pull_up>, + /* scr_rst */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + sdmmc2 { + /omit-if-no-ref/ + sdmmc2m0_bus4: sdmmc2m0-bus4 { + rockchip,pins = + /* sdmmc2_d0m0 */ + <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m0 */ + <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m0 */ + <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m0 */ + <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_clk: sdmmc2m0-clk { + rockchip,pins = + /* sdmmc2_clkm0 */ + <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_cmd: sdmmc2m0-cmd { + rockchip,pins = + /* sdmmc2_cmdm0 */ + <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_det: sdmmc2m0-det { + rockchip,pins = + /* sdmmc2_detm0 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m0_pwren: sdmmc2m0-pwren { + rockchip,pins = + /* sdmmc2m0_pwren */ + <3 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc2m1_bus4: sdmmc2m1-bus4 { + rockchip,pins = + /* sdmmc2_d0m1 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m1 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m1 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m1 */ + <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_clk: sdmmc2m1-clk { + rockchip,pins = + /* sdmmc2_clkm1 */ + <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_cmd: sdmmc2m1-cmd { + rockchip,pins = + /* sdmmc2_cmdm1 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_det: sdmmc2m1-det { + rockchip,pins = + /* sdmmc2_detm1 */ + <3 RK_PA7 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m1_pwren: sdmmc2m1-pwren { + rockchip,pins = + /* sdmmc2m1_pwren */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_tx: spdifm0-tx { + rockchip,pins = + /* spdifm0_tx */ + <1 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_tx: spdifm1-tx { + rockchip,pins = + /* spdifm1_tx */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_tx: spdifm2-tx { + rockchip,pins = + /* spdifm2_tx */ + <4 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_none>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_none>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_none>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_none>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_none>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_none>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_none>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_none>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_none>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_none>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_none>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_none>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_none>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_shut: tsadcm0-shut { + rockchip,pins = + /* tsadcm0_shut */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + /* tsadc_shutorg */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC0 3 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC1 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PC7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <2 RK_PB3 2 &pcfg_pull_up>, + /* uart1_txm0 */ + <2 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <3 RK_PD7 4 &pcfg_pull_up>, + /* uart1_txm1 */ + <3 RK_PD6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart2_txm0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <1 RK_PD6 2 &pcfg_pull_up>, + /* uart2_txm1 */ + <1 RK_PD5 2 &pcfg_pull_up>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <1 RK_PA0 2 &pcfg_pull_up>, + /* uart3_txm0 */ + <1 RK_PA1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <1 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rxm1 */ + <3 RK_PC0 4 &pcfg_pull_up>, + /* uart3_txm1 */ + <3 RK_PB7 4 &pcfg_pull_up>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rxm0 */ + <1 RK_PA4 2 &pcfg_pull_up>, + /* uart4_txm0 */ + <1 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rxm1 */ + <3 RK_PB1 4 &pcfg_pull_up>, + /* uart4_txm1 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rxm0 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_txm0 */ + <2 RK_PA2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rxm1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart5_txm1 */ + <3 RK_PC2 4 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rxm0 */ + <2 RK_PA3 3 &pcfg_pull_up>, + /* uart6_txm0 */ + <2 RK_PA4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rxm1 */ + <1 RK_PD6 3 &pcfg_pull_up>, + /* uart6_txm1 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rxm0 */ + <2 RK_PA5 3 &pcfg_pull_up>, + /* uart7_txm0 */ + <2 RK_PA6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <2 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <2 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rxm1 */ + <3 RK_PC5 4 &pcfg_pull_up>, + /* uart7_txm1 */ + <3 RK_PC4 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rxm2 */ + <4 RK_PA3 4 &pcfg_pull_up>, + /* uart7_txm2 */ + <4 RK_PA2 4 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rxm0 */ + <2 RK_PC6 2 &pcfg_pull_up>, + /* uart8_txm0 */ + <2 RK_PC5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <2 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rxm1 */ + <3 RK_PA0 4 &pcfg_pull_up>, + /* uart8_txm1 */ + <2 RK_PD7 4 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rxm0 */ + <2 RK_PA7 3 &pcfg_pull_up>, + /* uart9_txm0 */ + <2 RK_PB0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <2 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <2 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rxm1 */ + <4 RK_PC6 4 &pcfg_pull_up>, + /* uart9_txm1 */ + <4 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rxm2 */ + <4 RK_PA5 4 &pcfg_pull_up>, + /* uart9_txm2 */ + <4 RK_PA4 4 &pcfg_pull_up>; + }; + }; + + vop { + /omit-if-no-ref/ + vopm0_pins: vopm0-pins { + rockchip,pins = + /* vop_pwmm0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + vopm1_pins: vopm1-pins { + rockchip,pins = + /* vop_pwmm1 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + spi0-hs { + /omit-if-no-ref/ + spi0m0_pins_hs: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0_hs: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1_hs: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_pins_hs: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0_hs: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1-hs { + /omit-if-no-ref/ + spi1m0_pins_hs: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0_hs: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1_hs: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_pins_hs: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0_hs: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2-hs { + /omit-if-no-ref/ + spi2m0_pins_hs: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0_hs: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1_hs: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins_hs: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0_hs: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1_hs: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3-hs { + /omit-if-no-ref/ + spi3m0_pins_hs: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0_hs: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1_hs: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_pins_hs: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0_hs: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1_hs: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; + }; + }; + + gmac-txd-level3 { + /omit-if-no-ref/ + gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; + }; + }; + + gmac-txc-level2 { + /omit-if-no-ref/ + gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi new file mode 100644 index 00000000000000..d225e6a45d5cb1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3568"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&scmi_clk 0>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1150000>; + opp-suspend; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <975000 975000 1150000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000 1050000 1150000>; + }; + + opp-1992000000 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000 1150000 1150000>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + pinctrl-0 = <&clk32k_out0>; + pinctrl-names = "default"; + #clock-cells = <0>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ + <0x0 0xfd460000 0 0x80000>; /* GICR */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + mbi-alias = <0x0 0xfd100000>; + mbi-ranges = <296 24>; + msi-controller; + }; + + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; + }; + + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + i2c0: i2c@fdd40000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfdd40000 0x0 0x1000>; + interrupts = ; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fdd50000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfdd50000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + pinctrl-0 = <&uart0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, + <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC2>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc1: mmc@fe2c0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC1>; + reset-names = "reset"; + status = "disabled"; + }; + + sdhci: mmc@fe310000 { + compatible = "rockchip,rk3568-dwcmshc"; + reg = <0x0 0xfe310000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dmac@fe550000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe550000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fe5a0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c1_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe5b0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5b0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe5c0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5c0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe5d0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5d0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe5e0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5e0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + pinctrl-0 = <&uart1m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@fe660000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe660000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 4>, <&dmac0 5>; + pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@fe670000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe670000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-0 = <&uart3m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@fe680000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe680000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-0 = <&uart4m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@fe690000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe690000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-0 = <&uart5m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@fe6a0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@fe6b0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + pinctrl-0 = <&uart7m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@fe6c0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + pinctrl-0 = <&uart8m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@fe6d0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 18>, <&dmac0 19>; + pinctrl-0 = <&uart9m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe760000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3568-pinctrl.dtsi" From 01610a24cefa182b155a17e38cd0b84f8a3f0529 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 22 Jun 2021 10:05:17 +0800 Subject: [PATCH 511/511] arm64: dts: rockchip: add basic dts for RK3568 EVB This patch add rk3568-evb1-v10.dts for RK3568 evaluation board. add uart/emmc/i2c/rk809 node for basic function. Signed-off-by: Liang Chen Link: https://lore.kernel.org/r/20210622020517.13100-5-cl@rock-chips.com Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 5 ++ arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-evb1-v10.dts | 79 +++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 4a6f772c104385..6546b015fc623f 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -600,6 +600,11 @@ properties: - const: zkmagic,a95x-z2 - const: rockchip,rk3318 + - description: Rockchip RK3568 Evaluation board + items: + - const: rockchip,rk3568-evb1-v10 + - const: rockchip,rk3568 + additionalProperties: true ... diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index c3e00c0e2db7e1..7fdb41de01ec9f 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -51,3 +51,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts new file mode 100644 index 00000000000000..69786557093dae --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; + compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + status = "okay"; +}; + +&uart2 { + status = "okay"; +};