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ptp_clockmatrix.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
* synchronization devices.
*
* Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
*/
#include <linux/firmware.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/timekeeping.h>
#include <linux/string.h>
#include <linux/of.h>
#include <linux/mfd/rsmu.h>
#include <linux/mfd/idt8a340_reg.h>
#include <asm/unaligned.h>
#include "ptp_private.h"
#include "ptp_clockmatrix.h"
MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
MODULE_AUTHOR("Richard Cochran <[email protected]>");
MODULE_AUTHOR("IDT support-1588 <[email protected]>");
MODULE_VERSION("1.0");
MODULE_LICENSE("GPL");
/*
* The name of the firmware file to be loaded
* over-rides any automatic selection
*/
static char *firmware;
module_param(firmware, charp, 0);
#define SETTIME_CORRECTION (0)
#define EXTTS_PERIOD_MS (95)
static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
static inline int idtcm_read(struct idtcm *idtcm,
u16 module,
u16 regaddr,
u8 *buf,
u16 count)
{
return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count);
}
static inline int idtcm_write(struct idtcm *idtcm,
u16 module,
u16 regaddr,
u8 *buf,
u16 count)
{
return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count);
}
static int contains_full_configuration(struct idtcm *idtcm,
const struct firmware *fw)
{
struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
s32 full_count;
s32 count = 0;
u16 regaddr;
u8 loaddr;
s32 len;
/* 4 bytes skipped every 0x80 */
full_count = (scratch - GPIO_USER_CONTROL) -
((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4;
/* If the firmware contains 'full configuration' SM_RESET can be used
* to ensure proper configuration.
*
* Full configuration is defined as the number of programmable
* bytes within the configuration range minus page offset addr range.
*/
for (len = fw->size; len > 0; len -= sizeof(*rec)) {
regaddr = rec->hiaddr << 8;
regaddr |= rec->loaddr;
loaddr = rec->loaddr;
rec++;
/* Top (status registers) and bottom are read-only */
if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
continue;
/* Page size 128, last 4 bytes of page skipped */
if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
continue;
count++;
}
return (count >= full_count);
}
static int char_array_to_timespec(u8 *buf,
u8 count,
struct timespec64 *ts)
{
u8 i;
u64 nsec;
time64_t sec;
if (count < TOD_BYTE_COUNT)
return 1;
/* Sub-nanoseconds are in buf[0]. */
nsec = buf[4];
for (i = 0; i < 3; i++) {
nsec <<= 8;
nsec |= buf[3 - i];
}
sec = buf[10];
for (i = 0; i < 5; i++) {
sec <<= 8;
sec |= buf[9 - i];
}
ts->tv_sec = sec;
ts->tv_nsec = nsec;
return 0;
}
static int timespec_to_char_array(struct timespec64 const *ts,
u8 *buf,
u8 count)
{
u8 i;
s32 nsec;
time64_t sec;
if (count < TOD_BYTE_COUNT)
return 1;
nsec = ts->tv_nsec;
sec = ts->tv_sec;
/* Sub-nanoseconds are in buf[0]. */
buf[0] = 0;
for (i = 1; i < 5; i++) {
buf[i] = nsec & 0xff;
nsec >>= 8;
}
for (i = 5; i < TOD_BYTE_COUNT; i++) {
buf[i] = sec & 0xff;
sec >>= 8;
}
return 0;
}
static int idtcm_strverscmp(const char *version1, const char *version2)
{
u8 ver1[3], ver2[3];
int i;
if (sscanf(version1, "%hhu.%hhu.%hhu",
&ver1[0], &ver1[1], &ver1[2]) != 3)
return -1;
if (sscanf(version2, "%hhu.%hhu.%hhu",
&ver2[0], &ver2[1], &ver2[2]) != 3)
return -1;
for (i = 0; i < 3; i++) {
if (ver1[i] > ver2[i])
return 1;
if (ver1[i] < ver2[i])
return -1;
}
return 0;
}
static enum fw_version idtcm_fw_version(const char *version)
{
enum fw_version ver = V_DEFAULT;
if (idtcm_strverscmp(version, "4.8.7") >= 0)
ver = V487;
if (idtcm_strverscmp(version, "5.2.0") >= 0)
ver = V520;
return ver;
}
static int clear_boot_status(struct idtcm *idtcm)
{
u8 buf[4] = {0};
return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
}
static int read_boot_status(struct idtcm *idtcm, u32 *status)
{
int err;
u8 buf[4] = {0};
err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
*status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
return err;
}
static int wait_for_boot_status_ready(struct idtcm *idtcm)
{
u32 status = 0;
u8 i = 30; /* 30 * 100ms = 3s */
int err;
do {
err = read_boot_status(idtcm, &status);
if (err)
return err;
if (status == 0xA0)
return 0;
msleep(100);
i--;
} while (i);
dev_warn(idtcm->dev, "%s timed out", __func__);
return -EBUSY;
}
static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)
{
struct idtcm *idtcm = channel->idtcm;
u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
u8 val = 0;
int err;
val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
val |= (ref << WR_REF_INDEX_SHIFT);
err = idtcm_write(idtcm, channel->tod_read_secondary,
TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val));
if (err)
return err;
val = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT);
err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
&val, sizeof(val));
if (err)
dev_err(idtcm->dev, "%s: err = %d", __func__, err);
return err;
}
static bool is_single_shot(u8 mask)
{
/* Treat single bit ToD masks as continuous trigger */
return !(mask <= 8 && is_power_of_2(mask));
}
static int idtcm_extts_enable(struct idtcm_channel *channel,
struct ptp_clock_request *rq, int on)
{
u8 index = rq->extts.index;
struct idtcm *idtcm;
u8 mask = 1 << index;
int err = 0;
u8 old_mask;
int ref;
idtcm = channel->idtcm;
old_mask = idtcm->extts_mask;
/* Reject requests with unsupported flags */
if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
PTP_RISING_EDGE |
PTP_FALLING_EDGE |
PTP_STRICT_FLAGS))
return -EOPNOTSUPP;
/* Reject requests to enable time stamping on falling edge */
if ((rq->extts.flags & PTP_ENABLE_FEATURE) &&
(rq->extts.flags & PTP_FALLING_EDGE))
return -EOPNOTSUPP;
if (index >= MAX_TOD)
return -EINVAL;
if (on) {
/* Support triggering more than one TOD_0/1/2/3 by same pin */
/* Use the pin configured for the channel */
ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod);
if (ref < 0) {
dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n",
__func__, channel->tod);
return -EBUSY;
}
err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
if (err == 0) {
idtcm->extts_mask |= mask;
idtcm->event_channel[index] = channel;
idtcm->channel[index].refn = ref;
idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
if (old_mask)
return 0;
schedule_delayed_work(&idtcm->extts_work,
msecs_to_jiffies(EXTTS_PERIOD_MS));
}
} else {
idtcm->extts_mask &= ~mask;
idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
if (idtcm->extts_mask == 0)
cancel_delayed_work(&idtcm->extts_work);
}
return err;
}
static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
{
return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
sizeof(u8));
}
static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
{
return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
}
static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
{
unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
u8 apll = 0;
u8 dpll = 0;
int err;
do {
err = read_sys_apll_status(idtcm, &apll);
if (err)
return err;
err = read_sys_dpll_status(idtcm, &dpll);
if (err)
return err;
apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
dpll &= DPLL_SYS_STATE_MASK;
if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
dpll == DPLL_STATE_LOCKED) {
return 0;
} else if (dpll == DPLL_STATE_FREERUN ||
dpll == DPLL_STATE_HOLDOVER ||
dpll == DPLL_STATE_OPEN_LOOP) {
dev_warn(idtcm->dev,
"No wait state: DPLL_SYS_STATE %d", dpll);
return -EPERM;
}
msleep(LOCK_POLL_INTERVAL_MS);
} while (time_is_after_jiffies(timeout));
dev_warn(idtcm->dev,
"%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d",
LOCK_TIMEOUT_MS, apll, dpll);
return -ETIME;
}
static void wait_for_chip_ready(struct idtcm *idtcm)
{
if (wait_for_boot_status_ready(idtcm))
dev_warn(idtcm->dev, "BOOT_STATUS != 0xA0");
if (wait_for_sys_apll_dpll_lock(idtcm))
dev_warn(idtcm->dev,
"Continuing while SYS APLL/DPLL is not locked");
}
static int _idtcm_gettime_triggered(struct idtcm_channel *channel,
struct timespec64 *ts)
{
struct idtcm *idtcm = channel->idtcm;
u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
u8 buf[TOD_BYTE_COUNT];
u8 trigger;
int err;
err = idtcm_read(idtcm, channel->tod_read_secondary,
tod_read_cmd, &trigger, sizeof(trigger));
if (err)
return err;
if (trigger & TOD_READ_TRIGGER_MASK)
return -EBUSY;
err = idtcm_read(idtcm, channel->tod_read_secondary,
TOD_READ_SECONDARY_BASE, buf, sizeof(buf));
if (err)
return err;
return char_array_to_timespec(buf, sizeof(buf), ts);
}
static int _idtcm_gettime(struct idtcm_channel *channel,
struct timespec64 *ts, u8 timeout)
{
struct idtcm *idtcm = channel->idtcm;
u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
u8 buf[TOD_BYTE_COUNT];
u8 trigger;
int err;
/* wait trigger to be 0 */
do {
if (timeout-- == 0)
return -EIO;
if (idtcm->calculate_overhead_flag)
idtcm->start_time = ktime_get_raw();
err = idtcm_read(idtcm, channel->tod_read_primary,
tod_read_cmd, &trigger,
sizeof(trigger));
if (err)
return err;
} while (trigger & TOD_READ_TRIGGER_MASK);
err = idtcm_read(idtcm, channel->tod_read_primary,
TOD_READ_PRIMARY_BASE, buf, sizeof(buf));
if (err)
return err;
err = char_array_to_timespec(buf, sizeof(buf), ts);
return err;
}
static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn)
{
struct idtcm_channel *ptp_channel, *extts_channel;
struct ptp_clock_event event;
struct timespec64 ts;
u32 dco_delay = 0;
int err;
extts_channel = &idtcm->channel[todn];
ptp_channel = idtcm->event_channel[todn];
if (extts_channel == ptp_channel)
dco_delay = ptp_channel->dco_delay;
err = _idtcm_gettime_triggered(extts_channel, &ts);
if (err)
return err;
/* Triggered - save timestamp */
event.type = PTP_CLOCK_EXTTS;
event.index = todn;
event.timestamp = timespec64_to_ns(&ts) - dco_delay;
ptp_clock_event(ptp_channel->ptp_clock, &event);
return err;
}
static int _idtcm_gettime_immediate(struct idtcm_channel *channel,
struct timespec64 *ts)
{
struct idtcm *idtcm = channel->idtcm;
u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
u8 val = (SCSR_TOD_READ_TRIG_SEL_IMMEDIATE << TOD_READ_TRIGGER_SHIFT);
int err;
err = idtcm_write(idtcm, channel->tod_read_primary,
tod_read_cmd, &val, sizeof(val));
if (err)
return err;
return _idtcm_gettime(channel, ts, 10);
}
static int _sync_pll_output(struct idtcm *idtcm,
u8 pll,
u8 sync_src,
u8 qn,
u8 qn_plus_1)
{
int err;
u8 val;
u16 sync_ctrl0;
u16 sync_ctrl1;
u8 temp;
if (qn == 0 && qn_plus_1 == 0)
return 0;
switch (pll) {
case 0:
sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
break;
case 1:
sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
break;
case 2:
sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
break;
case 3:
sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
break;
case 4:
sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
break;
case 5:
sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
break;
case 6:
sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
break;
case 7:
sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
break;
default:
return -EINVAL;
}
val = SYNCTRL1_MASTER_SYNC_RST;
/* Place master sync in reset */
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
if (err)
return err;
err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
if (err)
return err;
/* Set sync trigger mask */
val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
if (qn)
val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
if (qn_plus_1)
val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
if (err)
return err;
/* PLL5 can have OUT8 as second additional output. */
if (pll == 5 && qn_plus_1 != 0) {
err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
return err;
temp &= ~(Q9_TO_Q8_SYNC_TRIG);
err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
return err;
temp |= Q9_TO_Q8_SYNC_TRIG;
err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
return err;
}
/* PLL6 can have OUT11 as second additional output. */
if (pll == 6 && qn_plus_1 != 0) {
err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
return err;
temp &= ~(Q10_TO_Q11_SYNC_TRIG);
err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
return err;
temp |= Q10_TO_Q11_SYNC_TRIG;
err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
return err;
}
/* Place master sync out of reset */
val &= ~(SYNCTRL1_MASTER_SYNC_RST);
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
return err;
}
static int idtcm_sync_pps_output(struct idtcm_channel *channel)
{
struct idtcm *idtcm = channel->idtcm;
u8 pll;
u8 qn;
u8 qn_plus_1;
int err = 0;
u8 out8_mux = 0;
u8 out11_mux = 0;
u8 temp;
u16 output_mask = channel->output_mask;
err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
return err;
if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
out8_mux = 1;
err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
return err;
if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
out11_mux = 1;
for (pll = 0; pll < 8; pll++) {
qn = 0;
qn_plus_1 = 0;
if (pll < 4) {
/* First 4 pll has 2 outputs */
qn = output_mask & 0x1;
output_mask = output_mask >> 1;
qn_plus_1 = output_mask & 0x1;
output_mask = output_mask >> 1;
} else if (pll == 4) {
if (out8_mux == 0) {
qn = output_mask & 0x1;
output_mask = output_mask >> 1;
}
} else if (pll == 5) {
if (out8_mux) {
qn_plus_1 = output_mask & 0x1;
output_mask = output_mask >> 1;
}
qn = output_mask & 0x1;
output_mask = output_mask >> 1;
} else if (pll == 6) {
qn = output_mask & 0x1;
output_mask = output_mask >> 1;
if (out11_mux) {
qn_plus_1 = output_mask & 0x1;
output_mask = output_mask >> 1;
}
} else if (pll == 7) {
if (out11_mux == 0) {
qn = output_mask & 0x1;
output_mask = output_mask >> 1;
}
}
if (qn != 0 || qn_plus_1 != 0)
err = _sync_pll_output(idtcm, pll, channel->sync_src,
qn, qn_plus_1);
if (err)
return err;
}
return err;
}
static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
struct timespec64 const *ts,
enum hw_tod_write_trig_sel wr_trig)
{
struct idtcm *idtcm = channel->idtcm;
u8 buf[TOD_BYTE_COUNT];
u8 cmd;
int err;
struct timespec64 local_ts = *ts;
s64 total_overhead_ns;
/* Configure HW TOD write trigger. */
err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
&cmd, sizeof(cmd));
if (err)
return err;
cmd &= ~(0x0f);
cmd |= wr_trig | 0x08;
err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
&cmd, sizeof(cmd));
if (err)
return err;
if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
if (err)
return err;
err = idtcm_write(idtcm, channel->hw_dpll_n,
HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
if (err)
return err;
}
/* ARM HW TOD write trigger. */
cmd &= ~(0x08);
err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
&cmd, sizeof(cmd));
if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
if (idtcm->calculate_overhead_flag) {
/* Assumption: I2C @ 400KHz */
ktime_t diff = ktime_sub(ktime_get_raw(),
idtcm->start_time);
total_overhead_ns = ktime_to_ns(diff)
+ idtcm->tod_write_overhead_ns
+ SETTIME_CORRECTION;
timespec64_add_ns(&local_ts, total_overhead_ns);
idtcm->calculate_overhead_flag = 0;
}
err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
if (err)
return err;
err = idtcm_write(idtcm, channel->hw_dpll_n,
HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
}
return err;
}
static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
struct timespec64 const *ts,
enum scsr_tod_write_trig_sel wr_trig,
enum scsr_tod_write_type_sel wr_type)
{
struct idtcm *idtcm = channel->idtcm;
unsigned char buf[TOD_BYTE_COUNT], cmd;
struct timespec64 local_ts = *ts;
int err, count = 0;
timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
if (err)
return err;
err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
buf, sizeof(buf));
if (err)
return err;
/* Trigger the write operation. */
err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
&cmd, sizeof(cmd));
if (err)
return err;
cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
&cmd, sizeof(cmd));
if (err)
return err;
/* Wait for the operation to complete. */
while (1) {
/* pps trigger takes up to 1 sec to complete */
if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
msleep(50);
err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
&cmd, sizeof(cmd));
if (err)
return err;
if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
break;
if (++count > 20) {
dev_err(idtcm->dev,
"Timed out waiting for the write counter");
return -EIO;
}
}
return 0;
}
static int get_output_base_addr(enum fw_version ver, u8 outn)
{
int base;
switch (outn) {
case 0:
base = IDTCM_FW_REG(ver, V520, OUTPUT_0);
break;
case 1:
base = IDTCM_FW_REG(ver, V520, OUTPUT_1);
break;
case 2:
base = IDTCM_FW_REG(ver, V520, OUTPUT_2);
break;
case 3:
base = IDTCM_FW_REG(ver, V520, OUTPUT_3);
break;
case 4:
base = IDTCM_FW_REG(ver, V520, OUTPUT_4);
break;
case 5:
base = IDTCM_FW_REG(ver, V520, OUTPUT_5);
break;
case 6:
base = IDTCM_FW_REG(ver, V520, OUTPUT_6);
break;
case 7:
base = IDTCM_FW_REG(ver, V520, OUTPUT_7);
break;
case 8:
base = IDTCM_FW_REG(ver, V520, OUTPUT_8);
break;
case 9:
base = IDTCM_FW_REG(ver, V520, OUTPUT_9);
break;
case 10:
base = IDTCM_FW_REG(ver, V520, OUTPUT_10);
break;
case 11:
base = IDTCM_FW_REG(ver, V520, OUTPUT_11);
break;
default:
base = -EINVAL;
}
return base;
}
static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
struct timespec64 const *ts)
{
struct idtcm *idtcm = channel->idtcm;
int err;
err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
if (err) {
dev_err(idtcm->dev,
"%s: Set HW ToD failed", __func__);
return err;
}
return idtcm_sync_pps_output(channel);
}
static int _idtcm_settime(struct idtcm_channel *channel,
struct timespec64 const *ts,
enum scsr_tod_write_type_sel wr_type)
{
return _idtcm_set_dpll_scsr_tod(channel, ts,
SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
wr_type);
}
static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
s32 offset_ns)
{
int err;
int i;
struct idtcm *idtcm = channel->idtcm;
u8 buf[4];
for (i = 0; i < 4; i++) {
buf[i] = 0xff & (offset_ns);
offset_ns >>= 8;
}
err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
buf, sizeof(buf));
return err;
}
static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
u32 max_ffo_ppb)
{
int err;
u8 i;
struct idtcm *idtcm = channel->idtcm;
u8 buf[3];
if (max_ffo_ppb & 0xff000000)
max_ffo_ppb = 0;
for (i = 0; i < 3; i++) {
buf[i] = 0xff & (max_ffo_ppb);
max_ffo_ppb >>= 8;
}
err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
return err;
}
static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
{
int err;
struct idtcm *idtcm = channel->idtcm;
u8 buf;
err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
&buf, sizeof(buf));
if (err)
return err;
if (buf == 0) {
buf = 0x01;
err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
PULL_IN_CTRL, &buf, sizeof(buf));
} else {
err = -EBUSY;
}
return err;
}
static int do_phase_pull_in_fw(struct idtcm_channel *channel,
s32 offset_ns,
u32 max_ffo_ppb)
{
int err;
err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
if (err)
return err;
err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
if (err)
return err;
err = idtcm_start_phase_pull_in(channel);
return err;
}
static int set_tod_write_overhead(struct idtcm_channel *channel)
{
struct idtcm *idtcm = channel->idtcm;
s64 current_ns = 0;
s64 lowest_ns = 0;
int err;
u8 i;
ktime_t start;
ktime_t stop;
ktime_t diff;
char buf[TOD_BYTE_COUNT] = {0};