forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathdgrs.c
1617 lines (1429 loc) · 38.3 KB
/
dgrs.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Digi RightSwitch SE-X loadable device driver for Linux
*
* The RightSwitch is a 4 (EISA) or 6 (PCI) port etherswitch and
* a NIC on an internal board.
*
* Author: Rick Richardson, [email protected]
* Derived from the SVR4.2 (UnixWare) driver for the same card.
*
* Copyright 1995-1996 Digi International Inc.
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
* For information on purchasing a RightSwitch SE-4 or SE-6
* board, please contact Digi's sales department at 1-612-912-3444
* or 1-800-DIGIBRD. Outside the U.S., please check our Web page
* at http://www.dgii.com for sales offices worldwide.
*
* OPERATION:
* When compiled as a loadable module, this driver can operate
* the board as either a 4/6 port switch with a 5th or 7th port
* that is a conventional NIC interface as far as the host is
* concerned, OR as 4/6 independent NICs. To select multi-NIC
* mode, add "nicmode=1" on the insmod load line for the driver.
*
* This driver uses the "dev" common ethernet device structure
* and a private "priv" (dev->priv) structure that contains
* mostly DGRS-specific information and statistics. To keep
* the code for both the switch mode and the multi-NIC mode
* as similar as possible, I have introduced the concept of
* "dev0"/"priv0" and "devN"/"privN" pointer pairs in subroutines
* where needed. The first pair of pointers points to the
* "dev" and "priv" structures of the zeroth (0th) device
* interface associated with a board. The second pair of
* pointers points to the current (Nth) device interface
* for the board: the one for which we are processing data.
*
* In switch mode, the pairs of pointers are always the same,
* that is, dev0 == devN and priv0 == privN. This is just
* like previous releases of this driver which did not support
* NIC mode.
*
* In multi-NIC mode, the pairs of pointers may be different.
* We use the devN and privN pointers to reference just the
* name, port number, and statistics for the current interface.
* We use the dev0 and priv0 pointers to access the variables
* that control access to the board, such as board address
* and simulated 82596 variables. This is because there is
* only one "fake" 82596 that serves as the interface to
* the board. We do not want to try to keep the variables
* associated with this 82596 in sync across all devices.
*
* This scheme works well. As you will see, except for
* initialization, there is very little difference between
* the two modes as far as this driver is concerned. On the
* receive side in NIC mode, the interrupt *always* comes in on
* the 0th interface (dev0/priv0). We then figure out which
* real 82596 port it came in on from looking at the "chan"
* member that the board firmware adds at the end of each
* RBD (a.k.a. TBD). We get the channel number like this:
* int chan = ((I596_RBD *) S2H(cbp->xmit.tbdp))->chan;
*
* On the transmit side in multi-NIC mode, we specify the
* output 82596 port by setting the new "dstchan" structure
* member that is at the end of the RFD, like this:
* priv0->rfdp->dstchan = privN->chan;
*
* TODO:
* - Multi-NIC mode is not yet supported when the driver is linked
* into the kernel.
* - Better handling of multicast addresses.
*
* Fixes:
* Arnaldo Carvalho de Melo <[email protected]> - 11/01/2001
* - fix dgrs_found_device wrt checking kmalloc return and
* rollbacking the partial steps of the whole process when
* one of the devices can't be allocated. Fix SET_MODULE_OWNER
* on the loop to use devN instead of repeated calls to dev.
*
* davej <[email protected]> - 9/2/2001
* - Enable PCI device before reading ioaddr/irq
*
*/
#include <linux/module.h>
#include <linux/eisa.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <asm/uaccess.h>
static char version[] __initdata =
"$Id: dgrs.c,v 1.13 2000/06/06 04:07:00 rick Exp $";
/*
* DGRS include files
*/
typedef unsigned char uchar;
typedef unsigned int bool;
#define vol volatile
#include "dgrs.h"
#include "dgrs_es4h.h"
#include "dgrs_plx9060.h"
#include "dgrs_i82596.h"
#include "dgrs_ether.h"
#include "dgrs_asstruct.h"
#include "dgrs_bcomm.h"
#ifdef CONFIG_PCI
static struct pci_device_id dgrs_pci_tbl[] = {
{ SE6_PCI_VENDOR_ID, SE6_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, },
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(pci, dgrs_pci_tbl);
#endif
#ifdef CONFIG_EISA
static struct eisa_device_id dgrs_eisa_tbl[] = {
{ "DBI0A01" },
{ }
};
MODULE_DEVICE_TABLE(eisa, dgrs_eisa_tbl);
#endif
MODULE_LICENSE("GPL");
/*
* Firmware. Compiled separately for local compilation,
* but #included for Linux distribution.
*/
#ifndef NOFW
#include "dgrs_firmware.c"
#else
extern int dgrs_firmnum;
extern char dgrs_firmver[];
extern char dgrs_firmdate[];
extern uchar dgrs_code[];
extern int dgrs_ncode;
#endif
/*
* Linux out*() is backwards from all other operating systems
*/
#define OUTB(ADDR, VAL) outb(VAL, ADDR)
#define OUTW(ADDR, VAL) outw(VAL, ADDR)
#define OUTL(ADDR, VAL) outl(VAL, ADDR)
/*
* Macros to convert switch to host and host to switch addresses
* (assumes a local variable priv points to board dependent struct)
*/
#define S2H(A) ( ((unsigned long)(A)&0x00ffffff) + priv0->vmem )
#define S2HN(A) ( ((unsigned long)(A)&0x00ffffff) + privN->vmem )
#define H2S(A) ( ((char *) (A) - priv0->vmem) + 0xA3000000 )
/*
* Convert a switch address to a "safe" address for use with the
* PLX 9060 DMA registers and the associated HW kludge that allows
* for host access of the DMA registers.
*/
#define S2DMA(A) ( (unsigned long)(A) & 0x00ffffff)
/*
* "Space.c" variables, now settable from module interface
* Use the name below, minus the "dgrs_" prefix. See init_module().
*/
static int dgrs_debug = 1;
static int dgrs_dma = 1;
static int dgrs_spantree = -1;
static int dgrs_hashexpire = -1;
static uchar dgrs_ipaddr[4] = { 0xff, 0xff, 0xff, 0xff};
static uchar dgrs_iptrap[4] = { 0xff, 0xff, 0xff, 0xff};
static __u32 dgrs_ipxnet = -1;
static int dgrs_nicmode;
/*
* Private per-board data structure (dev->priv)
*/
typedef struct
{
/*
* Stuff for generic ethercard I/F
*/
struct net_device_stats stats;
/*
* DGRS specific data
*/
char *vmem;
struct bios_comm *bcomm; /* Firmware BIOS comm structure */
PORT *port; /* Ptr to PORT[0] struct in VM */
I596_SCB *scbp; /* Ptr to SCB struct in VM */
I596_RFD *rfdp; /* Current RFD list */
I596_RBD *rbdp; /* Current RBD list */
volatile int intrcnt; /* Count of interrupts */
/*
* SE-4 (EISA) board variables
*/
uchar is_reg; /* EISA: Value for ES4H_IS reg */
/*
* SE-6 (PCI) board variables
*
* The PLX "expansion rom" space is used for DMA register
* access from the host on the SE-6. These are the physical
* and virtual addresses of that space.
*/
ulong plxreg; /* Phys address of PLX chip */
char *vplxreg; /* Virtual address of PLX chip */
ulong plxdma; /* Phys addr of PLX "expansion rom" */
ulong volatile *vplxdma; /* Virtual addr of "expansion rom" */
int use_dma; /* Flag: use DMA */
DMACHAIN *dmadesc_s; /* area for DMA chains (SW addr.) */
DMACHAIN *dmadesc_h; /* area for DMA chains (Host Virtual) */
/*
* Multi-NIC mode variables
*
* All entries of the devtbl[] array are valid for the 0th
* device (i.e. eth0, but not eth1...eth5). devtbl[0] is
* valid for all devices (i.e. eth0, eth1, ..., eth5).
*/
int nports; /* Number of physical ports (4 or 6) */
int chan; /* Channel # (1-6) for this device */
struct net_device *devtbl[6]; /* Ptrs to N device structs */
} DGRS_PRIV;
/*
* reset or un-reset the IDT processor
*/
static void
proc_reset(struct net_device *dev0, int reset)
{
DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
if (priv0->plxreg)
{
ulong val;
val = inl(dev0->base_addr + PLX_MISC_CSR);
if (reset)
val |= SE6_RESET;
else
val &= ~SE6_RESET;
OUTL(dev0->base_addr + PLX_MISC_CSR, val);
}
else
{
OUTB(dev0->base_addr + ES4H_PC, reset ? ES4H_PC_RESET : 0);
}
}
/*
* See if the board supports bus master DMA
*/
static int
check_board_dma(struct net_device *dev0)
{
DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
ulong x;
/*
* If Space.c says not to use DMA, or if it's not a PLX based
* PCI board, or if the expansion ROM space is not PCI
* configured, then return false.
*/
if (!dgrs_dma || !priv0->plxreg || !priv0->plxdma)
return (0);
/*
* Set the local address remap register of the "expansion rom"
* area to 0x80000000 so that we can use it to access the DMA
* registers from the host side.
*/
OUTL(dev0->base_addr + PLX_ROM_BASE_ADDR, 0x80000000);
/*
* Set the PCI region descriptor to:
* Space 0:
* disable read-prefetch
* enable READY
* enable BURST
* 0 internal wait states
* Expansion ROM: (used for host DMA register access)
* disable read-prefetch
* enable READY
* disable BURST
* 0 internal wait states
*/
OUTL(dev0->base_addr + PLX_BUS_REGION, 0x49430343);
/*
* Now map the DMA registers into our virtual space
*/
priv0->vplxdma = (ulong *) ioremap (priv0->plxdma, 256);
if (!priv0->vplxdma)
{
printk("%s: can't *remap() the DMA regs\n", dev0->name);
return (0);
}
/*
* Now test to see if we can access the DMA registers
* If we write -1 and get back 1FFF, then we accessed the
* DMA register. Otherwise, we probably have an old board
* and wrote into regular RAM.
*/
priv0->vplxdma[PLX_DMA0_MODE/4] = 0xFFFFFFFF;
x = priv0->vplxdma[PLX_DMA0_MODE/4];
if (x != 0x00001FFF) {
iounmap((void *)priv0->vplxdma);
return (0);
}
return (1);
}
/*
* Initiate DMA using PLX part on PCI board. Spin the
* processor until completed. All addresses are physical!
*
* If pciaddr is NULL, then it's a chaining DMA, and lcladdr is
* the address of the first DMA descriptor in the chain.
*
* If pciaddr is not NULL, then it's a single DMA.
*
* In either case, "lcladdr" must have been fixed up to make
* sure the MSB isn't set using the S2DMA macro before passing
* the address to this routine.
*/
static int
do_plx_dma(
struct net_device *dev,
ulong pciaddr,
ulong lcladdr,
int len,
int to_host
)
{
int i;
ulong csr = 0;
DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
if (pciaddr)
{
/*
* Do a single, non-chain DMA
*/
priv->vplxdma[PLX_DMA0_PCI_ADDR/4] = pciaddr;
priv->vplxdma[PLX_DMA0_LCL_ADDR/4] = lcladdr;
priv->vplxdma[PLX_DMA0_SIZE/4] = len;
priv->vplxdma[PLX_DMA0_DESCRIPTOR/4] = to_host
? PLX_DMA_DESC_TO_HOST
: PLX_DMA_DESC_TO_BOARD;
priv->vplxdma[PLX_DMA0_MODE/4] =
PLX_DMA_MODE_WIDTH32
| PLX_DMA_MODE_WAITSTATES(0)
| PLX_DMA_MODE_READY
| PLX_DMA_MODE_NOBTERM
| PLX_DMA_MODE_BURST
| PLX_DMA_MODE_NOCHAIN;
}
else
{
/*
* Do a chaining DMA
*/
priv->vplxdma[PLX_DMA0_MODE/4] =
PLX_DMA_MODE_WIDTH32
| PLX_DMA_MODE_WAITSTATES(0)
| PLX_DMA_MODE_READY
| PLX_DMA_MODE_NOBTERM
| PLX_DMA_MODE_BURST
| PLX_DMA_MODE_CHAIN;
priv->vplxdma[PLX_DMA0_DESCRIPTOR/4] = lcladdr;
}
priv->vplxdma[PLX_DMA_CSR/4] =
PLX_DMA_CSR_0_ENABLE | PLX_DMA_CSR_0_START;
/*
* Wait for DMA to complete
*/
for (i = 0; i < 1000000; ++i)
{
/*
* Spin the host CPU for 1 usec, so we don't thrash
* the PCI bus while the PLX 9060 is doing DMA.
*/
udelay(1);
csr = (volatile unsigned long) priv->vplxdma[PLX_DMA_CSR/4];
if (csr & PLX_DMA_CSR_0_DONE)
break;
}
if ( ! (csr & PLX_DMA_CSR_0_DONE) )
{
printk("%s: DMA done never occurred. DMA disabled.\n",
dev->name);
priv->use_dma = 0;
return 1;
}
return 0;
}
/*
* dgrs_rcv_frame()
*
* Process a received frame. This is called from the interrupt
* routine, and works for both switch mode and multi-NIC mode.
*
* Note that when in multi-NIC mode, we want to always access the
* hardware using the dev and priv structures of the first port,
* so that we are using only one set of variables to maintain
* the board interface status, but we want to use the Nth port
* dev and priv structures to maintain statistics and to pass
* the packet up.
*
* Only the first device structure is attached to the interrupt.
* We use the special "chan" variable at the end of the first RBD
* to select the Nth device in multi-NIC mode.
*
* We currently do chained DMA on a per-packet basis when the
* packet is "long", and we spin the CPU a short time polling
* for DMA completion. This avoids a second interrupt overhead,
* and gives the best performance for light traffic to the host.
*
* However, a better scheme that could be implemented would be
* to see how many packets are outstanding for the host, and if
* the number is "large", create a long chain to DMA several
* packets into the host in one go. In this case, we would set
* up some state variables to let the host CPU continue doing
* other things until a DMA completion interrupt comes along.
*/
static void
dgrs_rcv_frame(
struct net_device *dev0,
DGRS_PRIV *priv0,
I596_CB *cbp
)
{
int len;
I596_TBD *tbdp;
struct sk_buff *skb;
uchar *putp;
uchar *p;
struct net_device *devN;
DGRS_PRIV *privN;
/*
* Determine Nth priv and dev structure pointers
*/
if (dgrs_nicmode)
{ /* Multi-NIC mode */
int chan = ((I596_RBD *) S2H(cbp->xmit.tbdp))->chan;
devN = priv0->devtbl[chan-1];
/*
* If devN is null, we got an interrupt before the I/F
* has been initialized. Pitch the packet.
*/
if (devN == NULL)
goto out;
privN = (DGRS_PRIV *) devN->priv;
}
else
{ /* Switch mode */
devN = dev0;
privN = priv0;
}
if (0) printk("%s: rcv len=%ld\n", devN->name, cbp->xmit.count);
/*
* Allocate a message block big enough to hold the whole frame
*/
len = cbp->xmit.count;
if ((skb = dev_alloc_skb(len+5)) == NULL)
{
printk("%s: dev_alloc_skb failed for rcv buffer\n", devN->name);
++privN->stats.rx_dropped;
/* discarding the frame */
goto out;
}
skb->dev = devN;
skb_reserve(skb, 2); /* Align IP header */
again:
putp = p = skb_put(skb, len);
/*
* There are three modes here for doing the packet copy.
* If we have DMA, and the packet is "long", we use the
* chaining mode of DMA. If it's shorter, we use single
* DMA's. Otherwise, we use memcpy().
*/
if (priv0->use_dma && priv0->dmadesc_h && len > 64)
{
/*
* If we can use DMA and it's a long frame, copy it using
* DMA chaining.
*/
DMACHAIN *ddp_h; /* Host virtual DMA desc. pointer */
DMACHAIN *ddp_s; /* Switch physical DMA desc. pointer */
uchar *phys_p;
/*
* Get the physical address of the STREAMS buffer.
* NOTE: allocb() guarantees that the whole buffer
* is in a single page if the length < 4096.
*/
phys_p = (uchar *) virt_to_phys(putp);
ddp_h = priv0->dmadesc_h;
ddp_s = priv0->dmadesc_s;
tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
for (;;)
{
int count;
int amt;
count = tbdp->count;
amt = count & 0x3fff;
if (amt == 0)
break; /* For safety */
if ( (p-putp) >= len)
{
printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
proc_reset(dev0, 1); /* Freeze IDT */
break; /* For Safety */
}
ddp_h->pciaddr = (ulong) phys_p;
ddp_h->lcladdr = S2DMA(tbdp->buf);
ddp_h->len = amt;
phys_p += amt;
p += amt;
if (count & I596_TBD_EOF)
{
ddp_h->next = PLX_DMA_DESC_TO_HOST
| PLX_DMA_DESC_EOC;
++ddp_h;
break;
}
else
{
++ddp_s;
ddp_h->next = PLX_DMA_DESC_TO_HOST
| (ulong) ddp_s;
tbdp = (I596_TBD *) S2H(tbdp->next);
++ddp_h;
}
}
if (ddp_h - priv0->dmadesc_h)
{
int rc;
rc = do_plx_dma(dev0,
0, (ulong) priv0->dmadesc_s, len, 0);
if (rc)
{
printk("%s: Chained DMA failure\n", devN->name);
goto again;
}
}
}
else if (priv0->use_dma)
{
/*
* If we can use DMA and it's a shorter frame, copy it
* using single DMA transfers.
*/
uchar *phys_p;
/*
* Get the physical address of the STREAMS buffer.
* NOTE: allocb() guarantees that the whole buffer
* is in a single page if the length < 4096.
*/
phys_p = (uchar *) virt_to_phys(putp);
tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
for (;;)
{
int count;
int amt;
int rc;
count = tbdp->count;
amt = count & 0x3fff;
if (amt == 0)
break; /* For safety */
if ( (p-putp) >= len)
{
printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
proc_reset(dev0, 1); /* Freeze IDT */
break; /* For Safety */
}
rc = do_plx_dma(dev0, (ulong) phys_p,
S2DMA(tbdp->buf), amt, 1);
if (rc)
{
memcpy(p, S2H(tbdp->buf), amt);
printk("%s: Single DMA failed\n", devN->name);
}
phys_p += amt;
p += amt;
if (count & I596_TBD_EOF)
break;
tbdp = (I596_TBD *) S2H(tbdp->next);
}
}
else
{
/*
* Otherwise, copy it piece by piece using memcpy()
*/
tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
for (;;)
{
int count;
int amt;
count = tbdp->count;
amt = count & 0x3fff;
if (amt == 0)
break; /* For safety */
if ( (p-putp) >= len)
{
printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
proc_reset(dev0, 1); /* Freeze IDT */
break; /* For Safety */
}
memcpy(p, S2H(tbdp->buf), amt);
p += amt;
if (count & I596_TBD_EOF)
break;
tbdp = (I596_TBD *) S2H(tbdp->next);
}
}
/*
* Pass the frame to upper half
*/
skb->protocol = eth_type_trans(skb, devN);
netif_rx(skb);
devN->last_rx = jiffies;
++privN->stats.rx_packets;
privN->stats.rx_bytes += len;
out:
cbp->xmit.status = I596_CB_STATUS_C | I596_CB_STATUS_OK;
}
/*
* Start transmission of a frame
*
* The interface to the board is simple: we pretend that we are
* a fifth 82596 ethernet controller 'receiving' data, and copy the
* data into the same structures that a real 82596 would. This way,
* the board firmware handles the host 'port' the same as any other.
*
* NOTE: we do not use Bus master DMA for this routine. Turns out
* that it is not needed. Slave writes over the PCI bus are about
* as fast as DMA, due to the fact that the PLX part can do burst
* writes. The same is not true for data being read from the board.
*
* For multi-NIC mode, we tell the firmware the desired 82596
* output port by setting the special "dstchan" member at the
* end of the traditional 82596 RFD structure.
*/
static int dgrs_start_xmit(struct sk_buff *skb, struct net_device *devN)
{
DGRS_PRIV *privN = (DGRS_PRIV *) devN->priv;
struct net_device *dev0;
DGRS_PRIV *priv0;
I596_RBD *rbdp;
int count;
int i, len, amt;
/*
* Determine 0th priv and dev structure pointers
*/
if (dgrs_nicmode)
{
dev0 = privN->devtbl[0];
priv0 = (DGRS_PRIV *) dev0->priv;
}
else
{
dev0 = devN;
priv0 = privN;
}
if (dgrs_debug > 1)
printk("%s: xmit len=%d\n", devN->name, (int) skb->len);
devN->trans_start = jiffies;
netif_start_queue(devN);
if (priv0->rfdp->cmd & I596_RFD_EL)
{ /* Out of RFD's */
if (0) printk("%s: NO RFD's\n", devN->name);
goto no_resources;
}
rbdp = priv0->rbdp;
count = 0;
priv0->rfdp->rbdp = (I596_RBD *) H2S(rbdp);
i = 0; len = skb->len;
for (;;)
{
if (rbdp->size & I596_RBD_EL)
{ /* Out of RBD's */
if (0) printk("%s: NO RBD's\n", devN->name);
goto no_resources;
}
amt = min_t(unsigned int, len, rbdp->size - count);
memcpy( (char *) S2H(rbdp->buf) + count, skb->data + i, amt);
i += amt;
count += amt;
len -= amt;
if (len == 0)
{
if (skb->len < 60)
rbdp->count = 60 | I596_RBD_EOF;
else
rbdp->count = count | I596_RBD_EOF;
rbdp = (I596_RBD *) S2H(rbdp->next);
goto frame_done;
}
else if (count < 32)
{
/* More data to come, but we used less than 32
* bytes of this RBD. Keep filling this RBD.
*/
{} /* Yes, we do nothing here */
}
else
{
rbdp->count = count;
rbdp = (I596_RBD *) S2H(rbdp->next);
count = 0;
}
}
frame_done:
priv0->rbdp = rbdp;
if (dgrs_nicmode)
priv0->rfdp->dstchan = privN->chan;
priv0->rfdp->status = I596_RFD_C | I596_RFD_OK;
priv0->rfdp = (I596_RFD *) S2H(priv0->rfdp->next);
++privN->stats.tx_packets;
dev_kfree_skb (skb);
return (0);
no_resources:
priv0->scbp->status |= I596_SCB_RNR; /* simulate I82596 */
return (-EAGAIN);
}
/*
* Open the interface
*/
static int
dgrs_open( struct net_device *dev )
{
netif_start_queue(dev);
return (0);
}
/*
* Close the interface
*/
static int dgrs_close( struct net_device *dev )
{
netif_stop_queue(dev);
return (0);
}
/*
* Get statistics
*/
static struct net_device_stats *dgrs_get_stats( struct net_device *dev )
{
DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
return (&priv->stats);
}
/*
* Set multicast list and/or promiscuous mode
*/
static void dgrs_set_multicast_list( struct net_device *dev)
{
DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
priv->port->is_promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
}
/*
* Unique ioctl's
*/
static int dgrs_ioctl(struct net_device *devN, struct ifreq *ifr, int cmd)
{
DGRS_PRIV *privN = (DGRS_PRIV *) devN->priv;
DGRS_IOCTL ioc;
int i;
if (cmd != DGRSIOCTL)
return -EINVAL;
if(copy_from_user(&ioc, ifr->ifr_data, sizeof(DGRS_IOCTL)))
return -EFAULT;
switch (ioc.cmd)
{
case DGRS_GETMEM:
if (ioc.len != sizeof(ulong))
return -EINVAL;
if(copy_to_user(ioc.data, &devN->mem_start, ioc.len))
return -EFAULT;
return (0);
case DGRS_SETFILTER:
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if (ioc.port > privN->bcomm->bc_nports)
return -EINVAL;
if (ioc.filter >= NFILTERS)
return -EINVAL;
if (ioc.len > privN->bcomm->bc_filter_area_len)
return -EINVAL;
/* Wait for old command to finish */
for (i = 0; i < 1000; ++i)
{
if ( (volatile long) privN->bcomm->bc_filter_cmd <= 0 )
break;
udelay(1);
}
if (i >= 1000)
return -EIO;
privN->bcomm->bc_filter_port = ioc.port;
privN->bcomm->bc_filter_num = ioc.filter;
privN->bcomm->bc_filter_len = ioc.len;
if (ioc.len)
{
if(copy_from_user(S2HN(privN->bcomm->bc_filter_area),
ioc.data, ioc.len))
return -EFAULT;
privN->bcomm->bc_filter_cmd = BC_FILTER_SET;
}
else
privN->bcomm->bc_filter_cmd = BC_FILTER_CLR;
return(0);
default:
return -EOPNOTSUPP;
}
}
/*
* Process interrupts
*
* dev, priv will always refer to the 0th device in Multi-NIC mode.
*/
static irqreturn_t dgrs_intr(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *dev0 = (struct net_device *) dev_id;
DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
I596_CB *cbp;
int cmd;
int i;
++priv0->intrcnt;
if (1) ++priv0->bcomm->bc_cnt[4];
if (0)
{
static int cnt = 100;
if (--cnt > 0)
printk("%s: interrupt: irq %d\n", dev0->name, irq);
}
/*
* Get 596 command
*/
cmd = priv0->scbp->cmd;
/*
* See if RU has been restarted
*/
if ( (cmd & I596_SCB_RUC) == I596_SCB_RUC_START)
{
if (0) printk("%s: RUC start\n", dev0->name);
priv0->rfdp = (I596_RFD *) S2H(priv0->scbp->rfdp);
priv0->rbdp = (I596_RBD *) S2H(priv0->rfdp->rbdp);
priv0->scbp->status &= ~(I596_SCB_RNR|I596_SCB_RUS);
/*
* Tell upper half (halves)
*/
if (dgrs_nicmode)
{
for (i = 0; i < priv0->nports; ++i)
netif_wake_queue (priv0->devtbl[i]);
}
else
netif_wake_queue (dev0);
/* if (bd->flags & TX_QUEUED)
DL_sched(bd, bdd); */
}
/*
* See if any CU commands to process
*/
if ( (cmd & I596_SCB_CUC) != I596_SCB_CUC_START)
{
priv0->scbp->cmd = 0; /* Ignore all other commands */
goto ack_intr;
}
priv0->scbp->status &= ~(I596_SCB_CNA|I596_SCB_CUS);
/*
* Process a command
*/
cbp = (I596_CB *) S2H(priv0->scbp->cbp);
priv0->scbp->cmd = 0; /* Safe to clear the command */
for (;;)
{
switch (cbp->nop.cmd & I596_CB_CMD)
{
case I596_CB_CMD_XMIT:
dgrs_rcv_frame(dev0, priv0, cbp);
break;
default:
cbp->nop.status = I596_CB_STATUS_C | I596_CB_STATUS_OK;
break;
}
if (cbp->nop.cmd & I596_CB_CMD_EL)
break;
cbp = (I596_CB *) S2H(cbp->nop.next);
}
priv0->scbp->status |= I596_SCB_CNA;
/*
* Ack the interrupt
*/
ack_intr:
if (priv0->plxreg)
OUTL(dev0->base_addr + PLX_LCL2PCI_DOORBELL, 1);
return IRQ_HANDLED;
}
/*
* Download the board firmware
*/
static int __init
dgrs_download(struct net_device *dev0)
{
DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
int is;
unsigned long i;
static int iv2is[16] = {
0, 0, 0, ES4H_IS_INT3,
0, ES4H_IS_INT5, 0, ES4H_IS_INT7,
0, 0, ES4H_IS_INT10, ES4H_IS_INT11,
ES4H_IS_INT12, 0, 0, ES4H_IS_INT15 };