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skge.h
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/*
* Definitions for the new Marvell Yukon / SysKonenct driver.
*/
#ifndef _SKGE_H
#define _SKGE_H
/* PCI config registers */
#define PCI_DEV_REG1 0x40
#define PCI_DEV_REG2 0x44
#define PCI_REV_DESC 0x4
#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
PCI_STATUS_SIG_SYSTEM_ERROR | \
PCI_STATUS_REC_MASTER_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_PARITY)
enum csr_regs {
B0_RAP = 0x0000,
B0_CTST = 0x0004,
B0_LED = 0x0006,
B0_POWER_CTRL = 0x0007,
B0_ISRC = 0x0008,
B0_IMSK = 0x000c,
B0_HWE_ISRC = 0x0010,
B0_HWE_IMSK = 0x0014,
B0_SP_ISRC = 0x0018,
B0_XM1_IMSK = 0x0020,
B0_XM1_ISRC = 0x0028,
B0_XM1_PHY_ADDR = 0x0030,
B0_XM1_PHY_DATA = 0x0034,
B0_XM2_IMSK = 0x0040,
B0_XM2_ISRC = 0x0048,
B0_XM2_PHY_ADDR = 0x0050,
B0_XM2_PHY_DATA = 0x0054,
B0_R1_CSR = 0x0060,
B0_R2_CSR = 0x0064,
B0_XS1_CSR = 0x0068,
B0_XA1_CSR = 0x006c,
B0_XS2_CSR = 0x0070,
B0_XA2_CSR = 0x0074,
B2_MAC_1 = 0x0100,
B2_MAC_2 = 0x0108,
B2_MAC_3 = 0x0110,
B2_CONN_TYP = 0x0118,
B2_PMD_TYP = 0x0119,
B2_MAC_CFG = 0x011a,
B2_CHIP_ID = 0x011b,
B2_E_0 = 0x011c,
B2_E_1 = 0x011d,
B2_E_2 = 0x011e,
B2_E_3 = 0x011f,
B2_FAR = 0x0120,
B2_FDP = 0x0124,
B2_LD_CTRL = 0x0128,
B2_LD_TEST = 0x0129,
B2_TI_INI = 0x0130,
B2_TI_VAL = 0x0134,
B2_TI_CTRL = 0x0138,
B2_TI_TEST = 0x0139,
B2_IRQM_INI = 0x0140,
B2_IRQM_VAL = 0x0144,
B2_IRQM_CTRL = 0x0148,
B2_IRQM_TEST = 0x0149,
B2_IRQM_MSK = 0x014c,
B2_IRQM_HWE_MSK = 0x0150,
B2_TST_CTRL1 = 0x0158,
B2_TST_CTRL2 = 0x0159,
B2_GP_IO = 0x015c,
B2_I2C_CTRL = 0x0160,
B2_I2C_DATA = 0x0164,
B2_I2C_IRQ = 0x0168,
B2_I2C_SW = 0x016c,
B2_BSC_INI = 0x0170,
B2_BSC_VAL = 0x0174,
B2_BSC_CTRL = 0x0178,
B2_BSC_STAT = 0x0179,
B2_BSC_TST = 0x017a,
B3_RAM_ADDR = 0x0180,
B3_RAM_DATA_LO = 0x0184,
B3_RAM_DATA_HI = 0x0188,
B3_RI_WTO_R1 = 0x0190,
B3_RI_WTO_XA1 = 0x0191,
B3_RI_WTO_XS1 = 0x0192,
B3_RI_RTO_R1 = 0x0193,
B3_RI_RTO_XA1 = 0x0194,
B3_RI_RTO_XS1 = 0x0195,
B3_RI_WTO_R2 = 0x0196,
B3_RI_WTO_XA2 = 0x0197,
B3_RI_WTO_XS2 = 0x0198,
B3_RI_RTO_R2 = 0x0199,
B3_RI_RTO_XA2 = 0x019a,
B3_RI_RTO_XS2 = 0x019b,
B3_RI_TO_VAL = 0x019c,
B3_RI_CTRL = 0x01a0,
B3_RI_TEST = 0x01a2,
B3_MA_TOINI_RX1 = 0x01b0,
B3_MA_TOINI_RX2 = 0x01b1,
B3_MA_TOINI_TX1 = 0x01b2,
B3_MA_TOINI_TX2 = 0x01b3,
B3_MA_TOVAL_RX1 = 0x01b4,
B3_MA_TOVAL_RX2 = 0x01b5,
B3_MA_TOVAL_TX1 = 0x01b6,
B3_MA_TOVAL_TX2 = 0x01b7,
B3_MA_TO_CTRL = 0x01b8,
B3_MA_TO_TEST = 0x01ba,
B3_MA_RCINI_RX1 = 0x01c0,
B3_MA_RCINI_RX2 = 0x01c1,
B3_MA_RCINI_TX1 = 0x01c2,
B3_MA_RCINI_TX2 = 0x01c3,
B3_MA_RCVAL_RX1 = 0x01c4,
B3_MA_RCVAL_RX2 = 0x01c5,
B3_MA_RCVAL_TX1 = 0x01c6,
B3_MA_RCVAL_TX2 = 0x01c7,
B3_MA_RC_CTRL = 0x01c8,
B3_MA_RC_TEST = 0x01ca,
B3_PA_TOINI_RX1 = 0x01d0,
B3_PA_TOINI_RX2 = 0x01d4,
B3_PA_TOINI_TX1 = 0x01d8,
B3_PA_TOINI_TX2 = 0x01dc,
B3_PA_TOVAL_RX1 = 0x01e0,
B3_PA_TOVAL_RX2 = 0x01e4,
B3_PA_TOVAL_TX1 = 0x01e8,
B3_PA_TOVAL_TX2 = 0x01ec,
B3_PA_CTRL = 0x01f0,
B3_PA_TEST = 0x01f2,
};
/* B0_CTST 16 bit Control/Status register */
enum {
CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
CS_STOP_DONE = 1<<5, /* Stop Master is finished */
CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
CS_MRST_CLR = 1<<3, /* Clear Master reset */
CS_MRST_SET = 1<<2, /* Set Master reset */
CS_RST_CLR = 1<<1, /* Clear Software reset */
CS_RST_SET = 1, /* Set Software reset */
/* B0_LED 8 Bit LED register */
/* Bit 7.. 2: reserved */
LED_STAT_ON = 1<<1, /* Status LED on */
LED_STAT_OFF = 1, /* Status LED off */
/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
PC_VAUX_ON = 1<<3, /* Switch VAUX On */
PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
PC_VCC_ON = 1<<1, /* Switch VCC On */
PC_VCC_OFF = 1<<0, /* Switch VCC Off */
};
/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
enum {
IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
IS_HW_ERR = 1<<31, /* Interrupt HW Error */
/* Bit 30: reserved */
IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
IS_IRQ_SW = 1<<24, /* SW forced IRQ */
IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
/* IRQ from PHY (YUKON only) */
IS_TIMINT = 1<<22, /* IRQ from Timer */
IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
/* Receive Queue 1 */
IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
IS_R1_F = 1<<16, /* Q_R1 End of Frame */
IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
/* Receive Queue 2 */
IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
IS_R2_F = 1<<13, /* Q_R2 End of Frame */
IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
/* Synchronous Transmit Queue 1 */
IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
/* Asynchronous Transmit Queue 1 */
IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
/* Synchronous Transmit Queue 2 */
IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
/* Asynchronous Transmit Queue 2 */
IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
};
/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
enum {
IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
IS_IRQ_STAT = 1<<10, /* IRQ status exception */
IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
| IS_NO_STAT_M1 | IS_NO_STAT_M2
| IS_RAM_RD_PAR | IS_RAM_WR_PAR
| IS_M1_PAR_ERR | IS_M2_PAR_ERR
| IS_R1_PAR_ERR | IS_R2_PAR_ERR,
};
/* B2_TST_CTRL1 8 bit Test Control Register 1 */
enum {
TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
};
/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
enum {
CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
/* Bit 3.. 2: reserved */
CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
};
/* B2_CHIP_ID 8 bit Chip Identification Number */
enum {
CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
};
/* B2_TI_CTRL 8 bit Timer control */
/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
enum {
TIM_START = 1<<2, /* Start Timer */
TIM_STOP = 1<<1, /* Stop Timer */
TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
};
/* B2_TI_TEST 8 Bit Timer Test */
/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
enum {
TIM_T_ON = 1<<2, /* Test mode on */
TIM_T_OFF = 1<<1, /* Test mode off */
TIM_T_STEP = 1<<0, /* Test step */
};
/* B2_GP_IO 32 bit General Purpose I/O Register */
enum {
GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
GP_IO_9 = 1<<9, /* IO_9 pin */
GP_IO_8 = 1<<8, /* IO_8 pin */
GP_IO_7 = 1<<7, /* IO_7 pin */
GP_IO_6 = 1<<6, /* IO_6 pin */
GP_IO_5 = 1<<5, /* IO_5 pin */
GP_IO_4 = 1<<4, /* IO_4 pin */
GP_IO_3 = 1<<3, /* IO_3 pin */
GP_IO_2 = 1<<2, /* IO_2 pin */
GP_IO_1 = 1<<1, /* IO_1 pin */
GP_IO_0 = 1<<0, /* IO_0 pin */
};
/* Descriptor Bit Definition */
/* TxCtrl Transmit Buffer Control Field */
/* RxCtrl Receive Buffer Control Field */
enum {
BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
BMU_STF = 1<<30, /* Start of Frame */
BMU_EOF = 1<<29, /* End of Frame */
BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
/* TxCtrl specific bits */
BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
/* RxCtrl specific bits */
BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
/* Bit 23..16: BMU Check Opcodes */
BMU_CHECK = 0x55<<16, /* Default BMU check */
BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
};
/* B2_BSC_CTRL 8 bit Blink Source Counter Control */
enum {
BSC_START = 1<<1, /* Start Blink Source Counter */
BSC_STOP = 1<<0, /* Stop Blink Source Counter */
};
/* B2_BSC_STAT 8 bit Blink Source Counter Status */
enum {
BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
};
/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
enum {
BSC_T_ON = 1<<2, /* Test mode on */
BSC_T_OFF = 1<<1, /* Test mode off */
BSC_T_STEP = 1<<0, /* Test step */
};
/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
/* Bit 31..19: reserved */
#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
/* RAM Interface Registers */
/* B3_RI_CTRL 16 bit RAM Iface Control Register */
enum {
RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
};
/* MAC Arbiter Registers */
/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
enum {
MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
};
/* Timeout values */
#define SK_MAC_TO_53 72 /* MAC arbiter timeout */
#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
#define SK_PKT_TO_MAX 0xffff /* Maximum value */
#define SK_RI_TO_53 36 /* RAM interface timeout */
/* Packet Arbiter Registers */
/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
enum {
PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */
PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */
PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */
PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */
PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
};
#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
/* TXA_CTRL 8 bit Tx Arbiter Control Register */
enum {
TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
TXA_START_RC = 1<<3, /* Start sync Rate Control */
TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
};
/*
* Bank 4 - 5
*/
/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
enum {
TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
};
enum {
B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
};
/* Queue Register Offsets, use Q_ADDR() to access */
enum {
B8_Q_REGS = 0x0400, /* base of Queue registers */
Q_D = 0x00, /* 8*32 bit Current Descriptor */
Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
Q_BC = 0x30, /* 32 bit Current Byte Counter */
Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
Q_F = 0x38, /* 32 bit Flag Register */
Q_T1 = 0x3c, /* 32 bit Test Register 1 */
Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
Q_T2 = 0x40, /* 32 bit Test Register 2 */
Q_T3 = 0x44, /* 32 bit Test Register 3 */
/* Yukon-2 */
Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
Q_WM = 0x40, /* 16 bit FIFO Watermark */
Q_AL = 0x42, /* 8 bit FIFO Alignment */
Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
Q_RL = 0x4a, /* 8 bit FIFO Read Level */
Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
Q_WL = 0x4e, /* 8 bit FIFO Write Level */
Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
};
#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
/* RAM Buffer Register Offsets */
enum {
RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
RB_END = 0x04,/* 32 bit RAM Buffer End Address */
RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
/* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
};
/* Receive and Transmit Queues */
enum {
Q_R1 = 0x0000, /* Receive Queue 1 */
Q_R2 = 0x0080, /* Receive Queue 2 */
Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
};
/* Different MAC Types */
enum {
SK_MAC_XMAC = 0, /* Xaqti XMAC II */
SK_MAC_GMAC = 1, /* Marvell GMAC */
};
/* Different PHY Types */
enum {
SK_PHY_XMAC = 0,/* integrated in XMAC II */
SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
SK_PHY_NAT = 3,/* National DP83891 [not supported] */
SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
};
/* PHY addresses (bits 12..8 of PHY address reg) */
enum {
PHY_ADDR_XMAC = 0<<8,
PHY_ADDR_BCOM = 1<<8,
/* GPHY address (bits 15..11 of SMI control reg) */
PHY_ADDR_MARV = 0,
};
#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
enum {
RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
};
/* Receive and Transmit MAC FIFO Registers (GENESIS only) */
/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
enum {
MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
};
/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
enum {
MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
/* Bit 14: reserved */
MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
};
#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
enum {
MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
MFF_PC_INC = 1<<0, /* Packet Counter Increment */
};
/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
enum {
MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
MFF_WP_INC = 1<<4, /* Write Pointer Increm */
MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
};
/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
enum {
MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
};
/* Link LED Counter Registers (GENESIS only) */
/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
enum {
LED_START = 1<<2, /* Start Timer */
LED_STOP = 1<<1, /* Stop Timer */
LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
};
/* RX_LED_TST 8 bit Receive LED Cnt Test Register */
/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
enum {
LED_T_ON = 1<<2, /* LED Counter Test mode On */
LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
LED_T_STEP = 1<<0, /* LED Counter Step */
};
/* LNK_LED_REG 8 bit Link LED Register */
enum {
LED_BLK_ON = 1<<5, /* Link LED Blinking On */
LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
LED_ON = 1<<1, /* switch LED on */
LED_OFF = 1<<0, /* switch LED off */
};
/* Receive GMAC FIFO (YUKON and Yukon-2) */
enum {
RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
};
/* TXA_TEST 8 bit Tx Arbiter Test Register */
enum {
TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
};
/* TXA_STAT 8 bit Tx Arbiter Status Register */
enum {
TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
};
/* Q_BC 32 bit Current Byte Counter */
/* BMU Control Status Registers */
/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
/* Q_CSR 32 bit BMU Control/Status Register */
enum {
CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
CSR_HPI_RUN = 1<<17, /* Release HPI SM */
CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
CSR_START = 1<<4, /* Start Rx/Tx Queue */
CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
};
#define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
CSR_TRANS_RST)
#define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
CSR_TRANS_RUN)
/* Q_F 32 bit Flag Register */
enum {
F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
F_WM_REACHED = 1<<25, /* Watermark reached */
F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
};
/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
/* RB_START 32 bit RAM Buffer Start Address */
/* RB_END 32 bit RAM Buffer End Address */
/* RB_WP 32 bit RAM Buffer Write Pointer */
/* RB_RP 32 bit RAM Buffer Read Pointer */
/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
/* RB_PC 32 bit RAM Buffer Packet Counter */
/* RB_LEV 32 bit RAM Buffer Level Register */
#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
/* RB_TST2 8 bit RAM Buffer Test Register 2 */
/* RB_TST1 8 bit RAM Buffer Test Register 1 */
/* RB_CTRL 8 bit RAM Buffer Control Register */
enum {
RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
};
/* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
enum {
TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
};
/* Counter and Timer constants, for a host clock of 62.5 MHz */
#define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
#define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
#define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
/* 215 ms at 78.12 MHz */
#define SK_FACT_62 100 /* is given in percent */
#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
#define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
/* Transmit GMAC FIFO (YUKON only) */
enum {
TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
/* Descriptor Poll Timer Registers */
B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
/* Time Stamp Timer Registers (YUKON only) */
GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
};
/* Status BMU Registers (Yukon-2 only)*/
enum {
STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
/* 0x0e85 - 0x0e86: reserved */
STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */
STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */
STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
/* FIFO Control/Status Registers (Yukon-2 only)*/
STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
/* Level and ISR Timer Registers (Yukon-2 only)*/
STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */
STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */
STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */
STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */
STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */
ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
};
enum {
LINKLED_OFF = 0x01,
LINKLED_ON = 0x02,
LINKLED_LINKSYNC_OFF = 0x04,
LINKLED_LINKSYNC_ON = 0x08,
LINKLED_BLINK_OFF = 0x10,
LINKLED_BLINK_ON = 0x20,
};
/* GMAC and GPHY Control Registers (YUKON only) */
enum {
GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
/* WOL Pattern Length Registers (YUKON only) */
WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
/* WOL Pattern Counter Registers (YUKON only) */
WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
};
enum {
WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
};
enum {
BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
};
/*
* Receive Frame Status Encoding
*/
enum {
XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
XMR_FS_LEN_SHIFT = 18,
XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
/*
* XMR_FS_ERR will be set if
* XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
* XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
* is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
* XMR_FS_ERR unless the corresponding bit in the Receive Command
* Register is set.
*/
};
/*
,* XMAC-PHY Registers, indirect addressed over the XMAC
*/
enum {
PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */