forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathvia-rhine.c
2063 lines (1705 loc) · 57.2 KB
/
via-rhine.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
/*
Written 1998-2001 by Donald Becker.
Current Maintainer: Roger Luethi <[email protected]>
This software may be used and distributed according to the terms of
the GNU General Public License (GPL), incorporated herein by reference.
Drivers based on or derived from this code fall under the GPL and must
retain the authorship, copyright and license notice. This file is not
a complete program and may only be used when the entire operating
system is licensed under the GPL.
This driver is designed for the VIA VT86C100A Rhine-I.
It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
and management NIC 6105M).
The author may be reached as [email protected], or C/O
Scyld Computing Corporation
410 Severn Ave., Suite 210
Annapolis MD 21403
This driver contains some changes from the original Donald Becker
version. He may or may not be interested in bug reports on this
code. You can find his versions at:
http://www.scyld.com/network/via-rhine.html
Linux kernel version history:
LK1.1.0:
- Jeff Garzik: softnet 'n stuff
LK1.1.1:
- Justin Guyett: softnet and locking fixes
- Jeff Garzik: use PCI interface
LK1.1.2:
- Urban Widmark: minor cleanups, merges from Becker 1.03a/1.04 versions
LK1.1.3:
- Urban Widmark: use PCI DMA interface (with thanks to the eepro100.c
code) update "Theory of Operation" with
softnet/locking changes
- Dave Miller: PCI DMA and endian fixups
- Jeff Garzik: MOD_xxx race fixes, updated PCI resource allocation
LK1.1.4:
- Urban Widmark: fix gcc 2.95.2 problem and
remove writel's to fixed address 0x7c
LK1.1.5:
- Urban Widmark: mdio locking, bounce buffer changes
merges from Beckers 1.05 version
added netif_running_on/off support
LK1.1.6:
- Urban Widmark: merges from Beckers 1.08b version (VT6102 + mdio)
set netif_running_on/off on startup, del_timer_sync
LK1.1.7:
- Manfred Spraul: added reset into tx_timeout
LK1.1.9:
- Urban Widmark: merges from Beckers 1.10 version
(media selection + eeprom reload)
- David Vrabel: merges from D-Link "1.11" version
(disable WOL and PME on startup)
LK1.1.10:
- Manfred Spraul: use "singlecopy" for unaligned buffers
don't allocate bounce buffers for !ReqTxAlign cards
LK1.1.11:
- David Woodhouse: Set dev->base_addr before the first time we call
wait_for_reset(). It's a lot happier that way.
Free np->tx_bufs only if we actually allocated it.
LK1.1.12:
- Martin Eriksson: Allow Memory-Mapped IO to be enabled.
LK1.1.13 (jgarzik):
- Add ethtool support
- Replace some MII-related magic numbers with constants
LK1.1.14 (Ivan G.):
- fixes comments for Rhine-III
- removes W_MAX_TIMEOUT (unused)
- adds HasDavicomPhy for Rhine-I (basis: linuxfet driver; my card
is R-I and has Davicom chip, flag is referenced in kernel driver)
- sends chip_id as a parameter to wait_for_reset since np is not
initialized on first call
- changes mmio "else if (chip_id==VT6102)" to "else" so it will work
for Rhine-III's (documentation says same bit is correct)
- transmit frame queue message is off by one - fixed
- adds IntrNormalSummary to "Something Wicked" exclusion list
so normal interrupts will not trigger the message (src: Donald Becker)
(Roger Luethi)
- show confused chip where to continue after Tx error
- location of collision counter is chip specific
- allow selecting backoff algorithm (module parameter)
LK1.1.15 (jgarzik):
- Use new MII lib helper generic_mii_ioctl
LK1.1.16 (Roger Luethi)
- Etherleak fix
- Handle Tx buffer underrun
- Fix bugs in full duplex handling
- New reset code uses "force reset" cmd on Rhine-II
- Various clean ups
LK1.1.17 (Roger Luethi)
- Fix race in via_rhine_start_tx()
- On errors, wait for Tx engine to turn off before scavenging
- Handle Tx descriptor write-back race on Rhine-II
- Force flushing for PCI posted writes
- More reset code changes
LK1.1.18 (Roger Luethi)
- No filtering multicast in promisc mode (Edward Peng)
- Fix for Rhine-I Tx timeouts
LK1.1.19 (Roger Luethi)
- Increase Tx threshold for unspecified errors
LK1.2.0-2.6 (Roger Luethi)
- Massive clean-up
- Rewrite PHY, media handling (remove options, full_duplex, backoff)
- Fix Tx engine race for good
*/
#define DRV_NAME "via-rhine"
#define DRV_VERSION "1.2.0-2.6"
#define DRV_RELDATE "June-10-2004"
/* A few user-configurable values.
These may be modified when a driver module is loaded. */
static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
static int max_interrupt_work = 20;
/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
Setting to > 1518 effectively disables this feature. */
static int rx_copybreak;
/*
* In case you are looking for 'options[]' or 'full_duplex[]', they
* are gone. Use ethtool(8) instead.
*/
/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
The Rhine has a 64 element 8390-like hash table. */
static const int multicast_filter_limit = 32;
/* Operational parameters that are set at compile time. */
/* Keep the ring sizes a power of two for compile efficiency.
The compiler will convert <unsigned>'%'<2^N> into a bit mask.
Making the Tx ring too large decreases the effectiveness of channel
bonding and packet priority.
There are no ill effects from too-large receive rings. */
#define TX_RING_SIZE 16
#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
#define RX_RING_SIZE 16
/* Operational parameters that usually are not changed. */
/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT (2*HZ)
#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/crc32.h>
#include <linux/bitops.h>
#include <asm/processor.h> /* Processor type for cache alignment. */
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
/* These identify the driver base version and may not be removed. */
static char version[] __devinitdata =
KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
/* This driver was written to use PCI memory space. Some early versions
of the Rhine may only work correctly with I/O space accesses. */
#ifdef CONFIG_VIA_RHINE_MMIO
#define USE_MMIO
#else
#endif
MODULE_AUTHOR("Donald Becker <[email protected]>");
MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
MODULE_LICENSE("GPL");
module_param(max_interrupt_work, int, 0);
module_param(debug, int, 0);
module_param(rx_copybreak, int, 0);
MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
/*
Theory of Operation
I. Board Compatibility
This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
controller.
II. Board-specific settings
Boards with this chip are functional only in a bus-master PCI slot.
Many operational settings are loaded from the EEPROM to the Config word at
offset 0x78. For most of these settings, this driver assumes that they are
correct.
If this driver is compiled to use PCI memory space operations the EEPROM
must be configured to enable memory ops.
III. Driver operation
IIIa. Ring buffers
This driver uses two statically allocated fixed-size descriptor lists
formed into rings by a branch from the final descriptor to the beginning of
the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
IIIb/c. Transmit/Receive Structure
This driver attempts to use a zero-copy receive and transmit scheme.
Alas, all data buffers are required to start on a 32 bit boundary, so
the driver must often copy transmit packets into bounce buffers.
The driver allocates full frame size skbuffs for the Rx ring buffers at
open() time and passes the skb->data field to the chip as receive data
buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
a fresh skbuff is allocated and the frame is copied to the new skbuff.
When the incoming frame is larger, the skbuff is passed directly up the
protocol stack. Buffers consumed this way are replaced by newly allocated
skbuffs in the last phase of rhine_rx().
The RX_COPYBREAK value is chosen to trade-off the memory wasted by
using a full-sized skbuff for small frames vs. the copying costs of larger
frames. New boards are typically used in generously configured machines
and the underfilled buffers have negligible impact compared to the benefit of
a single allocation size, so the default value of zero results in never
copying packets. When copying is done, the cost is usually mitigated by using
a combined copy/checksum routine. Copying also preloads the cache, which is
most useful with small frames.
Since the VIA chips are only able to transfer data to buffers on 32 bit
boundaries, the IP header at offset 14 in an ethernet frame isn't
longword aligned for further processing. Copying these unaligned buffers
has the beneficial effect of 16-byte aligning the IP header.
IIId. Synchronization
The driver runs as two independent, single-threaded flows of control. One
is the send-packet routine, which enforces single-threaded use by the
dev->priv->lock spinlock. The other thread is the interrupt handler, which
is single threaded by the hardware and interrupt handling software.
The send packet thread has partial control over the Tx ring. It locks the
dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
is not available it stops the transmit queue by calling netif_stop_queue.
The interrupt handler has exclusive control over the Rx ring and records stats
from the Tx ring. After reaping the stats, it marks the Tx queue entry as
empty by incrementing the dirty_tx mark. If at least half of the entries in
the Rx ring are available the transmit queue is woken up if it was stopped.
IV. Notes
IVb. References
Preliminary VT86C100A manual from http://www.via.com.tw/
http://www.scyld.com/expert/100mbps.html
http://www.scyld.com/expert/NWay.html
ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
IVc. Errata
The VT86C100A manual is not reliable information.
The 3043 chip does not handle unaligned transmit or receive buffers, resulting
in significant performance degradation for bounce buffer copies on transmit
and unaligned IP headers on receive.
The chip does not pad to minimum transmit length.
*/
/* This table drives the PCI probe routines. It's mostly boilerplate in all
of the drivers, and will likely be provided by some future kernel.
Note the matching code -- the first table entry matchs all 56** cards but
second only the 1234 card.
*/
enum rhine_revs {
VT86C100A = 0x00,
VTunknown0 = 0x20,
VT6102 = 0x40,
VT8231 = 0x50, /* Integrated MAC */
VT8233 = 0x60, /* Integrated MAC */
VT8235 = 0x74, /* Integrated MAC */
VT8237 = 0x78, /* Integrated MAC */
VTunknown1 = 0x7C,
VT6105 = 0x80,
VT6105_B0 = 0x83,
VT6105L = 0x8A,
VT6107 = 0x8C,
VTunknown2 = 0x8E,
VT6105M = 0x90, /* Management adapter */
};
enum rhine_quirks {
rqWOL = 0x0001, /* Wake-On-LAN support */
rqForceReset = 0x0002,
rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
rqRhineI = 0x0100, /* See comment below */
};
/*
* rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
* MMIO as well as for the collision counter and the Tx FIFO underflow
* indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
*/
/* Beware of PCI posted writes */
#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
static struct pci_device_id rhine_pci_tbl[] =
{
{0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT86C100A */
{0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6102 */
{0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* 6105{,L,LOM} */
{0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6105M */
{ } /* terminate list */
};
MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
/* Offsets to the device registers. */
enum register_offsets {
StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
ChipCmd1=0x09,
IntrStatus=0x0C, IntrEnable=0x0E,
MulticastFilter0=0x10, MulticastFilter1=0x14,
RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
StickyHW=0x83, IntrStatus2=0x84,
WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
WOLcrClr1=0xA6, WOLcgClr=0xA7,
PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
};
/* Bits in ConfigD */
enum backoff_bits {
BackOptional=0x01, BackModify=0x02,
BackCaptureEffect=0x04, BackRandom=0x08
};
#ifdef USE_MMIO
/* Registers we check that mmio and reg are the same. */
static const int mmio_verify_registers[] = {
RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
0
};
#endif
/* Bits in the interrupt status/mask registers. */
enum intr_status_bits {
IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
IntrPCIErr=0x0040,
IntrStatsMax=0x0080, IntrRxEarly=0x0100,
IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
IntrTxAborted=0x2000, IntrLinkChange=0x4000,
IntrRxWakeUp=0x8000,
IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
IntrTxErrSummary=0x082218,
};
/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
enum wol_bits {
WOLucast = 0x10,
WOLmagic = 0x20,
WOLbmcast = 0x30,
WOLlnkon = 0x40,
WOLlnkoff = 0x80,
};
/* The Rx and Tx buffer descriptors. */
struct rx_desc {
s32 rx_status;
u32 desc_length; /* Chain flag, Buffer/frame length */
u32 addr;
u32 next_desc;
};
struct tx_desc {
s32 tx_status;
u32 desc_length; /* Chain flag, Tx Config, Frame length */
u32 addr;
u32 next_desc;
};
/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
#define TXDESC 0x00e08000
enum rx_status_bits {
RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
};
/* Bits in *_desc.*_status */
enum desc_status_bits {
DescOwn=0x80000000
};
/* Bits in ChipCmd. */
enum chip_cmd_bits {
CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
};
struct rhine_private {
/* Descriptor rings */
struct rx_desc *rx_ring;
struct tx_desc *tx_ring;
dma_addr_t rx_ring_dma;
dma_addr_t tx_ring_dma;
/* The addresses of receive-in-place skbuffs. */
struct sk_buff *rx_skbuff[RX_RING_SIZE];
dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
/* The saved address of a sent-in-place packet/buffer, for later free(). */
struct sk_buff *tx_skbuff[TX_RING_SIZE];
dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
/* Tx bounce buffers */
unsigned char *tx_buf[TX_RING_SIZE];
unsigned char *tx_bufs;
dma_addr_t tx_bufs_dma;
struct pci_dev *pdev;
long pioaddr;
struct net_device_stats stats;
spinlock_t lock;
/* Frequently used values: keep some adjacent for cache effect. */
u32 quirks;
struct rx_desc *rx_head_desc;
unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
unsigned int cur_tx, dirty_tx;
unsigned int rx_buf_sz; /* Based on MTU+slack. */
u8 wolopts;
u8 tx_thresh, rx_thresh;
struct mii_if_info mii_if;
struct work_struct tx_timeout_task;
struct work_struct check_media_task;
void __iomem *base;
};
static int mdio_read(struct net_device *dev, int phy_id, int location);
static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
static int rhine_open(struct net_device *dev);
static void rhine_tx_timeout(struct net_device *dev);
static void rhine_tx_timeout_task(struct net_device *dev);
static void rhine_check_media_task(struct net_device *dev);
static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
static void rhine_tx(struct net_device *dev);
static void rhine_rx(struct net_device *dev);
static void rhine_error(struct net_device *dev, int intr_status);
static void rhine_set_rx_mode(struct net_device *dev);
static struct net_device_stats *rhine_get_stats(struct net_device *dev);
static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
static struct ethtool_ops netdev_ethtool_ops;
static int rhine_close(struct net_device *dev);
static void rhine_shutdown (struct pci_dev *pdev);
#define RHINE_WAIT_FOR(condition) do { \
int i=1024; \
while (!(condition) && --i) \
; \
if (debug > 1 && i < 512) \
printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
DRV_NAME, 1024-i, __func__, __LINE__); \
} while(0)
static inline u32 get_intr_status(struct net_device *dev)
{
struct rhine_private *rp = netdev_priv(dev);
void __iomem *ioaddr = rp->base;
u32 intr_status;
intr_status = ioread16(ioaddr + IntrStatus);
/* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
if (rp->quirks & rqStatusWBRace)
intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
return intr_status;
}
/*
* Get power related registers into sane state.
* Notify user about past WOL event.
*/
static void rhine_power_init(struct net_device *dev)
{
struct rhine_private *rp = netdev_priv(dev);
void __iomem *ioaddr = rp->base;
u16 wolstat;
if (rp->quirks & rqWOL) {
/* Make sure chip is in power state D0 */
iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
/* Disable "force PME-enable" */
iowrite8(0x80, ioaddr + WOLcgClr);
/* Clear power-event config bits (WOL) */
iowrite8(0xFF, ioaddr + WOLcrClr);
/* More recent cards can manage two additional patterns */
if (rp->quirks & rq6patterns)
iowrite8(0x03, ioaddr + WOLcrClr1);
/* Save power-event status bits */
wolstat = ioread8(ioaddr + PwrcsrSet);
if (rp->quirks & rq6patterns)
wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
/* Clear power-event status bits */
iowrite8(0xFF, ioaddr + PwrcsrClr);
if (rp->quirks & rq6patterns)
iowrite8(0x03, ioaddr + PwrcsrClr1);
if (wolstat) {
char *reason;
switch (wolstat) {
case WOLmagic:
reason = "Magic packet";
break;
case WOLlnkon:
reason = "Link went up";
break;
case WOLlnkoff:
reason = "Link went down";
break;
case WOLucast:
reason = "Unicast packet";
break;
case WOLbmcast:
reason = "Multicast/broadcast packet";
break;
default:
reason = "Unknown";
}
printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
DRV_NAME, reason);
}
}
}
static void rhine_chip_reset(struct net_device *dev)
{
struct rhine_private *rp = netdev_priv(dev);
void __iomem *ioaddr = rp->base;
iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
IOSYNC;
if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
printk(KERN_INFO "%s: Reset not complete yet. "
"Trying harder.\n", DRV_NAME);
/* Force reset */
if (rp->quirks & rqForceReset)
iowrite8(0x40, ioaddr + MiscCmd);
/* Reset can take somewhat longer (rare) */
RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
}
if (debug > 1)
printk(KERN_INFO "%s: Reset %s.\n", dev->name,
(ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
"failed" : "succeeded");
}
#ifdef USE_MMIO
static void enable_mmio(long pioaddr, u32 quirks)
{
int n;
if (quirks & rqRhineI) {
/* More recent docs say that this bit is reserved ... */
n = inb(pioaddr + ConfigA) | 0x20;
outb(n, pioaddr + ConfigA);
} else {
n = inb(pioaddr + ConfigD) | 0x80;
outb(n, pioaddr + ConfigD);
}
}
#endif
/*
* Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
* (plus 0x6C for Rhine-I/II)
*/
static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
{
struct rhine_private *rp = netdev_priv(dev);
void __iomem *ioaddr = rp->base;
outb(0x20, pioaddr + MACRegEEcsr);
RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
#ifdef USE_MMIO
/*
* Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
* MMIO. If reloading EEPROM was done first this could be avoided, but
* it is not known if that still works with the "win98-reboot" problem.
*/
enable_mmio(pioaddr, rp->quirks);
#endif
/* Turn off EEPROM-controlled wake-up (magic packet) */
if (rp->quirks & rqWOL)
iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
}
#ifdef CONFIG_NET_POLL_CONTROLLER
static void rhine_poll(struct net_device *dev)
{
disable_irq(dev->irq);
rhine_interrupt(dev->irq, (void *)dev, NULL);
enable_irq(dev->irq);
}
#endif
static void rhine_hw_init(struct net_device *dev, long pioaddr)
{
struct rhine_private *rp = netdev_priv(dev);
/* Reset the chip to erase previous misconfiguration. */
rhine_chip_reset(dev);
/* Rhine-I needs extra time to recuperate before EEPROM reload */
if (rp->quirks & rqRhineI)
msleep(5);
/* Reload EEPROM controlled bytes cleared by soft reset */
rhine_reload_eeprom(pioaddr, dev);
}
static int __devinit rhine_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct net_device *dev;
struct rhine_private *rp;
int i, rc;
u8 pci_rev;
u32 quirks;
long pioaddr;
long memaddr;
void __iomem *ioaddr;
int io_size, phy_id;
const char *name;
#ifdef USE_MMIO
int bar = 1;
#else
int bar = 0;
#endif
/* when built into the kernel, we only print version if device is found */
#ifndef MODULE
static int printed_version;
if (!printed_version++)
printk(version);
#endif
pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
io_size = 256;
phy_id = 0;
quirks = 0;
name = "Rhine";
if (pci_rev < VTunknown0) {
quirks = rqRhineI;
io_size = 128;
}
else if (pci_rev >= VT6102) {
quirks = rqWOL | rqForceReset;
if (pci_rev < VT6105) {
name = "Rhine II";
quirks |= rqStatusWBRace; /* Rhine-II exclusive */
}
else {
phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
if (pci_rev >= VT6105_B0)
quirks |= rq6patterns;
if (pci_rev < VT6105M)
name = "Rhine III";
else
name = "Rhine III (Management Adapter)";
}
}
rc = pci_enable_device(pdev);
if (rc)
goto err_out;
/* this should always be supported */
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
if (rc) {
printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
"the card!?\n");
goto err_out;
}
/* sanity check */
if ((pci_resource_len(pdev, 0) < io_size) ||
(pci_resource_len(pdev, 1) < io_size)) {
rc = -EIO;
printk(KERN_ERR "Insufficient PCI resources, aborting\n");
goto err_out;
}
pioaddr = pci_resource_start(pdev, 0);
memaddr = pci_resource_start(pdev, 1);
pci_set_master(pdev);
dev = alloc_etherdev(sizeof(struct rhine_private));
if (!dev) {
rc = -ENOMEM;
printk(KERN_ERR "alloc_etherdev failed\n");
goto err_out;
}
SET_MODULE_OWNER(dev);
SET_NETDEV_DEV(dev, &pdev->dev);
rp = netdev_priv(dev);
rp->quirks = quirks;
rp->pioaddr = pioaddr;
rp->pdev = pdev;
rc = pci_request_regions(pdev, DRV_NAME);
if (rc)
goto err_out_free_netdev;
ioaddr = pci_iomap(pdev, bar, io_size);
if (!ioaddr) {
rc = -EIO;
printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
"@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
goto err_out_free_res;
}
#ifdef USE_MMIO
enable_mmio(pioaddr, quirks);
/* Check that selected MMIO registers match the PIO ones */
i = 0;
while (mmio_verify_registers[i]) {
int reg = mmio_verify_registers[i++];
unsigned char a = inb(pioaddr+reg);
unsigned char b = readb(ioaddr+reg);
if (a != b) {
rc = -EIO;
printk(KERN_ERR "MMIO do not match PIO [%02x] "
"(%02x != %02x)\n", reg, a, b);
goto err_out_unmap;
}
}
#endif /* USE_MMIO */
dev->base_addr = (unsigned long)ioaddr;
rp->base = ioaddr;
/* Get chip registers into a sane state */
rhine_power_init(dev);
rhine_hw_init(dev, pioaddr);
for (i = 0; i < 6; i++)
dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
if (!is_valid_ether_addr(dev->perm_addr)) {
rc = -EIO;
printk(KERN_ERR "Invalid MAC address\n");
goto err_out_unmap;
}
/* For Rhine-I/II, phy_id is loaded from EEPROM */
if (!phy_id)
phy_id = ioread8(ioaddr + 0x6C);
dev->irq = pdev->irq;
spin_lock_init(&rp->lock);
rp->mii_if.dev = dev;
rp->mii_if.mdio_read = mdio_read;
rp->mii_if.mdio_write = mdio_write;
rp->mii_if.phy_id_mask = 0x1f;
rp->mii_if.reg_num_mask = 0x1f;
/* The chip-specific entries in the device structure. */
dev->open = rhine_open;
dev->hard_start_xmit = rhine_start_tx;
dev->stop = rhine_close;
dev->get_stats = rhine_get_stats;
dev->set_multicast_list = rhine_set_rx_mode;
dev->do_ioctl = netdev_ioctl;
dev->ethtool_ops = &netdev_ethtool_ops;
dev->tx_timeout = rhine_tx_timeout;
dev->watchdog_timeo = TX_TIMEOUT;
#ifdef CONFIG_NET_POLL_CONTROLLER
dev->poll_controller = rhine_poll;
#endif
if (rp->quirks & rqRhineI)
dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
INIT_WORK(&rp->tx_timeout_task,
(void (*)(void *))rhine_tx_timeout_task, dev);
INIT_WORK(&rp->check_media_task,
(void (*)(void *))rhine_check_media_task, dev);
/* dev->name not defined before register_netdev()! */
rc = register_netdev(dev);
if (rc)
goto err_out_unmap;
printk(KERN_INFO "%s: VIA %s at 0x%lx, ",
dev->name, name,
#ifdef USE_MMIO
memaddr
#else
(long)ioaddr
#endif
);
for (i = 0; i < 5; i++)
printk("%2.2x:", dev->dev_addr[i]);
printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], pdev->irq);
pci_set_drvdata(pdev, dev);
{
u16 mii_cmd;
int mii_status = mdio_read(dev, phy_id, 1);
mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
if (mii_status != 0xffff && mii_status != 0x0000) {
rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
printk(KERN_INFO "%s: MII PHY found at address "
"%d, status 0x%4.4x advertising %4.4x "
"Link %4.4x.\n", dev->name, phy_id,
mii_status, rp->mii_if.advertising,
mdio_read(dev, phy_id, 5));
/* set IFF_RUNNING */
if (mii_status & BMSR_LSTATUS)
netif_carrier_on(dev);
else
netif_carrier_off(dev);
}
}
rp->mii_if.phy_id = phy_id;
return 0;
err_out_unmap:
pci_iounmap(pdev, ioaddr);
err_out_free_res:
pci_release_regions(pdev);
err_out_free_netdev:
free_netdev(dev);
err_out:
return rc;
}
static int alloc_ring(struct net_device* dev)
{
struct rhine_private *rp = netdev_priv(dev);
void *ring;
dma_addr_t ring_dma;
ring = pci_alloc_consistent(rp->pdev,
RX_RING_SIZE * sizeof(struct rx_desc) +
TX_RING_SIZE * sizeof(struct tx_desc),
&ring_dma);
if (!ring) {
printk(KERN_ERR "Could not allocate DMA memory.\n");
return -ENOMEM;
}
if (rp->quirks & rqRhineI) {
rp->tx_bufs = pci_alloc_consistent(rp->pdev,
PKT_BUF_SZ * TX_RING_SIZE,
&rp->tx_bufs_dma);
if (rp->tx_bufs == NULL) {
pci_free_consistent(rp->pdev,
RX_RING_SIZE * sizeof(struct rx_desc) +
TX_RING_SIZE * sizeof(struct tx_desc),
ring, ring_dma);
return -ENOMEM;
}
}
rp->rx_ring = ring;
rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
rp->rx_ring_dma = ring_dma;
rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
return 0;
}
static void free_ring(struct net_device* dev)
{
struct rhine_private *rp = netdev_priv(dev);
pci_free_consistent(rp->pdev,
RX_RING_SIZE * sizeof(struct rx_desc) +
TX_RING_SIZE * sizeof(struct tx_desc),
rp->rx_ring, rp->rx_ring_dma);
rp->tx_ring = NULL;
if (rp->tx_bufs)
pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
rp->tx_bufs, rp->tx_bufs_dma);
rp->tx_bufs = NULL;
}
static void alloc_rbufs(struct net_device *dev)
{
struct rhine_private *rp = netdev_priv(dev);
dma_addr_t next;
int i;
rp->dirty_rx = rp->cur_rx = 0;
rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
rp->rx_head_desc = &rp->rx_ring[0];
next = rp->rx_ring_dma;
/* Init the ring entries */
for (i = 0; i < RX_RING_SIZE; i++) {
rp->rx_ring[i].rx_status = 0;
rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
next += sizeof(struct rx_desc);
rp->rx_ring[i].next_desc = cpu_to_le32(next);
rp->rx_skbuff[i] = NULL;
}
/* Mark the last entry as wrapping the ring. */
rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
/* Fill in the Rx buffers. Handle allocation failure gracefully. */
for (i = 0; i < RX_RING_SIZE; i++) {
struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
rp->rx_skbuff[i] = skb;
if (skb == NULL)
break;