forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathabituguru3.c
1308 lines (1198 loc) · 40.2 KB
/
abituguru3.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* abituguru3.c
*
* Copyright (c) 2006-2008 Hans de Goede <[email protected]>
* Copyright (c) 2008 Alistair John Strachan <[email protected]>
*/
/*
* This driver supports the sensor part of revision 3 of the custom Abit uGuru
* chip found on newer Abit uGuru motherboards. Note: because of lack of specs
* only reading the sensors and their settings is supported.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/dmi.h>
#include <linux/io.h>
/* uGuru3 bank addresses */
#define ABIT_UGURU3_SETTINGS_BANK 0x01
#define ABIT_UGURU3_SENSORS_BANK 0x08
#define ABIT_UGURU3_MISC_BANK 0x09
#define ABIT_UGURU3_ALARMS_START 0x1E
#define ABIT_UGURU3_SETTINGS_START 0x24
#define ABIT_UGURU3_VALUES_START 0x80
#define ABIT_UGURU3_BOARD_ID 0x0A
/* uGuru3 sensor bank flags */ /* Alarm if: */
#define ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE 0x01 /* temp over warn */
#define ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE 0x02 /* volt over max */
#define ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE 0x04 /* volt under min */
#define ABIT_UGURU3_TEMP_HIGH_ALARM_FLAG 0x10 /* temp is over warn */
#define ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG 0x20 /* volt is over max */
#define ABIT_UGURU3_VOLT_LOW_ALARM_FLAG 0x40 /* volt is under min */
#define ABIT_UGURU3_FAN_LOW_ALARM_ENABLE 0x01 /* fan under min */
#define ABIT_UGURU3_BEEP_ENABLE 0x08 /* beep if alarm */
#define ABIT_UGURU3_SHUTDOWN_ENABLE 0x80 /* shutdown if alarm */
/* sensor types */
#define ABIT_UGURU3_IN_SENSOR 0
#define ABIT_UGURU3_TEMP_SENSOR 1
#define ABIT_UGURU3_FAN_SENSOR 2
/*
* Timeouts / Retries, if these turn out to need a lot of fiddling we could
* convert them to params. Determined by trial and error. I assume this is
* cpu-speed independent, since the ISA-bus and not the CPU should be the
* bottleneck.
*/
#define ABIT_UGURU3_WAIT_TIMEOUT 250
/*
* Normally the 0xAC at the end of synchronize() is reported after the
* first read, but sometimes not and we need to poll
*/
#define ABIT_UGURU3_SYNCHRONIZE_TIMEOUT 5
/* utility macros */
#define ABIT_UGURU3_NAME "abituguru3"
#define ABIT_UGURU3_DEBUG(format, arg...) \
do { \
if (verbose) \
pr_debug(format , ## arg); \
} while (0)
/* Macros to help calculate the sysfs_names array length */
#define ABIT_UGURU3_MAX_NO_SENSORS 26
/*
* sum of strlen +1 of: in??_input\0, in??_{min,max}\0, in??_{min,max}_alarm\0,
* in??_{min,max}_alarm_enable\0, in??_beep\0, in??_shutdown\0, in??_label\0
*/
#define ABIT_UGURU3_IN_NAMES_LENGTH \
(11 + 2 * 9 + 2 * 15 + 2 * 22 + 10 + 14 + 11)
/*
* sum of strlen +1 of: temp??_input\0, temp??_max\0, temp??_crit\0,
* temp??_alarm\0, temp??_alarm_enable\0, temp??_beep\0, temp??_shutdown\0,
* temp??_label\0
*/
#define ABIT_UGURU3_TEMP_NAMES_LENGTH (13 + 11 + 12 + 13 + 20 + 12 + 16 + 13)
/*
* sum of strlen +1 of: fan??_input\0, fan??_min\0, fan??_alarm\0,
* fan??_alarm_enable\0, fan??_beep\0, fan??_shutdown\0, fan??_label\0
*/
#define ABIT_UGURU3_FAN_NAMES_LENGTH (12 + 10 + 12 + 19 + 11 + 15 + 12)
/*
* Worst case scenario 16 in sensors (longest names_length) and the rest
* temp sensors (second longest names_length).
*/
#define ABIT_UGURU3_SYSFS_NAMES_LENGTH (16 * ABIT_UGURU3_IN_NAMES_LENGTH + \
(ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH)
/*
* All the macros below are named identical to the openguru2 program
* reverse engineered by Louis Kruger, hence the names might not be 100%
* logical. I could come up with better names, but I prefer keeping the names
* identical so that this driver can be compared with his work more easily.
*/
/* Two i/o-ports are used by uGuru */
#define ABIT_UGURU3_BASE 0x00E0
#define ABIT_UGURU3_CMD 0x00
#define ABIT_UGURU3_DATA 0x04
#define ABIT_UGURU3_REGION_LENGTH 5
/*
* The wait_xxx functions return this on success and the last contents
* of the DATA register (0-255) on failure.
*/
#define ABIT_UGURU3_SUCCESS -1
/* uGuru status flags */
#define ABIT_UGURU3_STATUS_READY_FOR_READ 0x01
#define ABIT_UGURU3_STATUS_BUSY 0x02
/* Structures */
struct abituguru3_sensor_info {
const char *name;
int port;
int type;
int multiplier;
int divisor;
int offset;
};
/* Avoid use of flexible array members */
#define ABIT_UGURU3_MAX_DMI_NAMES 2
struct abituguru3_motherboard_info {
u16 id;
const char *dmi_name[ABIT_UGURU3_MAX_DMI_NAMES + 1];
/* + 1 -> end of sensors indicated by a sensor with name == NULL */
struct abituguru3_sensor_info sensors[ABIT_UGURU3_MAX_NO_SENSORS + 1];
};
/*
* For the Abit uGuru, we need to keep some data in memory.
* The structure is dynamically allocated, at the same time when a new
* abituguru3 device is allocated.
*/
struct abituguru3_data {
struct device *hwmon_dev; /* hwmon registered device */
struct mutex update_lock; /* protect access to data and uGuru */
unsigned short addr; /* uguru base address */
char valid; /* !=0 if following fields are valid */
unsigned long last_updated; /* In jiffies */
/*
* For convenience the sysfs attr and their names are generated
* automatically. We have max 10 entries per sensor (for in sensors)
*/
struct sensor_device_attribute_2 sysfs_attr[ABIT_UGURU3_MAX_NO_SENSORS
* 10];
/* Buffer to store the dynamically generated sysfs names */
char sysfs_names[ABIT_UGURU3_SYSFS_NAMES_LENGTH];
/* Pointer to the sensors info for the detected motherboard */
const struct abituguru3_sensor_info *sensors;
/*
* The abituguru3 supports up to 48 sensors, and thus has registers
* sets for 48 sensors, for convenience reasons / simplicity of the
* code we always read and store all registers for all 48 sensors
*/
/* Alarms for all 48 sensors (1 bit per sensor) */
u8 alarms[48/8];
/* Value of all 48 sensors */
u8 value[48];
/*
* Settings of all 48 sensors, note in and temp sensors (the first 32
* sensors) have 3 bytes of settings, while fans only have 2 bytes,
* for convenience we use 3 bytes for all sensors
*/
u8 settings[48][3];
};
/* Constants */
static const struct abituguru3_motherboard_info abituguru3_motherboards[] = {
{ 0x000C, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS FAN", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x000D, { NULL } /* Abit AW8, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM1", 26, 1, 1, 1, 0 },
{ "PWM2", 27, 1, 1, 1, 0 },
{ "PWM3", 28, 1, 1, 1, 0 },
{ "PWM4", 29, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
{ "AUX4 Fan", 38, 2, 60, 1, 0 },
{ "AUX5 Fan", 39, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x000E, { NULL } /* AL-8, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x000F, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0010, { NULL } /* Abit NI8 SLI GR, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "NB 1.4V", 4, 0, 10, 1, 0 },
{ "SB 1.5V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "SYS", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "OTES1 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0011, { "AT8 32X", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 20, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
{ "NB 1.8V", 4, 0, 10, 1, 0 },
{ "NB 1.8V Dual", 5, 0, 10, 1, 0 },
{ "HTV 1.2", 3, 0, 10, 1, 0 },
{ "PCIE 1.2V", 12, 0, 10, 1, 0 },
{ "NB 1.2V", 13, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "NB", 25, 1, 1, 1, 0 },
{ "System", 26, 1, 1, 1, 0 },
{ "PWM", 27, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0012, { NULL } /* Abit AN8 32X, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 20, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "HyperTransport", 3, 0, 10, 1, 0 },
{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
{ "NB", 4, 0, 10, 1, 0 },
{ "SB", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "SYS", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0013, { NULL } /* Abit AW8D, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM1", 26, 1, 1, 1, 0 },
{ "PWM2", 27, 1, 1, 1, 0 },
{ "PWM3", 28, 1, 1, 1, 0 },
{ "PWM4", 29, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
{ "AUX4 Fan", 38, 2, 60, 1, 0 },
{ "AUX5 Fan", 39, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0014, { "AB9", "AB9 Pro", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 10, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0015, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR", 1, 0, 20, 1, 0 },
{ "DDR VTT", 2, 0, 10, 1, 0 },
{ "HyperTransport", 3, 0, 10, 1, 0 },
{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
{ "NB", 4, 0, 10, 1, 0 },
{ "SB", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "SYS", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0016, { "AW9D-MAX", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM1", 26, 1, 1, 1, 0 },
{ "PWM2", 27, 1, 1, 1, 0 },
{ "PWM3", 28, 1, 1, 1, 0 },
{ "PWM4", 29, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "NB Fan", 33, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
{ "AUX2 Fan", 36, 2, 60, 1, 0 },
{ "AUX3 Fan", 37, 2, 60, 1, 0 },
{ "OTES1 Fan", 38, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0017, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "HyperTransport", 3, 0, 10, 1, 0 },
{ "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
{ "NB 1.8V", 4, 0, 10, 1, 0 },
{ "NB 1.2V ", 13, 0, 10, 1, 0 },
{ "SB 1.2V", 5, 0, 10, 1, 0 },
{ "PCIE 1.2V", 12, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "ATX +3.3V", 10, 0, 20, 1, 0 },
{ "ATX 5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 26, 1, 1, 1, 0 },
{ "PWM", 27, 1, 1, 1, 0 },
{ "CPU FAN", 32, 2, 60, 1, 0 },
{ "SYS FAN", 34, 2, 60, 1, 0 },
{ "AUX1 FAN", 35, 2, 60, 1, 0 },
{ "AUX2 FAN", 36, 2, 60, 1, 0 },
{ "AUX3 FAN", 37, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0018, { "AB9 QuadGT", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT", 3, 0, 10, 1, 0 },
{ "MCH 1.25V", 4, 0, 10, 1, 0 },
{ "ICHIO 1.5V", 5, 0, 10, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM Phase1", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0019, { "IN9 32X MAX", NULL }, {
{ "CPU Core", 7, 0, 10, 1, 0 },
{ "DDR2", 13, 0, 20, 1, 0 },
{ "DDR2 VTT", 14, 0, 10, 1, 0 },
{ "CPU VTT", 3, 0, 20, 1, 0 },
{ "NB 1.2V", 4, 0, 10, 1, 0 },
{ "SB 1.5V", 6, 0, 10, 1, 0 },
{ "HyperTransport", 5, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 12, 0, 60, 1, 0 },
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "ATX +3.3V", 10, 0, 20, 1, 0 },
{ "ATX 5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM Phase1", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU FAN", 32, 2, 60, 1, 0 },
{ "SYS FAN", 34, 2, 60, 1, 0 },
{ "AUX1 FAN", 33, 2, 60, 1, 0 },
{ "AUX2 FAN", 35, 2, 60, 1, 0 },
{ "AUX3 FAN", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x001A, { "IP35 Pro", "IP35 Pro XE", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
{ "MCH 1.25V", 4, 0, 10, 1, 0 },
{ "ICHIO 1.5V", 5, 0, 10, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ "AUX4 Fan", 37, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x001B, { NULL } /* Unknown, need DMI string */, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR3", 1, 0, 20, 1, 0 },
{ "DDR3 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT", 3, 0, 10, 1, 0 },
{ "MCH 1.25V", 4, 0, 10, 1, 0 },
{ "ICHIO 1.5V", 5, 0, 10, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM Phase1", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x001C, { "IX38 QuadGT", NULL }, {
{ "CPU Core", 0, 0, 10, 1, 0 },
{ "DDR2", 1, 0, 20, 1, 0 },
{ "DDR2 VTT", 2, 0, 10, 1, 0 },
{ "CPU VTT", 3, 0, 10, 1, 0 },
{ "MCH 1.25V", 4, 0, 10, 1, 0 },
{ "ICHIO 1.5V", 5, 0, 10, 1, 0 },
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
{ "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
{ "ATX +5V", 9, 0, 30, 1, 0 },
{ "+3.3V", 10, 0, 20, 1, 0 },
{ "5VSB", 11, 0, 30, 1, 0 },
{ "CPU", 24, 1, 1, 1, 0 },
{ "System", 25, 1, 1, 1, 0 },
{ "PWM Phase1", 26, 1, 1, 1, 0 },
{ "PWM Phase2", 27, 1, 1, 1, 0 },
{ "PWM Phase3", 28, 1, 1, 1, 0 },
{ "PWM Phase4", 29, 1, 1, 1, 0 },
{ "PWM Phase5", 30, 1, 1, 1, 0 },
{ "CPU Fan", 32, 2, 60, 1, 0 },
{ "SYS Fan", 34, 2, 60, 1, 0 },
{ "AUX1 Fan", 33, 2, 60, 1, 0 },
{ "AUX2 Fan", 35, 2, 60, 1, 0 },
{ "AUX3 Fan", 36, 2, 60, 1, 0 },
{ NULL, 0, 0, 0, 0, 0 } }
},
{ 0x0000, { NULL }, { { NULL, 0, 0, 0, 0, 0 } } }
};
/* Insmod parameters */
static bool force;
module_param(force, bool, 0);
MODULE_PARM_DESC(force, "Set to one to force detection.");
/* Default verbose is 1, since this driver is still in the testing phase */
static bool verbose = 1;
module_param(verbose, bool, 0644);
MODULE_PARM_DESC(verbose, "Enable/disable verbose error reporting");
static const char *never_happen = "This should never happen.";
static const char *report_this =
"Please report this to the abituguru3 maintainer (see MAINTAINERS)";
/* wait while the uguru is busy (usually after a write) */
static int abituguru3_wait_while_busy(struct abituguru3_data *data)
{
u8 x;
int timeout = ABIT_UGURU3_WAIT_TIMEOUT;
while ((x = inb_p(data->addr + ABIT_UGURU3_DATA)) &
ABIT_UGURU3_STATUS_BUSY) {
timeout--;
if (timeout == 0)
return x;
/*
* sleep a bit before our last try, to give the uGuru3 one
* last chance to respond.
*/
if (timeout == 1)
msleep(1);
}
return ABIT_UGURU3_SUCCESS;
}
/* wait till uguru is ready to be read */
static int abituguru3_wait_for_read(struct abituguru3_data *data)
{
u8 x;
int timeout = ABIT_UGURU3_WAIT_TIMEOUT;
while (!((x = inb_p(data->addr + ABIT_UGURU3_DATA)) &
ABIT_UGURU3_STATUS_READY_FOR_READ)) {
timeout--;
if (timeout == 0)
return x;
/*
* sleep a bit before our last try, to give the uGuru3 one
* last chance to respond.
*/
if (timeout == 1)
msleep(1);
}
return ABIT_UGURU3_SUCCESS;
}
/*
* This synchronizes us with the uGuru3's protocol state machine, this
* must be done before each command.
*/
static int abituguru3_synchronize(struct abituguru3_data *data)
{
int x, timeout = ABIT_UGURU3_SYNCHRONIZE_TIMEOUT;
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout during initial busy "
"wait, status: 0x%02x\n", x);
return -EIO;
}
outb(0x20, data->addr + ABIT_UGURU3_DATA);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x20, "
"status: 0x%02x\n", x);
return -EIO;
}
outb(0x10, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x10, "
"status: 0x%02x\n", x);
return -EIO;
}
outb(0x00, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x00, "
"status: 0x%02x\n", x);
return -EIO;
}
x = abituguru3_wait_for_read(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("synchronize timeout waiting for read, "
"status: 0x%02x\n", x);
return -EIO;
}
while ((x = inb(data->addr + ABIT_UGURU3_CMD)) != 0xAC) {
timeout--;
if (timeout == 0) {
ABIT_UGURU3_DEBUG("synchronize timeout cmd does not "
"hold 0xAC after synchronize, cmd: 0x%02x\n",
x);
return -EIO;
}
msleep(1);
}
return 0;
}
/*
* Read count bytes from sensor sensor_addr in bank bank_addr and store the
* result in buf
*/
static int abituguru3_read(struct abituguru3_data *data, u8 bank, u8 offset,
u8 count, u8 *buf)
{
int i, x;
x = abituguru3_synchronize(data);
if (x)
return x;
outb(0x1A, data->addr + ABIT_UGURU3_DATA);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
"sending 0x1A, status: 0x%02x\n", (unsigned int)bank,
(unsigned int)offset, x);
return -EIO;
}
outb(bank, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
"sending the bank, status: 0x%02x\n",
(unsigned int)bank, (unsigned int)offset, x);
return -EIO;
}
outb(offset, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
"sending the offset, status: 0x%02x\n",
(unsigned int)bank, (unsigned int)offset, x);
return -EIO;
}
outb(count, data->addr + ABIT_UGURU3_CMD);
x = abituguru3_wait_while_busy(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
"sending the count, status: 0x%02x\n",
(unsigned int)bank, (unsigned int)offset, x);
return -EIO;
}
for (i = 0; i < count; i++) {
x = abituguru3_wait_for_read(data);
if (x != ABIT_UGURU3_SUCCESS) {
ABIT_UGURU3_DEBUG("timeout reading byte %d from "
"0x%02x:0x%02x, status: 0x%02x\n", i,
(unsigned int)bank, (unsigned int)offset, x);
break;
}
buf[i] = inb(data->addr + ABIT_UGURU3_CMD);
}
return i;
}
/*
* Sensor settings are stored 1 byte per offset with the bytes
* placed add consecutive offsets.
*/
static int abituguru3_read_increment_offset(struct abituguru3_data *data,
u8 bank, u8 offset, u8 count,
u8 *buf, int offset_count)
{
int i, x;
for (i = 0; i < offset_count; i++) {
x = abituguru3_read(data, bank, offset + i, count,
buf + i * count);
if (x != count) {
if (x < 0)
return x;
return i * count + x;
}
}
return i * count;
}
/*
* Following are the sysfs callback functions. These functions expect:
* sensor_device_attribute_2->index: index into the data->sensors array
* sensor_device_attribute_2->nr: register offset, bitmask or NA.
*/
static struct abituguru3_data *abituguru3_update_device(struct device *dev);
static ssize_t show_value(struct device *dev,
struct device_attribute *devattr, char *buf)
{
int value;
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru3_data *data = abituguru3_update_device(dev);
const struct abituguru3_sensor_info *sensor;
if (!data)
return -EIO;
sensor = &data->sensors[attr->index];
/* are we reading a setting, or is this a normal read? */
if (attr->nr)
value = data->settings[sensor->port][attr->nr];
else
value = data->value[sensor->port];
/* convert the value */
value = (value * sensor->multiplier) / sensor->divisor +
sensor->offset;
/*
* alternatively we could update the sensors settings struct for this,
* but then its contents would differ from the windows sw ini files
*/
if (sensor->type == ABIT_UGURU3_TEMP_SENSOR)
value *= 1000;
return sprintf(buf, "%d\n", value);
}
static ssize_t show_alarm(struct device *dev,
struct device_attribute *devattr, char *buf)
{
int port;
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru3_data *data = abituguru3_update_device(dev);
if (!data)
return -EIO;
port = data->sensors[attr->index].port;
/*
* See if the alarm bit for this sensor is set and if a bitmask is
* given in attr->nr also check if the alarm matches the type of alarm
* we're looking for (for volt it can be either low or high). The type
* is stored in a few readonly bits in the settings of the sensor.
*/
if ((data->alarms[port / 8] & (0x01 << (port % 8))) &&
(!attr->nr || (data->settings[port][0] & attr->nr)))
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static ssize_t show_mask(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru3_data *data = dev_get_drvdata(dev);
if (data->settings[data->sensors[attr->index].port][0] & attr->nr)
return sprintf(buf, "1\n");
else
return sprintf(buf, "0\n");
}
static ssize_t show_label(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
struct abituguru3_data *data = dev_get_drvdata(dev);
return sprintf(buf, "%s\n", data->sensors[attr->index].name);
}
static ssize_t show_name(struct device *dev,
struct device_attribute *devattr, char *buf)
{
return sprintf(buf, "%s\n", ABIT_UGURU3_NAME);
}
/* Sysfs attr templates, the real entries are generated automatically. */
static const
struct sensor_device_attribute_2 abituguru3_sysfs_templ[3][10] = { {
SENSOR_ATTR_2(in%d_input, 0444, show_value, NULL, 0, 0),
SENSOR_ATTR_2(in%d_min, 0444, show_value, NULL, 1, 0),
SENSOR_ATTR_2(in%d_max, 0444, show_value, NULL, 2, 0),
SENSOR_ATTR_2(in%d_min_alarm, 0444, show_alarm, NULL,
ABIT_UGURU3_VOLT_LOW_ALARM_FLAG, 0),
SENSOR_ATTR_2(in%d_max_alarm, 0444, show_alarm, NULL,
ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG, 0),
SENSOR_ATTR_2(in%d_beep, 0444, show_mask, NULL,
ABIT_UGURU3_BEEP_ENABLE, 0),
SENSOR_ATTR_2(in%d_shutdown, 0444, show_mask, NULL,
ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(in%d_min_alarm_enable, 0444, show_mask, NULL,
ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE, 0),
SENSOR_ATTR_2(in%d_max_alarm_enable, 0444, show_mask, NULL,
ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE, 0),
SENSOR_ATTR_2(in%d_label, 0444, show_label, NULL, 0, 0)
}, {
SENSOR_ATTR_2(temp%d_input, 0444, show_value, NULL, 0, 0),
SENSOR_ATTR_2(temp%d_max, 0444, show_value, NULL, 1, 0),
SENSOR_ATTR_2(temp%d_crit, 0444, show_value, NULL, 2, 0),
SENSOR_ATTR_2(temp%d_alarm, 0444, show_alarm, NULL, 0, 0),
SENSOR_ATTR_2(temp%d_beep, 0444, show_mask, NULL,
ABIT_UGURU3_BEEP_ENABLE, 0),
SENSOR_ATTR_2(temp%d_shutdown, 0444, show_mask, NULL,
ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(temp%d_alarm_enable, 0444, show_mask, NULL,
ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE, 0),
SENSOR_ATTR_2(temp%d_label, 0444, show_label, NULL, 0, 0)
}, {
SENSOR_ATTR_2(fan%d_input, 0444, show_value, NULL, 0, 0),
SENSOR_ATTR_2(fan%d_min, 0444, show_value, NULL, 1, 0),
SENSOR_ATTR_2(fan%d_alarm, 0444, show_alarm, NULL, 0, 0),
SENSOR_ATTR_2(fan%d_beep, 0444, show_mask, NULL,
ABIT_UGURU3_BEEP_ENABLE, 0),
SENSOR_ATTR_2(fan%d_shutdown, 0444, show_mask, NULL,
ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
SENSOR_ATTR_2(fan%d_alarm_enable, 0444, show_mask, NULL,
ABIT_UGURU3_FAN_LOW_ALARM_ENABLE, 0),
SENSOR_ATTR_2(fan%d_label, 0444, show_label, NULL, 0, 0)
} };
static struct sensor_device_attribute_2 abituguru3_sysfs_attr[] = {
SENSOR_ATTR_2(name, 0444, show_name, NULL, 0, 0),
};
static int abituguru3_probe(struct platform_device *pdev)
{
const int no_sysfs_attr[3] = { 10, 8, 7 };
int sensor_index[3] = { 0, 1, 1 };
struct abituguru3_data *data;
int i, j, type, used, sysfs_names_free, sysfs_attr_i, res = -ENODEV;
char *sysfs_filename;
u8 buf[2];
u16 id;
data = devm_kzalloc(&pdev->dev, sizeof(struct abituguru3_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
mutex_init(&data->update_lock);
platform_set_drvdata(pdev, data);
/* Read the motherboard ID */
i = abituguru3_read(data, ABIT_UGURU3_MISC_BANK, ABIT_UGURU3_BOARD_ID,
2, buf);
if (i != 2)
goto abituguru3_probe_error;
/* Completely read the uGuru to see if one really is there */
if (!abituguru3_update_device(&pdev->dev))
goto abituguru3_probe_error;
/* lookup the ID in our motherboard table */
id = ((u16)buf[0] << 8) | (u16)buf[1];
for (i = 0; abituguru3_motherboards[i].id; i++)
if (abituguru3_motherboards[i].id == id)
break;
if (!abituguru3_motherboards[i].id) {
pr_err("error unknown motherboard ID: %04X. %s\n",
(unsigned int)id, report_this);
goto abituguru3_probe_error;
}
data->sensors = abituguru3_motherboards[i].sensors;
pr_info("found Abit uGuru3, motherboard ID: %04X\n", (unsigned int)id);