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dfp.c
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dfp.c
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/* DFP.C (c) Copyright Roger Bowler, 2007-2007 */
/* Decimal Floating Point instructions */
// $Id$
/*-------------------------------------------------------------------*/
/* This module implements the Decimal Floating Point instructions */
/* and the Floating Point Support Enhancement Facility instructions */
/* described in the z/Architecture Principles of Operation manual. */
/*-------------------------------------------------------------------*/
// $Log$
// Revision 1.69 2008/11/23 11:11:54 rbowler
// Fix warning C4267 conversion from 'size_t' to 'int' in win64
//
// Revision 1.68 2008/11/23 11:06:04 rbowler
// Cosmetic: remove extraneous trailing blanks from dfp.c
//
// Revision 1.67 2007/11/23 12:28:07 rbowler
// Correct CPSDR when R1 and R3 are same register (2nd attempt)
//
// Revision 1.66 2007/11/15 22:11:26 rbowler
// Correct CPSDR when R1 and R3 are same register
//
// Revision 1.65 2007/06/23 00:04:08 ivan
// Update copyright notices to include current year (2007)
//
// Revision 1.64 2007/04/25 12:33:20 rbowler
// Move SRNMT to Floating-point-support-enhancement facility
//
// Revision 1.63 2007/04/25 12:10:27 rbowler
// Move LFAS,SFASR to IEEE-exception-simulation facility
//
// Revision 1.62 2007/03/13 01:52:42 gsmith
// Fix unsigned char (BYTE) vs char warnings for decNumberFromString
//
// Revision 1.61 2007/01/30 16:43:28 rbowler
// Activate Decimal Floating Point Facility
//
// Revision 1.10 2006/12/08 09:43:20 jj
// Add CVS message log
//
#include "hstdinc.h"
#if !defined(_HENGINE_DLL_)
#define _HENGINE_DLL_
#endif
#if !defined(_DFP_C_)
#define _DFP_C_
#endif
#include "hercules.h"
#include "opcode.h"
#include "inline.h"
#if defined(FEATURE_DECIMAL_FLOATING_POINT)
#include "decimal128.h"
#include "decimal64.h"
#include "decimal32.h"
#include "decPacked.h"
#endif /*defined(FEATURE_DECIMAL_FLOATING_POINT)*/
#if defined(FEATURE_FPS_ENHANCEMENT)
/*===================================================================*/
/* FLOATING POINT SUPPORT INSTRUCTIONS */
/*===================================================================*/
/* Note: the Floating Point Support instructions use the HFPREG_CHECK
and HFPREG2_CHECK macros to enforce an AFP-register data exception
if an FPS instruction attempts to use one of the 12 additional FPR
registers when the AFP-register-control bit in CR0 is zero. */
/*-------------------------------------------------------------------*/
/* B370 LPDFR - Load Positive FPR Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(load_positive_fpr_long_reg)
{
int r1, r2; /* Values of R fields */
int i1, i2; /* FP register subscripts */
RRE(inst, regs, r1, r2);
HFPREG2_CHECK(r1, r2, regs);
i1 = FPR2I(r1);
i2 = FPR2I(r2);
/* Copy register contents, clear the sign bit */
regs->fpr[i1] = regs->fpr[i2] & 0x7FFFFFFF;
regs->fpr[i1+1] = regs->fpr[i2+1];
} /* end DEF_INST(load_positive_fpr_long_reg) */
/*-------------------------------------------------------------------*/
/* B371 LNDFR - Load Negative FPR Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(load_negative_fpr_long_reg)
{
int r1, r2; /* Values of R fields */
int i1, i2; /* FP register subscripts */
RRE(inst, regs, r1, r2);
HFPREG2_CHECK(r1, r2, regs);
i1 = FPR2I(r1);
i2 = FPR2I(r2);
/* Copy register contents, set the sign bit */
regs->fpr[i1] = regs->fpr[i2] | 0x80000000;
regs->fpr[i1+1] = regs->fpr[i2+1];
} /* end DEF_INST(load_negative_fpr_long_reg) */
/*-------------------------------------------------------------------*/
/* B372 CPSDR - Copy Sign FPR Long Register [RRF] */
/*-------------------------------------------------------------------*/
DEF_INST(copy_sign_fpr_long_reg)
{
int r1, r2, r3; /* Values of R fields */
int i1, i2, i3; /* FP register subscripts */
U32 sign; /* Work area for sign bit */
RRF_M(inst, regs, r1, r2, r3);
HFPREG2_CHECK(r1, r2, regs);
HFPREG_CHECK(r3, regs);
i1 = FPR2I(r1);
i2 = FPR2I(r2);
i3 = FPR2I(r3);
/* Copy the sign bit from r3 register */
sign = regs->fpr[i3] & 0x80000000;
/* Copy r2 register contents to r1 register */
regs->fpr[i1] = regs->fpr[i2];
regs->fpr[i1+1] = regs->fpr[i2+1];
/* Insert the sign bit into r1 register */
regs->fpr[i1] &= 0x7FFFFFFF;
regs->fpr[i1] |= sign;
} /* end DEF_INST(copy_sign_fpr_long_reg) */
/*-------------------------------------------------------------------*/
/* B373 LCDFR - Load Complement FPR Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(load_complement_fpr_long_reg)
{
int r1, r2; /* Values of R fields */
int i1, i2; /* FP register subscripts */
RRE(inst, regs, r1, r2);
HFPREG2_CHECK(r1, r2, regs);
i1 = FPR2I(r1);
i2 = FPR2I(r2);
/* Copy register contents, invert sign bit */
regs->fpr[i1] = regs->fpr[i2] ^ 0x80000000;
regs->fpr[i1+1] = regs->fpr[i2+1];
} /* end DEF_INST(load_complement_fpr_long_reg) */
/*-------------------------------------------------------------------*/
/* B3C1 LDGR - Load FPR from GR Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(load_fpr_from_gr_long_reg)
{
int r1, r2; /* Values of R fields */
int i1; /* FP register subscript */
RRE(inst, regs, r1, r2);
HFPREG_CHECK(r1, regs);
i1 = FPR2I(r1);
/* Load FP register contents from general register */
regs->fpr[i1] = regs->GR_H(r2);
regs->fpr[i1+1] = regs->GR_L(r2);
} /* end DEF_INST(load_fpr_from_gr_long_reg) */
/*-------------------------------------------------------------------*/
/* B3CD LGDR - Load GR from FPR Long Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(load_gr_from_fpr_long_reg)
{
int r1, r2; /* Values of R fields */
int i2; /* FP register subscript */
RRE(inst, regs, r1, r2);
HFPREG_CHECK(r2, regs);
i2 = FPR2I(r2);
/* Load general register contents from FP register */
regs->GR_H(r1) = regs->fpr[i2];
regs->GR_L(r1) = regs->fpr[i2+1];
} /* end DEF_INST(load_gr_from_fpr_long_reg) */
/*-------------------------------------------------------------------*/
/* B2B9 SRNMT - Set DFP Rounding Mode [S] */
/*-------------------------------------------------------------------*/
DEF_INST(set_dfp_rounding_mode)
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
S(inst, regs, b2, effective_addr2);
DFPINST_CHECK(regs);
/* Set DFP rounding mode in FPC register from address bits 61-63 */
regs->fpc &= ~(FPC_DRM);
regs->fpc |= ((effective_addr2 << FPC_DRM_SHIFT) & FPC_DRM);
} /* end DEF_INST(set_dfp_rounding_mode) */
#endif /*defined(FEATURE_FPS_ENHANCEMENT)*/
#if defined(FEATURE_IEEE_EXCEPTION_SIMULATION)
/*===================================================================*/
/* IEEE-EXCEPTION-SIMULATION FACILITY INSTRUCTIONS */
/*===================================================================*/
#if !defined(_IXS_ARCH_INDEPENDENT_)
/*-------------------------------------------------------------------*/
/* Check if a simulated-IEEE-exception event is to be recognized */
/* */
/* This subroutine is called by the LFAS and SFASR instructions to */
/* determine whether the instruction should raise a data exception */
/* at the end of the instruction and, if so, the DXC code to be set. */
/* */
/* Input: */
/* cur_fpc Current value of the FPC register */
/* src_fpc Value of instruction source operand */
/* Output: */
/* The return value is the data exception code (DXC), or */
/* zero if no simulated-IEEE-exception event is recognized */
/*-------------------------------------------------------------------*/
static BYTE
fpc_signal_check(U32 cur_fpc, U32 src_fpc)
{
U32 ff, sm, enabled_flags; /* Mask and flag work areas */
BYTE dxc; /* Data exception code or 0 */
/* AND the current FPC flags with the source FPC mask */
ff = (cur_fpc & FPC_FLAG) >> FPC_FLAG_SHIFT;
sm = (src_fpc & FPC_MASK) >> FPC_MASK_SHIFT;
enabled_flags = (ff & sm) << FPC_FLAG_SHIFT;
/* A simulated-IEEE-exception event is recognized
if any current flag corresponds to the source mask */
if (enabled_flags & FPC_FLAG_SFI)
{
dxc = DXC_IEEE_INV_OP_IISE;
}
else if (enabled_flags & FPC_FLAG_SFZ)
{
dxc = DXC_IEEE_DIV_ZERO_IISE;
}
else if (enabled_flags & FPC_FLAG_SFO)
{
dxc = (cur_fpc & FPC_FLAG_SFX) ?
DXC_IEEE_OF_INEX_IISE :
DXC_IEEE_OF_EXACT_IISE;
}
else if (enabled_flags & FPC_FLAG_SFU)
{
dxc = (cur_fpc & FPC_FLAG_SFX) ?
DXC_IEEE_UF_INEX_IISE :
DXC_IEEE_UF_EXACT_IISE;
}
else if (enabled_flags & FPC_FLAG_SFX)
{
dxc = DXC_IEEE_INEXACT_IISE;
}
else
{
dxc = 0;
}
/* Return data exception code or zero */
return dxc;
} /* end function fpc_signal_check */
#define _IXS_ARCH_INDEPENDENT_
#endif /*!defined(_IXS_ARCH_INDEPENDENT_)*/
/*-------------------------------------------------------------------*/
/* B2BD LFAS - Load FPC and Signal [S] */
/*-------------------------------------------------------------------*/
DEF_INST(load_fpc_and_signal)
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
U32 src_fpc, new_fpc; /* New value for FPC */
BYTE dxc; /* Data exception code */
S(inst, regs, b2, effective_addr2);
DFPINST_CHECK(regs);
/* Load new FPC register contents from operand location */
src_fpc = ARCH_DEP(vfetch4) (effective_addr2, b2, regs);
/* Program check if reserved bits are non-zero */
FPC_CHECK(src_fpc, regs);
/* OR the flags from the current FPC register */
new_fpc = src_fpc | (regs->fpc & FPC_FLAG);
/* Determine whether an event is to be signaled */
dxc = fpc_signal_check(regs->fpc, src_fpc);
/* Update the FPC register */
regs->fpc = new_fpc;
/* Signal a simulated-IEEE-exception event if needed */
if (dxc != 0)
{
regs->dxc = dxc;
ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
}
} /* end DEF_INST(load_fpc_and_signal) */
/*-------------------------------------------------------------------*/
/* B385 SFASR - Set FPC and Signal [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(set_fpc_and_signal)
{
int r1, unused; /* Values of R fields */
U32 src_fpc, new_fpc; /* New value for FPC */
BYTE dxc; /* Data exception code */
RRE(inst, regs, r1, unused);
DFPINST_CHECK(regs);
/* Load new FPC register contents from R1 register bits 32-63 */
src_fpc = regs->GR_L(r1);
/* Program check if reserved bits are non-zero */
FPC_CHECK(src_fpc, regs);
/* OR the flags from the current FPC register */
new_fpc = src_fpc | (regs->fpc & FPC_FLAG);
/* Determine whether an event is to be signaled */
dxc = fpc_signal_check(regs->fpc, src_fpc);
/* Update the FPC register */
regs->fpc = new_fpc;
/* Signal a simulated-IEEE-exception event if needed */
if (dxc != 0)
{
regs->dxc = dxc;
ARCH_DEP(program_interrupt) (regs, PGM_DATA_EXCEPTION);
}
} /* end DEF_INST(set_fpc_and_signal) */
#endif /*defined(FEATURE_IEEE_EXCEPTION_SIMULATION)*/
#if defined(FEATURE_DECIMAL_FLOATING_POINT)
/*===================================================================*/
/* DECIMAL FLOATING POINT INSTRUCTIONS */
/*===================================================================*/
/* Note: the DFP instructions use the DFPINST_CHECK macro to check the
setting of the AFP-register-control bit in CR0. If this bit is zero
then the macro generates a DFP-instruction data exception. */
#if !defined(_DFP_ARCH_INDEPENDENT_)
/*-------------------------------------------------------------------*/
/* Extract the leftmost digit from a decimal32/64/128 structure */
/*-------------------------------------------------------------------*/
static const int
dfp_lmdtable[32] = {0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 9, 8, 9, 0, 0};
static inline int
dfp32_extract_lmd(decimal32 *xp)
{
unsigned int cf = (((FW*)xp)->F & 0x7C000000) >> 26;
return dfp_lmdtable[cf];
} /* end function dfp32_extract_lmd */
static inline int
dfp64_extract_lmd(decimal64 *xp)
{
unsigned int cf = (((DW*)xp)->F.H.F & 0x7C000000) >> 26;
return dfp_lmdtable[cf];
} /* end function dfp64_extract_lmd */
static inline int
dfp128_extract_lmd(decimal128 *xp)
{
unsigned int cf = (((QW*)xp)->F.HH.F & 0x7C000000) >> 26;
return dfp_lmdtable[cf];
} /* end function dfp128_extract_lmd */
/*-------------------------------------------------------------------*/
/* Clear the CF and BXCF fields of a decimal32/64/128 structure */
/*-------------------------------------------------------------------*/
static inline void
dfp32_clear_cf_and_bxcf(decimal32 *xp)
{
((FW*)xp)->F &= 0x800FFFFF; /* Clear CF and BXCF fields */
} /* end function dfp32_clear_cf_and_bxcf */
static inline void
dfp64_clear_cf_and_bxcf(decimal64 *xp)
{
((DW*)xp)->F.H.F &= 0x8003FFFF; /* Clear CF and BXCF fields */
} /* end function dfp64_clear_cf_and_bxcf */
static inline void
dfp128_clear_cf_and_bxcf(decimal128 *xp)
{
((QW*)xp)->F.HH.F &= 0x80003FFF; /* Clear CF and BXCF fields */
} /* end function dfp128_clear_cf_and_bxcf */
/*-------------------------------------------------------------------*/
/* Set the CF and BXCF fields of a decimal32/64/128 structure */
/* Input: */
/* xp Pointer to a decimal32/64/128 structure */
/* cfs A 32-bit value, of which bits 0-25 are ignored, */
/* bits 26-30 contain the new CF field value (5-bits), */
/* bit 31 is the new BXCF signaling indicator (1-bit). */
/* Output: */
/* The CF field and the high-order bit of the BXCF field in */
/* the decimal32/64/128 structure are set to the indicated */
/* values and the remaining bits of the BXCF field are cleared. */
/*-------------------------------------------------------------------*/
#define DFP_CFS_INF ((30<<1)|0) /* CF and BXCF-S for Inf */
#define DFP_CFS_QNAN ((31<<1)|0) /* CF and BXCF-S for QNaN */
#define DFP_CFS_SNAN ((31<<1)|1) /* CF and BXCF-S for SNaN */
static inline void
dfp32_set_cf_and_bxcf(decimal32 *xp, U32 cfs)
{
((FW*)xp)->F &= 0x800FFFFF; /* Clear CF and BXCF fields */
((FW*)xp)->F |= (cfs & 0x3F) << 25;
/* Set CF and BXCF S-bit */
} /* end function dfp32_set_cf_and_bxcf */
static inline void
dfp64_set_cf_and_bxcf(decimal64 *xp, U32 cfs)
{
((DW*)xp)->F.H.F &= 0x8003FFFF; /* Clear CF and BXCF fields */
((DW*)xp)->F.H.F |= (cfs & 0x3F) << 25;
/* Set CF and BXCF S-bit */
} /* end function dfp64_set_cf_and_bxcf */
static inline void
dfp128_set_cf_and_bxcf(decimal128 *xp, U32 cfs)
{
((QW*)xp)->F.HH.F &= 0x80003FFF; /* Clear CF and BXCF fields */
((QW*)xp)->F.HH.F |= (cfs & 0x3F) << 25;
/* Set CF and BXCF S-bit */
} /* end function dfp128_set_cf_and_bxcf */
/*-------------------------------------------------------------------*/
/* Compare exponent and return condition code */
/* */
/* This subroutine is called by the CEETR, CEDTR, and CEXTR */
/* instructions. It compares the exponents of two decimal */
/* numbers and returns a condition code. */
/* */
/* Input: */
/* d1,d2 Pointers to decimal number structures */
/* Output: */
/* The return value is the condition code */
/*-------------------------------------------------------------------*/
static inline int
dfp_compare_exponent(decNumber *d1, decNumber *d2)
{
int cc; /* Condition code */
if (decNumberIsNaN(d1) && decNumberIsNaN(d2))
cc = 0;
else if (decNumberIsNaN(d1) || decNumberIsNaN(d2))
cc = 3;
else if (decNumberIsInfinite(d1) && decNumberIsInfinite(d2))
cc = 0;
else if (decNumberIsInfinite(d1) || decNumberIsInfinite(d2))
cc = 3;
else
cc = (d1->exponent == d2->exponent) ? 0 :
(d1->exponent < d2->exponent) ? 1 : 2 ;
return cc;
} /* end function dfp_compare_exponent */
/*-------------------------------------------------------------------*/
/* Convert 64-bit signed binary integer to decimal number */
/* */
/* This subroutine is called by the CDGTR and CXGTR instructions. */
/* It converts a 64-bit signed binary integer value into a */
/* decimal number structure. The inexact condition will be set */
/* in the decimal context structure if the number is rounded to */
/* fit the maximum number of digits specified in the context. */
/* */
/* Input: */
/* dn Pointer to decimal number structure */
/* n 64-bit signed binary integer value */
/* pset Pointer to decimal number context structure */
/* Output: */
/* The decimal number structure is updated. */
/*-------------------------------------------------------------------*/
static void
dfp_number_from_fix64(decNumber *dn, S64 n, decContext *pset)
{
int sign = 0; /* Sign of binary integer */
int i; /* Counter */
char zoned[32]; /* Zoned decimal work area */
static char maxnegzd[]="-9223372036854775808";
static U64 maxneg64 = 0x8000000000000000ULL;
/* Handle maximum negative number as special case */
if (n == (S64)maxneg64)
{
decNumberFromString(dn, maxnegzd, pset);
return;
}
/* Convert binary value to zoned decimal */
if (n < 0) { n = -n; sign = 1; }
i = sizeof(zoned) - 1;
zoned[i] = '\0';
do {
zoned[--i] = (n % 10) + '0';
n /= 10;
} while(i > 1 && n > 0);
if (sign) zoned[--i] = '-';
/* Convert zoned decimal value to decimal number structure */
decNumberFromString(dn, zoned+i, pset);
} /* end function dfp_number_from_fix64 */
/*-------------------------------------------------------------------*/
/* Convert decimal number to 64-bit signed binary integer */
/* */
/* This subroutine is called by the CGDTR and CGXTR instructions. */
/* It converts a decimal number structure to a 64-bit signed */
/* binary integer value. The inexact condition will be set in */
/* the decimal context structure if the number is rounded to */
/* an integer. The invalid operation condition will be set if */
/* the decimal value is outside the range of a 64-bit integer. */
/* */
/* Input: */
/* b Pointer to decimal number structure */
/* pset Pointer to decimal number context structure */
/* Output: */
/* The return value is the 64-bit signed binary integer result */
/*-------------------------------------------------------------------*/
static S64
dfp_number_to_fix64(decNumber *b, decContext *pset)
{
S64 n; /* 64-bit signed result */
int32_t scale; /* Scaling factor */
unsigned i; /* Array subscript */
BYTE packed[17]; /* 33-digit packed work area */
decNumber p, c; /* Working decimal numbers */
static U64 mp64 = 0x7FFFFFFFFFFFFFFFULL; /* Max pos fixed 64 */
static U64 mn64 = 0x8000000000000000ULL; /* Max neg fixed 64 */
static char mpzd[]="9223372036854775807"; /* Max pos zoned dec */
static char mnzd[]="-9223372036854775808"; /* Max neg zoned dec */
static BYTE mpflag = 0; /* 1=mp,mn are initialized */
static decNumber mp, mn; /* Decimal maximum pos,neg */
decContext setmax; /* Working context for mp,mn */
/* Prime the decimal number structures representing the maximum
positive and negative numbers representable in 64 bits. Use
a 128-bit DFP working context because these numbers are too
big to be represented in the 32-bit and 64-bit DFP formats */
if (mpflag == 0)
{
decContextDefault(&setmax, DEC_INIT_DECIMAL128);
decNumberFromString(&mp, mpzd, &setmax);
decNumberFromString(&mn, mnzd, &setmax);
mpflag = 1;
}
/* If operand is a NaN then set invalid operation
and return maximum negative result */
if (decNumberIsNaN(b))
{
pset->status |= DEC_IEEE_854_Invalid_operation;
return (S64)mn64;
}
/* Remove fractional part of decimal number */
decNumberToIntegralValue(&p, b, pset);
/* Special case if operand is less than maximum negative
number (including where operand is negative infinity) */
decNumberCompare(&c, b, &mn, pset);
if (decNumberIsNegative(&c))
{
/* If rounded value is less than maximum negative number
then set invalid operation otherwise set inexact */
decNumberCompare(&c, &p, &mn, pset);
if (decNumberIsNegative(&c))
pset->status |= DEC_IEEE_854_Invalid_operation;
else
pset->status |= DEC_IEEE_854_Inexact;
/* Return maximum negative result */
return (S64)mn64;
}
/* Special case if operand is greater than maximum positive
number (including where operand is positive infinity) */
decNumberCompare(&c, b, &mp, pset);
if (decNumberIsNegative(&c) == 0 && decNumberIsZero(&c) == 0)
{
/* If rounded value is greater than maximum positive number
then set invalid operation otherwise set inexact */
decNumberCompare(&c, &p, &mp, pset);
if (decNumberIsNegative(&c) == 0 && decNumberIsZero(&c) == 0)
pset->status |= DEC_IEEE_854_Invalid_operation;
else
pset->status |= DEC_IEEE_854_Inexact;
/* Return maximum positive result */
return (S64)mp64;
}
/* Raise inexact condition if result was rounded */
decNumberCompare(&c, &p, b, pset);
if (decNumberIsZero(&c) == 0)
{
pset->status |= DEC_IEEE_854_Inexact;
if (decNumberIsNegative(&c) == decNumberIsNegative(b))
pset->status |= DEC_Rounded;
}
/* Convert decimal number structure to packed decimal */
decPackedFromNumber(packed, sizeof(packed), &scale, &p);
/* Convert packed decimal to binary value */
for (i = 0, n = 0; i < sizeof(packed)-1; i++)
{
n = n * 10 + ((packed[i] & 0xF0) >> 4);
n = n * 10 + (packed[i] & 0x0F);
}
n = n * 10 + ((packed[i] & 0xF0) >> 4);
while (scale++) n *= 10;
if ((packed[i] & 0x0F) == 0x0D) n = -n;
/* Return 64-bit signed result */
return n;
} /* end function dfp_number_to_fix64 */
#define MAXDECSTRLEN DECIMAL128_String /* Maximum string length */
/*-------------------------------------------------------------------*/
/* Shift decimal coefficient left or right */
/* */
/* This subroutine is called by the SLDT, SLXT, SRDT and SRXT */
/* instructions. It shifts the coefficient digits of a decimal */
/* number left or right. For a left shift, zeroes are appended */
/* to the coefficient. For a right shift, digits are dropped */
/* from the end of the coefficient. No rounding is performed. */
/* The sign and exponent of the number remain unchanged. */
/* */
/* Input: */
/* pset Pointer to decimal number context structure */
/* dn Pointer to decimal number structure to be shifted */
/* count Number of digits to shift (+ve=left, -ve=right) */
/* Output: */
/* The decimal number structure is updated. */
/*-------------------------------------------------------------------*/
static inline void
dfp_shift_coeff(decContext *pset, decNumber *dn, int count)
{
size_t len; /* String length */
size_t maxlen; /* Maximum coefficient length*/
int32_t exp; /* Original exponent */
uint8_t bits; /* Original flag bits */
char zd[MAXDECSTRLEN+64]; /* Zoned decimal work area */
/* Save original exponent and sign/Inf/NaN bits */
exp = dn->exponent;
bits = dn->bits;
/* Clear exponent and sign/Inf/NaN bits */
dn->exponent = 0;
dn->bits &= ~(DECNEG | DECSPECIAL);
/* Convert coefficient digits to zoned decimal */
decNumberToString(dn, zd);
len = strlen(zd);
/* Shift zoned digits left or right */
if (count > 0)
memset(zd + len, '0', count);
len += count;
maxlen = (bits & DECSPECIAL) ? pset->digits - 1 : pset->digits;
if (len > maxlen)
{
memmove(zd, zd + len - maxlen, maxlen);
len = maxlen;
}
else if (len < 1)
{
zd[0] = '0';
len = 1;
}
zd[len] = '\0';
/* Convert shifted coefficient to decimal number structure */
decNumberFromString(dn, zd, pset);
/* Restore original exponent and sign/Inf/NaN bits */
dn->exponent = exp;
dn->bits |= bits & (DECNEG | DECSPECIAL);
} /* end function dfp_shift_coeff */
/* Bit numbers for Test Data Class instructions */
#define DFP_TDC_ZERO 52
#define DFP_TDC_SUBNORMAL 54
#define DFP_TDC_NORMAL 56
#define DFP_TDC_INFINITY 58
#define DFP_TDC_QUIET_NAN 60
#define DFP_TDC_SIGNALING_NAN 62
/*-------------------------------------------------------------------*/
/* Test data class and return condition code */
/* */
/* This subroutine is called by the TDCET, TDCDT, and TDCXT */
/* instructions. It tests the data class and sign of a decimal */
/* number. Each combination of data class and sign corresponds */
/* to one of 12 possible bits in a bitmask. The value (0 or 1) */
/* of the corresponding bit is returned. */
/* */
/* Input: */
/* pset Pointer to decimal number context structure */
/* dn Pointer to decimal number structure to be tested */
/* bits Bitmask in rightmost 12 bits */
/* Output: */
/* The return value is 0 or 1. */
/*-------------------------------------------------------------------*/
static inline int
dfp_test_data_class(decContext *pset, decNumber *dn, U32 bits)
{
int bitn; /* Bit number */
decNumber dm; /* Normalized value of dn */
if (decNumberIsZero(dn))
bitn = DFP_TDC_ZERO;
else if (decNumberIsInfinite(dn))
bitn = DFP_TDC_INFINITY;
else if (decNumberIsQNaN(dn))
bitn = DFP_TDC_QUIET_NAN;
else if (decNumberIsSNaN(dn))
bitn = DFP_TDC_SIGNALING_NAN;
else {
decNumberNormalize(&dm, dn, pset);
bitn = (dm.exponent < pset->emin) ?
DFP_TDC_SUBNORMAL :
DFP_TDC_NORMAL ;
}
if (decNumberIsNegative(dn)) bitn++;
return (bits >> (63 - bitn)) & 0x01;
} /* end function dfp_test_data_class */
/* Bit numbers for Test Data Group instructions */
#define DFP_TDG_SAFE_ZERO 52
#define DFP_TDG_EXTREME_ZERO 54
#define DFP_TDG_EXTREME_NONZERO 56
#define DFP_TDG_SAFE_NZ_LMD_Z 58
#define DFP_TDG_SAFE_NZ_LMD_NZ 60
#define DFP_TDG_SPECIAL 62
/*-------------------------------------------------------------------*/
/* Test data group and return condition code */
/* */
/* This subroutine is called by the TDGET, TDGDT, and TDGXT */
/* instructions. It tests the exponent and leftmost coefficient */
/* digit of a decimal number to determine which of 12 possible */
/* groups the number corresponds to. Each group corresponds to */
/* one of 12 possible bits in a bitmask. The value (0 or 1) of */
/* the corresponding bit is returned. */
/* */
/* Input: */
/* pset Pointer to decimal number context structure */
/* dn Pointer to decimal number structure to be tested */
/* lmd Leftmost digit of decimal FP number */
/* bits Bitmask in rightmost 12 bits */
/* Output: */
/* The return value is 0 or 1. */
/*-------------------------------------------------------------------*/
static inline int
dfp_test_data_group(decContext *pset, decNumber *dn, int lmd, U32 bits)
{
int bitn; /* Bit number */
int extreme; /* 1=exponent is min or max */
int exp; /* Adjusted exponent */
exp = dn->exponent + pset->digits - 1;
extreme = (exp == pset->emin) || (exp == pset->emax);
if (decNumberIsZero(dn))
bitn = extreme ?
DFP_TDG_EXTREME_ZERO :
DFP_TDG_SAFE_ZERO ;
else if (decNumberIsInfinite(dn) || decNumberIsNaN(dn))
bitn = DFP_TDG_SPECIAL;
else if (extreme)
bitn = DFP_TDG_EXTREME_NONZERO;
else {
bitn = (lmd == 0) ?
DFP_TDG_SAFE_NZ_LMD_Z :
DFP_TDG_SAFE_NZ_LMD_NZ ;
}
if (decNumberIsNegative(dn)) bitn++;
return (bits >> (63 - bitn)) & 0x01;
} /* end function dfp_test_data_group */
#define _DFP_ARCH_INDEPENDENT_
#endif /*!defined(_DFP_ARCH_INDEPENDENT_)*/
/*-------------------------------------------------------------------*/
/* Set rounding mode in decimal context structure */
/* */
/* Input: */
/* pset Pointer to decimal number context structure */
/* mask 4-bit mask value */
/* regs CPU register context */
/* Output: */
/* If mask bit X'08' is one then the rounding mode in the */
/* context structure is set according to the value (0 to 7) */
/* indicated by the low-order three bits of the mask. */
/* If mask bit X'08' is zero then the rounding mode in the */
/* context structure is set according to the value (0 to 7) */
/* of the DRM field in the FPC register. */
/*-------------------------------------------------------------------*/
static inline void
ARCH_DEP(dfp_rounding_mode) (decContext *pset, int mask, REGS *regs)
{
BYTE drm; /* Decimal rounding mode */
/* Load DRM from mask or from FPC register */
if (mask & 0x08)
drm = mask & 0x07;
else
drm = (regs->fpc & FPC_DRM) >> FPC_DRM_SHIFT;
/* Set rounding mode according to DRM value */
switch (drm) {
case DRM_RNE: pset->round = DEC_ROUND_HALF_EVEN; break;
case DRM_RTZ: pset->round = DEC_ROUND_DOWN; break;
case DRM_RTPI: pset->round = DEC_ROUND_CEILING; break;
case DRM_RTMI: pset->round = DEC_ROUND_FLOOR; break;
case DRM_RNAZ: pset->round = DEC_ROUND_HALF_UP; break;
case DRM_RNTZ: pset->round = DEC_ROUND_HALF_DOWN; break;
case DRM_RAFZ: pset->round = DEC_ROUND_UP; break;
case DRM_RFSP:
/* Rounding mode DRM_RFSP is not supported by
the decNumber library, so we arbitrarily
convert it to another mode instead... */
pset->round = DEC_ROUND_DOWN; break;
} /* end switch(drm) */
} /* end function dfp_rounding_mode */
/*-------------------------------------------------------------------*/
/* Copy a DFP short register into a decimal32 structure */
/* */
/* Input: */
/* rn FP register number */
/* xp Pointer to decimal32 structure */
/* regs CPU register context */
/*-------------------------------------------------------------------*/
static inline void
ARCH_DEP(dfp_reg_to_decimal32) (int rn, decimal32 *xp, REGS *regs)
{
int i; /* FP register subscript */
FW *fwp; /* Fullword pointer */
i = FPR2I(rn); /* Register index */
fwp = (FW*)xp; /* Convert to FW pointer */
fwp->F = regs->fpr[i]; /* Copy FPR bits 0-31 */
} /* end function dfp_reg_to_decimal32 */
/*-------------------------------------------------------------------*/
/* Load a DFP short register from a decimal32 structure */
/* */
/* Input: */
/* rn FP register number (left register of pair) */
/* xp Pointer to decimal32 structure */
/* regs CPU register context */
/*-------------------------------------------------------------------*/
static inline void
ARCH_DEP(dfp_reg_from_decimal32) (int rn, decimal32 *xp, REGS *regs)
{
int i; /* FP register subscript */
FW *fwp; /* Fullword pointer */
i = FPR2I(rn); /* Register index */
fwp = (FW*)xp; /* Convert to FW pointer */
regs->fpr[i] = fwp->F; /* Load FPR bits 0-31 */
} /* end function dfp_reg_from_decimal32 */
/*-------------------------------------------------------------------*/
/* Copy a DFP long register into a decimal64 structure */
/* */
/* Input: */
/* rn FP register number */
/* xp Pointer to decimal64 structure */
/* regs CPU register context */
/*-------------------------------------------------------------------*/
static inline void
ARCH_DEP(dfp_reg_to_decimal64) (int rn, decimal64 *xp, REGS *regs)
{
int i; /* FP register subscript */
DW *dwp; /* Doubleword pointer */
i = FPR2I(rn); /* Register index */
dwp = (DW*)xp; /* Convert to DW pointer */
dwp->F.H.F = regs->fpr[i]; /* Copy FPR bits 0-31 */
dwp->F.L.F = regs->fpr[i+1]; /* Copy FPR bits 32-63 */
} /* end function dfp_reg_to_decimal64 */
/*-------------------------------------------------------------------*/
/* Load a DFP long register from a decimal64 structure */
/* */
/* Input: */
/* rn FP register number (left register of pair) */
/* xp Pointer to decimal64 structure */
/* regs CPU register context */
/*-------------------------------------------------------------------*/
static inline void
ARCH_DEP(dfp_reg_from_decimal64) (int rn, decimal64 *xp, REGS *regs)
{
int i; /* FP register subscript */
DW *dwp; /* Doubleword pointer */
i = FPR2I(rn); /* Register index */
dwp = (DW*)xp; /* Convert to DW pointer */
regs->fpr[i] = dwp->F.H.F; /* Load FPR bits 0-31 */
regs->fpr[i+1] = dwp->F.L.F; /* Load FPR bits 32-63 */
} /* end function dfp_reg_from_decimal64 */
/*-------------------------------------------------------------------*/
/* Copy a DFP extended register into a decimal128 structure */
/* */
/* Input: */
/* rn FP register number (left register of pair) */
/* xp Pointer to decimal128 structure */
/* regs CPU register context */
/*-------------------------------------------------------------------*/
static inline void
ARCH_DEP(dfp_reg_to_decimal128) (int rn, decimal128 *xp, REGS *regs)
{
int i, j; /* FP register subscripts */
QW *qwp; /* Quadword pointer */
i = FPR2I(rn); /* Left register index */
j = i + FPREX; /* Right register index */
qwp = (QW*)xp; /* Convert to QW pointer */
qwp->F.HH.F = regs->fpr[i]; /* Copy FPR bits 0-31 */
qwp->F.HL.F = regs->fpr[i+1]; /* Copy FPR bits 32-63 */
qwp->F.LH.F = regs->fpr[j]; /* Copy FPR bits 64-95 */
qwp->F.LL.F = regs->fpr[j+1]; /* Copy FPR bits 96-127 */
} /* end function dfp_reg_to_decimal128 */
/*-------------------------------------------------------------------*/
/* Load a DFP extended register from a decimal128 structure */
/* */
/* Input: */
/* rn FP register number (left register of pair) */
/* xp Pointer to decimal128 structure */
/* regs CPU register context */
/*-------------------------------------------------------------------*/
static inline void
ARCH_DEP(dfp_reg_from_decimal128) (int rn, decimal128 *xp, REGS *regs)
{
int i, j; /* FP register subscripts */