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control.c
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/* CONTROL.C (c) Copyright Roger Bowler, 1994-2004 */
/* ESA/390 CPU Emulator */
/* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2004 */
/* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2004 */
/*-------------------------------------------------------------------*/
/* This module implements all control instructions of the */
/* S/370 and ESA/390 architectures, as described in the manuals */
/* GA22-7000-03 System/370 Principles of Operation */
/* SA22-7201-06 ESA/390 Principles of Operation */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Additional credits: */
/* Bad frame support by Jan Jaeger */
/* Branch tracing by Jan Jaeger */
/* CSP instructions by Jan Jaeger */
/* Instruction decode by macros - Jan Jaeger */
/* Prevent TOD from going backwards in time - Jan Jaeger */
/* Instruction decode rework - Jan Jaeger */
/* PR may lose pending interrupts - Jan Jaeger */
/* Modifications for Interpretive Execution (SIE) by Jan Jaeger */
/* ESAME low-address protection - Roger Bowler */
/* ESAME linkage stack operations - Roger Bowler */
/* ESAME BSA instruction - Roger Bowler v209c*/
/*-------------------------------------------------------------------*/
#include "hercules.h"
#include "opcode.h"
#include "inline.h"
#if defined(OPTION_FISHIO)
#include "w32chan.h"
#endif // defined(OPTION_FISHIO)
#if defined(FEATURE_BRANCH_AND_SET_AUTHORITY)
/*-------------------------------------------------------------------*/
/* B25A BSA - Branch and Set Authority [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(branch_and_set_authority)
{
int r1, r2; /* Values of R fields */
U32 ducto; /* DUCT origin */
U32 duct_pkrp; /* DUCT PKM/Key/RA/P word */
RADR duct_reta; /* DUCT return address/amode */
BYTE key; /* New PSW key */
#ifdef FEATURE_TRACING
CREG newcr12 = 0; /* CR12 upon completion */
#endif /*FEATURE_TRACING*/
RRE(inst, regs, r1, r2);
/* Special operation exception if ASF is not enabled */
if (!ASF_ENABLED(regs))
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
#if defined(_FEATURE_SIE)
if(SIE_STATB(regs, IC1, BSA))
longjmp(regs->progjmp, SIE_INTERCEPT_INST);
#endif /*defined(_FEATURE_SIE)*/
/* Load real address of dispatchable unit control table */
ducto = regs->CR(2) & CR2_DUCTO;
/* Apply low-address protection to stores into the DUCT */
if (ARCH_DEP(is_low_address_protected) (ducto, 0, regs))
{
#ifdef FEATURE_SUPPRESSION_ON_PROTECTION
regs->TEA = (ducto & STORAGE_KEY_PAGEMASK);
regs->excarid = 0;
#endif /*FEATURE_SUPPRESSION_ON_PROTECTION*/
ARCH_DEP(program_interrupt) (regs, PGM_PROTECTION_EXCEPTION);
}
/* Convert DUCT real address to absolute address */
ducto = APPLY_PREFIXING (ducto, regs->PX);
/* Program check if DUCT origin address is invalid */
if (ducto > regs->mainlim)
ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
#if defined(FEATURE_ESAME)
/* For ESAME, load the PKM/Key/RA/P from DUCT word 5, and load
the return address and amode from DUCT words 8 and 9
(note: the DUCT cannot cross a page boundary) */
duct_pkrp = ARCH_DEP(fetch_fullword_absolute) (ducto+20, regs);
duct_reta = ARCH_DEP(fetch_doubleword_absolute) (ducto+32, regs);
#else /*!defined(FEATURE_ESAME)*/
/* For ESA/390, load the PKM/Key/RA/P from DUCT word 9, and load
the return address and amode from DUCT word 8
(note: the DUCT cannot cross a page boundary) */
duct_pkrp = ARCH_DEP(fetch_fullword_absolute) (ducto+36, regs);
duct_reta = ARCH_DEP(fetch_fullword_absolute) (ducto+32, regs);
#endif /*!defined(FEATURE_ESAME)*/
/* Perform base authority or reduced authority operation */
if ((duct_pkrp & DUCT_RA) == 0)
{
/* In base authority state R2 cannot specify register zero */
if (r2 == 0)
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
#ifdef FEATURE_TRACING
/* Perform tracing */
if (regs->CR(12) & CR12_BRTRACE)
newcr12 = ARCH_DEP(trace_br) (regs->GR_L(r2) & 0x80000000,
regs->GR_L(r2), regs);
#endif /*FEATURE_TRACING*/
/* Obtain the new PSW key from R1 register bits 24-27 */
key = regs->GR_L(r1) & 0x000000F0;
/* Privileged operation exception if in problem state and
current PSW key mask does not permit new key value */
if (PROBSTATE(®s->psw)
&& ((regs->CR(3) << (key >> 4)) & 0x80000000) == 0 )
ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
/* Save current PSW amode and instruction address */
#if defined(FEATURE_ESAME)
if (regs->psw.amode64)
{
duct_reta = regs->psw.IA;
}
else
#endif /*!defined(FEATURE_ESAME)*/
{
duct_reta = regs->psw.IA & DUCT_IA31;
if (regs->psw.amode) duct_reta |= DUCT_AM31;
}
/* Save current PSW key mask, PSW key, and problem state */
duct_pkrp = (regs->CR(3) & CR3_KEYMASK) | regs->psw.pkey;
if (PROBSTATE(®s->psw)) duct_pkrp |= DUCT_PROB;
/* Set the reduced authority bit */
duct_pkrp |= DUCT_RA;
#if defined(FEATURE_ESAME)
/* For ESAME, store the PKM/Key/RA/P into DUCT word 5, and
store the return address and amode into DUCT words 8 and 9
(note: the DUCT cannot cross a page boundary) */
ARCH_DEP(store_fullword_absolute) (duct_pkrp, ducto+20, regs);
ARCH_DEP(store_doubleword_absolute) (duct_reta, ducto+32, regs);
#else /*!defined(FEATURE_ESAME)*/
/* For ESA/390, store the PKM/Key/RA/P into DUCT word 9, and
store the return address and amode into DUCT word 8
(note: the DUCT cannot cross a page boundary) */
ARCH_DEP(store_fullword_absolute) (duct_pkrp, ducto+36, regs);
ARCH_DEP(store_fullword_absolute) (duct_reta, ducto+32, regs);
#endif /*!defined(FEATURE_ESAME)*/
/* Load new PSW key and PSW key mask from R1 register */
regs->psw.pkey = key;
regs->CR_LHH(3) &= regs->GR_LHH(r1);
/* Set the problem state bit in the current PSW */
regs->psw.states |= BIT(PSW_PROB_BIT);
/* Set PSW instruction address and amode from R2 register */
#if defined(FEATURE_ESAME)
if (regs->psw.amode64)
{
regs->psw.IA = regs->GR_G(r2);
}
else
#endif /*defined(FEATURE_ESAME)*/
if (regs->GR_L(r2) & 0x80000000)
{
#if defined(FEATURE_ESAME)
regs->psw.amode64 = 0;
#endif /*defined(FEATURE_ESAME)*/
regs->psw.amode = 1;
regs->psw.AMASK = AMASK31;
regs->psw.IA = regs->GR_L(r2) & AMASK31;
}
else
{
#if defined(FEATURE_ESAME)
regs->psw.amode64 =
#endif /*defined(FEATURE_ESAME)*/
regs->psw.amode = 0;
regs->psw.AMASK = AMASK24;
regs->psw.IA = regs->GR_L(r2) & AMASK24;
}
} /* end if(BSA-ba) */
else
{ /* BSA-ra */
/* In reduced authority state R2 must specify register zero */
if (r2 != 0)
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
#ifdef FEATURE_TRACING
/* Perform tracing */
if (regs->CR(12) & CR12_BRTRACE)
newcr12 = ARCH_DEP(trace_br) (duct_reta & DUCT_AM31,
duct_reta &DUCT_IA31, regs);
#endif /*FEATURE_TRACING*/
/* If R1 is non-zero, save the current PSW addressing mode
and instruction address in the R1 register */
if (r1 != 0)
{
#if defined(FEATURE_ESAME)
if (regs->psw.amode64)
{
regs->GR_G(r1) = regs->psw.IA;
}
else
#endif /*defined(FEATURE_ESAME)*/
{
regs->GR_L(r1) = regs->psw.IA;
if (regs->psw.amode) regs->GR_L(r1) |= 0x80000000;
}
}
/* Restore PSW amode and instruction address from the DUCT */
#if defined(FEATURE_ESAME)
if (regs->psw.amode64)
{
regs->psw.IA = duct_reta;
}
else
#endif /*defined(FEATURE_ESAME)*/
{
regs->psw.IA = duct_reta & DUCT_IA31;
regs->psw.amode = (duct_reta & DUCT_AM31) ? 1 : 0;
regs->psw.AMASK = regs->psw.amode ? AMASK31 : AMASK24;
}
/* Restore the PSW key mask from the DUCT */
regs->CR(3) &= 0x0000FFFF;
regs->CR(3) |= duct_pkrp & DUCT_PKM;
/* Restore the PSW key from the DUCT */
regs->psw.pkey = duct_pkrp & DUCT_KEY;
/* Restore the problem state bit from the DUCT */
if (duct_pkrp & DUCT_PROB)
regs->psw.states |= BIT(PSW_PROB_BIT);
else
regs->psw.states &= ~BIT(PSW_PROB_BIT);
/* Reset the reduced authority bit in the DUCT */
duct_pkrp &= ~DUCT_RA;
#if defined(FEATURE_ESAME)
ARCH_DEP(store_fullword_absolute) (duct_pkrp, ducto+20, regs);
#else /*!defined(FEATURE_ESAME)*/
ARCH_DEP(store_fullword_absolute) (duct_pkrp, ducto+36, regs);
#endif /*!defined(FEATURE_ESAME)*/
/* Specification exception if the PSW is now invalid */
if ((regs->psw.IA & 1)
#if defined(FEATURE_ESAME)
|| (regs->psw.amode64 == 0 && regs->psw.amode == 1
&& regs->psw.IA > 0x7FFFFFFF)
|| (regs->psw.amode64 == 0 && regs->psw.amode == 0
&& regs->psw.IA > 0x00FFFFFF))
#else /*!defined(FEATURE_ESAME)*/
|| (regs->psw.amode == 0 && regs->psw.IA > 0x00FFFFFF))
#endif /*!defined(FEATURE_ESAME)*/
{
regs->psw.ilc = 0;
ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
}
} /* end if(BSA-ra) */
INVALIDATE_AIA(regs);
INVALIDATE_AEA_ALL(regs);
#ifdef FEATURE_TRACING
/* Update trace table address if branch tracing is on */
if (regs->CR(12) & CR12_BRTRACE)
regs->CR(12) = newcr12;
#endif /*FEATURE_TRACING*/
#if defined(FEATURE_PER)
if( EN_IC_PER_SB(regs)
#if defined(FEATURE_PER2)
&& ( !(regs->CR(9) & CR9_BAC)
|| PER_RANGE_CHECK(regs->psw.IA,regs->CR(10),regs->CR(11)) )
#endif /*defined(FEATURE_PER2)*/
)
ON_IC_PER_SB(regs);
#endif /*defined(FEATURE_PER)*/
}
#endif /*defined(FEATURE_BRANCH_AND_SET_AUTHORITY)*/
#if defined(FEATURE_SUBSPACE_GROUP)
/*-------------------------------------------------------------------*/
/* B258 BSG - Branch in Subspace Group [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(branch_in_subspace_group)
{
int r1, r2; /* Values of R fields */
U32 alet; /* Destination subspace ALET */
U32 dasteo; /* Destination ASTE origin */
U32 daste[16]; /* ASN second table entry */
RADR ducto; /* DUCT origin */
U32 duct0; /* DUCT word 0 */
U32 duct1; /* DUCT word 1 */
U32 duct3; /* DUCT word 3 */
RADR abs; /* Absolute address */
BYTE *main; /* Mainstor address */
VADR newia; /* New instruction address */
U16 xcode; /* Exception code */
#ifdef FEATURE_TRACING
CREG newcr12 = 0; /* CR12 upon completion */
#endif /*FEATURE_TRACING*/
RRE(inst, regs, r1, r2);
SIE_MODE_XC_OPEX(regs);
/* Special operation exception if DAT is off or ASF not enabled */
if (REAL_MODE(&(regs->psw))
|| !ASF_ENABLED(regs))
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
#ifdef FEATURE_TRACING
/* Perform tracing */
if (regs->CR(12) & CR12_ASNTRACE)
newcr12 = ARCH_DEP(trace_bsg) ((r2 == 0) ? 0 : regs->AR(r2),
regs->GR_L(r2), regs);
else
if (regs->CR(12) & CR12_BRTRACE)
newcr12 = ARCH_DEP(trace_br) (regs->GR_L(r2) & 0x80000000,
regs->GR_L(r2), regs);
#endif /*FEATURE_TRACING*/
/* Load real address of dispatchable unit control table */
ducto = regs->CR(2) & CR2_DUCTO;
/* Apply low-address protection to stores into the DUCT */
if (ARCH_DEP(is_low_address_protected) (ducto, 0, regs))
{
#ifdef FEATURE_SUPPRESSION_ON_PROTECTION
regs->TEA = (ducto & STORAGE_KEY_PAGEMASK);
regs->excarid = 0;
#endif /*FEATURE_SUPPRESSION_ON_PROTECTION*/
ARCH_DEP(program_interrupt) (regs, PGM_PROTECTION_EXCEPTION);
}
/* Convert DUCT real address to absolute address */
ducto = APPLY_PREFIXING (ducto, regs->PX);
/* Program check if DUCT origin address is invalid */
if (ducto > regs->mainlim)
ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
/* Fetch DUCT words 0, 1, and 3 from absolute storage
(note: the DUCT cannot cross a page boundary) */
main = FETCH_MAIN_ABSOLUTE (ducto, regs, 16);
duct0 = fetch_fw (main);
duct1 = fetch_fw (main+4);
duct3 = fetch_fw (main+12);
/* Special operation exception if the current primary ASTE origin
is not the same as the base ASTE for the dispatchable unit */
if ((regs->CR_L(5) & CR5_PASTEO) != (duct0 & DUCT0_BASTEO))
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
/* Obtain the destination ALET from the R2 access register,
except that register zero means destination ALET is zero */
alet = (r2 == 0) ? 0 : regs->AR(r2);
/* Perform special ALET translation to obtain destination ASTE */
switch (alet) {
case ALET_PRIMARY: /* Branch to base space */
/* Load the base space ASTE origin from the DUCT */
dasteo = duct0 & DUCT0_BASTEO;
/* Convert the ASTE origin to an absolute address */
abs = APPLY_PREFIXING (dasteo, regs->PX);
/* Program check if ASTE origin address is invalid */
if (abs > regs->mainlim)
ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
/* Fetch destination ASTE words 2 and 3 from absolute storage
(note: the ASTE cannot cross a page boundary) */
main = FETCH_MAIN_ABSOLUTE (abs, regs, 16);
daste[2] = fetch_fw (main+8);
daste[3] = fetch_fw (main+12);
break;
case ALET_SECONDARY: /* Branch to last-used subspace */
/* Load the subspace ASTE origin from the DUCT */
dasteo = duct1 & DUCT1_SSASTEO;
/* Special operation exception if SSASTEO is zero */
if (dasteo == 0)
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
/* Convert the ASTE origin to an absolute address */
abs = APPLY_PREFIXING (dasteo, regs->PX);
/* Program check if ASTE origin address is invalid */
if (abs > regs->mainlim)
ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
/* Fetch subspace ASTE words 0, 2, 3, and 5 from absolute
storage (note: the ASTE cannot cross a page boundary) */
main = FETCH_MAIN_ABSOLUTE (abs, regs, 24);
daste[0] = fetch_fw (main);
daste[2] = fetch_fw (main+8);
daste[3] = fetch_fw (main+12);
daste[5] = fetch_fw (main+20);
/* ASTE validity exception if ASTE invalid bit is one */
if (daste[0] & ASTE0_INVALID)
{
regs->excarid = r2;
ARCH_DEP(program_interrupt) (regs, PGM_ASTE_VALIDITY_EXCEPTION);
}
/* ASTE sequence exception if the subspace ASTE sequence
number does not match the sequence number in the DUCT */
if ((daste[5] & ASTE5_ASTESN) != (duct3 & DUCT3_SSASTESN))
{
regs->excarid = r2;
ARCH_DEP(program_interrupt) (regs, PGM_ASTE_SEQUENCE_EXCEPTION);
}
break;
default: /* ALET not 0 or 1 */
/* Perform special ART to obtain destination ASTE */
xcode = ARCH_DEP(translate_alet) (alet, 0, ACCTYPE_BSG, regs,
&dasteo, daste);
/* Program check if ALET translation error */
if (xcode != 0)
{
regs->excarid = r2;
ARCH_DEP(program_interrupt) (regs, xcode);
}
/* Special operation exception if the destination ASTE
is the base space of a different subspace group */
if (dasteo != (duct0 & DUCT0_BASTEO)
&& ((ASTE_AS_DESIGNATOR(daste) & SSGROUP_BIT) == 0
|| (daste[0] & ASTE0_BASE) ))
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
} /* end switch(alet) */
/* Update the primary STD (or ASCE) from the destination ASTE */
if ((dasteo == (duct0 & DUCT0_BASTEO)) && (alet != ALET_SECONDARY))
{
/* When the destination ASTE is the base space, replace the
primary STD (or ASCE) by the STD (or ASCE) in the ASTE */
regs->CR(1) = ASTE_AS_DESIGNATOR(daste);
}
else
{
/* When the destination ASTE is a subspace, replace
the primary STD or ASCE by the STD or ASTE in the
ASTE, except for the space-switch event and storage
alteration event bits, which remain unchanged */
regs->CR(1) &= (SSEVENT_BIT | SAEVENT_BIT);
regs->CR(1) |= (ASTE_AS_DESIGNATOR(daste)
& ~((RADR)(SSEVENT_BIT | SAEVENT_BIT)));
}
/* Compute the branch address from the R2 operand */
newia = regs->GR(r2);
/* If R1 is non-zero, save the current PSW addressing mode
and instruction address in the R1 register */
if (r1 != 0)
{
#if defined(FEATURE_ESAME)
if (regs->psw.amode64)
regs->GR_G(r1) = regs->psw.IA;
else
#endif /*!defined(FEATURE_ESAME)*/
regs->GR_L(r1) = regs->psw.IA |
(regs->psw.amode ? 0x80000000 : 0);
}
/* Set mode and branch to address specified by R2 operand */
regs->psw.IA = newia;
#if defined(FEATURE_ESAME)
if (regs->psw.amode64 == 0 && (newia & 0x80000000))
#else /*!defined(FEATURE_ESAME)*/
if (newia & 0x80000000)
#endif /*!defined(FEATURE_ESAME)*/
{
regs->psw.amode = 1;
regs->psw.AMASK = AMASK31;
regs->psw.IA = newia & AMASK31;
}
else
{
regs->psw.amode = 0;
regs->psw.AMASK = AMASK24;
regs->psw.IA = newia & AMASK24;
}
/* Set the SSTD (or SASCE) equal to PSTD (or PASCE) */
regs->CR(7) = regs->CR(1);
/* Set SASN equal to PASN */
regs->CR_LHL(3) = regs->CR_LHL(4);
/* Reset the subspace fields in the DUCT */
if (alet == ALET_SECONDARY)
{
/* When the destination ASTE specifies a subspace by means
of ALET 1, set the subspace active bit in the DUCT */
duct1 |= DUCT1_SA;
ARCH_DEP(store_fullword_absolute) (duct1, ducto+4, regs);
}
else if (dasteo == (duct0 & DUCT0_BASTEO))
{
/* When the destination ASTE is the base space,
reset the subspace active bit in the DUCT */
duct1 &= ~DUCT1_SA;
ARCH_DEP(store_fullword_absolute) (duct1, ducto+4, regs);
}
else
{
/* When the destination ASTE specifies a subspace by means
of an ALET other than ALET 1, set the subspace active
bit and store the subspace ASTE origin in the DUCT */
duct1 = DUCT1_SA | dasteo;
ARCH_DEP(store_fullword_absolute) (duct1, ducto+4, regs);
/* Set the subspace ASTE sequence number in the DUCT
equal to the destination ASTE sequence number */
duct3 = daste[5];
ARCH_DEP(store_fullword_absolute) (duct3, ducto+12, regs);
}
#ifdef FEATURE_TRACING
/* Update trace table address if ASN tracing or branch tracing */
if (regs->CR(12) & (CR12_ASNTRACE | CR12_BRTRACE))
regs->CR(12) = newcr12;
#endif /*FEATURE_TRACING*/
INVALIDATE_AIA(regs);
INVALIDATE_AEA_ALL(regs);
#if defined(FEATURE_PER)
if( EN_IC_PER_SB(regs)
#if defined(FEATURE_PER2)
&& ( !(regs->CR(9) & CR9_BAC)
|| PER_RANGE_CHECK(regs->psw.IA,regs->CR(10),regs->CR(11)) )
#endif /*defined(FEATURE_PER2)*/
)
ON_IC_PER_SB(regs);
#endif /*defined(FEATURE_PER)*/
}
#endif /*defined(FEATURE_SUBSPACE_GROUP)*/
#if defined(FEATURE_LINKAGE_STACK)
/*-------------------------------------------------------------------*/
/* B240 BAKR - Branch and Stack Register [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(branch_and_stack)
{
int r1, r2; /* Values of R fields */
VADR n1, n2; /* Operand values */
#ifdef FEATURE_TRACING
VADR n = 0; /* Work area */
#endif /*FEATURE_TRACING*/
RRE(inst, regs, r1, r2);
SIE_MODE_XC_OPEX(regs);
#if defined(_FEATURE_SIE)
if(SIE_STATB(regs, IC3, BAKR))
longjmp(regs->progjmp, SIE_INTERCEPT_INST);
#endif /*defined(_FEATURE_SIE)*/
/* [5.12.3]/ Fig 10-2 Special operation exception if ASF is not enabled,
or if DAT is off, or if not primary-space mode or AR-mode */
if (!ASF_ENABLED(regs)
|| REAL_MODE(®s->psw)
|| SPACE_BIT(®s->psw))
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
/* Obtain the return address and addressing mode from
the R1 register, or use updated PSW if R1 is zero */
if ( r1 != 0 )
{
n1 = regs->GR(r1);
#if defined(FEATURE_ESAME)
if ( (n1 & 0x01) == 0 )
n1 &= (n1 & 0x80000000) ? 0xFFFFFFFF : 0x00FFFFFF;
#else /*!defined(FEATURE_ESAME)*/
if ( (n1 & 0x80000000) == 0 )
n1 &= 0x00FFFFFF;
#endif /*!defined(FEATURE_ESAME)*/
}
else
{
n1 = regs->psw.IA;
#if defined(FEATURE_ESAME)
if ( regs->psw.amode64 )
n1 |= 0x01;
else
#endif /*defined(FEATURE_ESAME)*/
if ( regs->psw.amode )
n1 |= 0x80000000;
}
/* Obtain the branch address from the R2 register, or use
the updated PSW instruction address if R2 is zero */
n2 = (r2 != 0) ? regs->GR(r2) : regs->psw.IA;
n2 &= ADDRESS_MAXWRAP(regs);
/* Set the addressing mode bit in the branch address */
#if defined(FEATURE_ESAME)
if ( regs->psw.amode64 )
n2 |= 0x01;
else
#endif /*defined(FEATURE_ESAME)*/
if ( regs->psw.amode )
n2 |= 0x80000000;
#ifdef FEATURE_TRACING
/* Form the branch trace entry */
if((regs->CR(12) & CR12_BRTRACE) && (r2 != 0))
n = ARCH_DEP(trace_br)(regs->psw.amode, regs->GR_L(r2), regs);
#endif /*FEATURE_TRACING*/
/* Form the linkage stack entry */
ARCH_DEP(form_stack_entry) (LSED_UET_BAKR, n1, n2, 0, 0, regs);
#ifdef FEATURE_TRACING
/* Update CR12 to reflect the new branch trace entry */
if((regs->CR(12) & CR12_BRTRACE) && (r2 != 0))
regs->CR(12) = n;
#endif /*FEATURE_TRACING*/
/* Execute the branch unless R2 specifies register 0 */
if ( r2 != 0 )
{
regs->psw.IA = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
#if defined(FEATURE_PER)
if( EN_IC_PER_SB(regs)
#if defined(FEATURE_PER2)
&& ( !(regs->CR(9) & CR9_BAC)
|| PER_RANGE_CHECK(regs->psw.IA,regs->CR(10),regs->CR(11)) )
#endif /*defined(FEATURE_PER2)*/
)
ON_IC_PER_SB(regs);
#endif /*defined(FEATURE_PER)*/
}
}
#endif /*defined(FEATURE_LINKAGE_STACK)*/
#if defined(FEATURE_BROADCASTED_PURGING)
/*-------------------------------------------------------------------*/
/* B250 CSP - Compare and Swap and Purge [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(compare_and_swap_and_purge)
{
int r1, r2; /* Values of R fields */
U64 n2; /* virtual address of op2 */
BYTE *main2; /* mainstor address of op2 */
U32 old; /* old value */
RRE(inst, regs, r1, r2);
PRIV_CHECK(regs);
ODD_CHECK(r1, regs);
#if defined(_FEATURE_SIE)
if(SIE_STATB(regs,IC0, IPTECSP))
longjmp(regs->progjmp, SIE_INTERCEPT_INST);
#endif /*defined(_FEATURE_SIE)*/
#if defined(_FEATURE_SIE)
if(SIE_MODE(regs) && regs->sie_scao)
{
STORAGE_KEY(regs->sie_scao, regs) |= STORKEY_REF;
if(regs->mainstor[regs->sie_scao] & 0x80)
longjmp(regs->progjmp, SIE_INTERCEPT_INST);
}
#endif /*defined(_FEATURE_SIE)*/
/* Perform serialization before starting operation */
PERFORM_SERIALIZATION (regs);
/* Obtain 2nd operand address from r2 */
n2 = regs->GR(r2) & 0xFFFFFFFFFFFFFFFCULL & ADDRESS_MAXWRAP(regs);
main2 = MADDR (n2, r2, regs, ACCTYPE_WRITE, regs->psw.pkey);
old = CSWAP32 (regs->GR_L(r1));
/* Obtain main-storage access lock */
OBTAIN_MAINLOCK(regs);
/* Attempt to exchange the values */
regs->psw.cc = cmpxchg4 (&old, CSWAP32(regs->GR_L(r1+1)), main2);
/* Release main-storage access lock */
RELEASE_MAINLOCK(regs);
if (regs->psw.cc == 0)
{
/* Perform requested funtion specified as per request code in r2 */
if (regs->GR_L(r2) & 3)
{
obtain_lock (&sysblk.intlock);
ARCH_DEP(synchronize_broadcast)(regs, regs->GR_L(r2) & 3, 0);
release_lock (&sysblk.intlock);
}
}
else
{
/* Otherwise yield */
regs->GR_L(r1) = CSWAP32(old);
if (sysblk.cpus > 1)
sched_yield();
}
/* Perform serialization after completing operation */
PERFORM_SERIALIZATION (regs);
}
#endif /*defined(FEATURE_BROADCASTED_PURGING)*/
/*-------------------------------------------------------------------*/
/* 83 DIAG - Diagnose */
/*-------------------------------------------------------------------*/
DEF_INST(diagnose)
{
int r1, r3; /* Register numbers */
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
RS(inst, regs, r1, r3, b2, effective_addr2);
#if defined(FEATURE_ECPSVM)
if(ecpsvm_dodiag(regs,r1,r3,b2,effective_addr2)==0)
{
return;
}
#endif
#ifdef FEATURE_HERCULES_DIAGCALLS
if (
#if defined(_FEATURE_SIE)
!SIE_MODE(regs) &&
#endif /* defined(_FEATURE_SIE) */
effective_addr2 != 0xF08)
#endif
PRIV_CHECK(regs);
SIE_INTERCEPT(regs);
/* Process diagnose instruction */
ARCH_DEP(diagnose_call) (effective_addr2, b2, r1, r3, regs);
/* Perform serialization and checkpoint-synchronization */
PERFORM_SERIALIZATION (regs);
PERFORM_CHKPT_SYNC (regs);
#ifdef FEATURE_HERCULES_DIAGCALLS
RETURN_INTCHECK(regs);
#endif
}
#if defined(FEATURE_DUAL_ADDRESS_SPACE)
/*-------------------------------------------------------------------*/
/* B226 EPAR - Extract Primary ASN [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(extract_primary_asn)
{
int r1, r2; /* Values of R fields */
RRE(inst, regs, r1, r2);
SIE_MODE_XC_OPEX(regs);
/* Special operation exception if DAT is off */
if ( (regs->psw.sysmask & PSW_DATMODE) == 0 )
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
/* Privileged operation exception if in problem state
and the extraction-authority control bit is zero */
if ( PROBSTATE(®s->psw)
&& (regs->CR(0) & CR0_EXT_AUTH) == 0 )
ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
/* Load R1 with PASN from control register 4 bits 16-31 */
regs->GR_L(r1) = regs->CR_LHL(4);
}
#endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
#if defined(FEATURE_DUAL_ADDRESS_SPACE)
/*-------------------------------------------------------------------*/
/* B227 ESAR - Extract Secondary ASN [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(extract_secondary_asn)
{
int r1, r2; /* Values of R fields */
RRE(inst, regs, r1, r2);
SIE_MODE_XC_OPEX(regs);
/* Special operation exception if DAT is off */
if ( (regs->psw.sysmask & PSW_DATMODE) == 0 )
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
/* Privileged operation exception if in problem state
and the extraction-authority control bit is zero */
if ( PROBSTATE(®s->psw)
&& (regs->CR(0) & CR0_EXT_AUTH) == 0 )
ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
/* Load R1 with SASN from control register 3 bits 16-31 */
regs->GR_L(r1) = regs->CR_LHL(3);
}
#endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
#if defined(FEATURE_LINKAGE_STACK)
/*-------------------------------------------------------------------*/
/* B249 EREG - Extract Stacked Registers [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(extract_stacked_registers)
{
int r1, r2; /* Values of R fields */
LSED lsed; /* Linkage stack entry desc. */
VADR lsea; /* Linkage stack entry addr */
RRE(inst, regs, r1, r2);
SIE_MODE_XC_OPEX(regs);
/* Find the virtual address of the entry descriptor
of the current state entry in the linkage stack */
lsea = ARCH_DEP(locate_stack_entry) (0, &lsed, regs);
/* Load registers from the stack entry */
ARCH_DEP(unstack_registers) (0, lsea, r1, r2, regs);
if (r1 == r2)
INVALIDATE_AEA_AR(r1, regs);
else
INVALIDATE_AEA_ARALL(regs);
}
#endif /*defined(FEATURE_LINKAGE_STACK)*/
#if defined(FEATURE_LINKAGE_STACK)
/*-------------------------------------------------------------------*/
/* B24A ESTA - Extract Stacked State [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(extract_stacked_state)
{
int r1, r2; /* Values of R fields */
BYTE code; /* Extraction code */
LSED lsed; /* Linkage stack entry desc. */
VADR lsea; /* Linkage stack entry addr */
#undef MAX_ESTA_CODE
#if defined(FEATURE_ESAME)
#define MAX_ESTA_CODE 4
#else /*!defined(FEATURE_ESAME)*/
#define MAX_ESTA_CODE 3
#endif /*!defined(FEATURE_ESAME)*/
RRE(inst, regs, r1, r2);
SIE_MODE_XC_OPEX(regs);
if (REAL_MODE(®s->psw)
|| SECONDARY_SPACE_MODE(®s->psw)
|| !ASF_ENABLED(regs))
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
/* Load the extraction code from low-order byte of R2 register */
code = regs->GR_LHLCL(r2);
/* Program check if r1 is odd, or if extraction code is invalid */
if ((r1 & 1) || code > MAX_ESTA_CODE)
ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
/* Find the virtual address of the entry descriptor
of the current state entry in the linkage stack */
lsea = ARCH_DEP(locate_stack_entry) (0, &lsed, regs);
/* Load general register pair from state entry */
ARCH_DEP(stack_extract) (lsea, r1, code, regs);
/* Set condition code depending on entry type */
regs->psw.cc = ((lsed.uet & LSED_UET_ET) == LSED_UET_PC) ? 1 : 0;
}
#endif /*defined(FEATURE_LINKAGE_STACK)*/
#if defined(FEATURE_DUAL_ADDRESS_SPACE)
/*-------------------------------------------------------------------*/
/* B224 IAC - Insert Address Space Control [RRE] */
/*-------------------------------------------------------------------*/
DEF_INST(insert_address_space_control)
{
int r1, r2; /* Values of R fields */
RRE(inst, regs, r1, r2);
/* Special operation exception if DAT is off */
if ( REAL_MODE(&(regs->psw))
#if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
/* Except in XC mode */
&& !SIE_STATB(regs, MX, XC)
#endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
)
ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
/* Privileged operation exception if in problem state
and the extraction-authority control bit is zero */
if ( PROBSTATE(®s->psw)
&& !(regs->CR(0) & CR0_EXT_AUTH)
#if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
/* Ignore extraction control in XC mode */
&& !SIE_STATB(regs, MX, XC)
#endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
)
ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
/* Extract the address-space control bits from the PSW */
regs->psw.cc = (AR_BIT(®s->psw) << 1) | SPACE_BIT(®s->psw);
/* Insert address-space mode into register bits 22-23 */
regs->GR_LHLCH(r1) = regs->psw.cc;
}
#endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
/*-------------------------------------------------------------------*/
/* B20B IPK - Insert PSW Key [S] */
/*-------------------------------------------------------------------*/
DEF_INST(insert_psw_key)
{
int b2; /* Base of effective addr */
VADR effective_addr2; /* Effective address */
S(inst, regs, b2, effective_addr2);
/* Privileged operation exception if in problem state
and the extraction-authority control bit is zero */
if ( PROBSTATE(®s->psw)
&& (regs->CR(0) & CR0_EXT_AUTH) == 0 )
ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
/* Insert PSW key into bits 24-27 of general register 2
and set bits 28-31 of general register 2 to zero */
regs->GR_LHLCL(2) = regs->psw.pkey & 0xF0;
}
#if defined(FEATURE_BASIC_STORAGE_KEYS)
/*-------------------------------------------------------------------*/
/* 09 ISK - Insert Storage Key [RR] */
/*-------------------------------------------------------------------*/
DEF_INST(insert_storage_key)
{
int r1, r2; /* Values of R fields */
RADR n; /* Absolute storage addr */
#if defined(_FEATURE_SIE)
BYTE storkey;
#endif /*defined(_FEATURE_SIE)*/