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ecpsvm.c
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ecpsvm.c
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/***********************************************************/
/* HERCULES ECPS:VM Support */
/* (c) Copyright 2003-2006 Roger Bowler and Others */
/* Use of this program is governed by the QPL License */
/* Original Author : Ivan Warren */
/* Prime Maintainer : Ivan Warren */
/* */
/* General guidelines about E6XX instruction class */
/* this is an implementation of ECPS:VM Level 20 */
/* */
/* General rule is : Only do what is safe to do. In doubt, */
/* give control to CP back (and act as */
/* a NO-OP). All instructions have this */
/* behaviour, therefore allowing only */
/* partial implementation, or bypassing */
/* tricky cases */
/* */
/* NOTE : ECPS:VM is only available for S/370 architecture */
/* */
/* In order for CP ASSIST to be active, a CONFIGURATION */
/* statement is added : ECPS:VM lvl|no */
/* lvl is the ASSIST level (20 is recommended) */
/* no means CP ASSIST is disabled (default) */
/* */
/* Currently supported CP ASSIST instructions : */
/* +-----+-------+----------------------------------------+*/
/* |opc | Mnemo | Function |*/
/* +-----+-------+----------------------------------------+*/
/* |E602 | LCKPG | Lock Page in core table |*/
/* |E603 | ULKPG | Unlock page in core table |*/
/* |E608 | TRBRG | LRA + Basic checks on VPAGE |*/
/* |E609 | TRLOK | Same as TRBRG + Lock page in core |*/
/* |E60E | SCNRU | Scan Real Unit control blocks |*/
/* |E612 | STLVL | Store ECPS:VM Level |*/
/* |E614 | FREEX | Allocate CP FREE Storage from subpool |*/
/* |E615 | FRETX | Release CP FREE Storage to subpool |*/
/* +-----+-------+----------------------------------------+*/
/* */
/* Currently supported VM ASSIST instructions : */
/* +-----+-------+----------------------------------------+*/
/* |opc | Mnemo | Function |*/
/* +-----+-------+----------------------------------------+*/
/* |0A | SVC | Virtual SVC Assist |*/
/* |80 | SSM | Virtual SSM Assist |*/
/* |82 | LPSW | Virtual LPSW Assist |*/
/* +-----+-------+----------------------------------------+*/
/* */
/***********************************************************/
#include "hstdinc.h"
#if !defined(_HENGINE_DLL_)
#define _HENGINE_DLL_
#endif
#if !defined(_ECPSVM_C_)
#define _ECPSVM_C_
#endif
#include "hercules.h"
#include "opcode.h"
#include "inline.h"
#include "ecpsvm.h"
#ifdef FEATURE_ECPSVM
ECPSVM_CMDENT *ecpsvm_getcmdent(char *cmd);
struct _ECPSVM_CPSTATS
{
ECPSVM_STAT_DCL(SVC);
ECPSVM_STAT_DCL(SSM);
ECPSVM_STAT_DCL(LPSW);
ECPSVM_STAT_DCL(STNSM);
ECPSVM_STAT_DCL(STOSM);
ECPSVM_STAT_DCL(SIO);
ECPSVM_STAT_DCL(VTIMER);
ECPSVM_STAT_DCL(STCTL);
ECPSVM_STAT_DCL(LCTL);
ECPSVM_STAT_DCL(DIAG);
ECPSVM_STAT_DCL(IUCV);
} ecpsvm_sastats={
ECPSVM_STAT_DEF(SVC),
ECPSVM_STAT_DEF(SSM),
ECPSVM_STAT_DEF(LPSW),
ECPSVM_STAT_DEFU(STNSM),
ECPSVM_STAT_DEFU(STOSM),
ECPSVM_STAT_DEFU(SIO),
ECPSVM_STAT_DEF(VTIMER),
ECPSVM_STAT_DEFU(STCTL),
ECPSVM_STAT_DEF(LCTL),
ECPSVM_STAT_DEFU(DIAG),
ECPSVM_STAT_DEFU(IUCV),
};
struct _ECPSVM_SASTATS
{
ECPSVM_STAT_DCL(FREE);
ECPSVM_STAT_DCL(FRET);
ECPSVM_STAT_DCL(LCKPG);
ECPSVM_STAT_DCL(ULKPG);
ECPSVM_STAT_DCL(SCNRU);
ECPSVM_STAT_DCL(SCNVU);
ECPSVM_STAT_DCL(DISP0);
ECPSVM_STAT_DCL(DISP1);
ECPSVM_STAT_DCL(DISP2);
ECPSVM_STAT_DCL(DNCCW);
ECPSVM_STAT_DCL(DFCCW);
ECPSVM_STAT_DCL(FCCWS);
ECPSVM_STAT_DCL(CCWGN);
ECPSVM_STAT_DCL(UXCCW);
ECPSVM_STAT_DCL(TRBRG);
ECPSVM_STAT_DCL(TRLOK);
ECPSVM_STAT_DCL(VIST);
ECPSVM_STAT_DCL(VIPT);
ECPSVM_STAT_DCL(STEVL);
ECPSVM_STAT_DCL(FREEX);
ECPSVM_STAT_DCL(FRETX);
ECPSVM_STAT_DCL(PMASS);
ECPSVM_STAT_DCL(LCSPG);
} ecpsvm_cpstats={
ECPSVM_STAT_DEFU(FREE),
ECPSVM_STAT_DEFU(FRET),
ECPSVM_STAT_DEF(LCKPG),
ECPSVM_STAT_DEF(ULKPG),
ECPSVM_STAT_DEF(SCNRU),
ECPSVM_STAT_DEF(SCNVU),
ECPSVM_STAT_DEF(DISP0),
ECPSVM_STAT_DEF(DISP1),
ECPSVM_STAT_DEF(DISP2),
ECPSVM_STAT_DEFU(DNCCW),
ECPSVM_STAT_DEFU(DFCCW),
ECPSVM_STAT_DEFU(FCCWS),
ECPSVM_STAT_DEFU(CCWGN),
ECPSVM_STAT_DEFU(UXCCW),
ECPSVM_STAT_DEF(TRBRG),
ECPSVM_STAT_DEF(TRLOK),
ECPSVM_STAT_DEFU(VIST),
ECPSVM_STAT_DEFU(VIPT),
ECPSVM_STAT_DEF(STEVL),
ECPSVM_STAT_DEF(FREEX),
ECPSVM_STAT_DEF(FRETX),
ECPSVM_STAT_DEFU(PMASS),
ECPSVM_STAT_DEFU(LCSPG),
};
#define DEBUG_CPASSIST
#define DEBUG_SASSIST
#define DODEBUG_ASSIST(_cond,x) \
{ \
if((_cond)) \
{ \
x; \
}\
}
#if defined(DEBUG_SASSIST)
#define DEBUG_SASSISTX(_inst,x) \
{ \
DODEBUG_ASSIST(ecpsvm_sastats._inst.debug,x) \
}
#else
#define DEBUG_SASSISTX(_cond,x)
#endif
#if defined(DEBUG_CPASSIST)
#define DEBUG_CPASSISTX(_inst,x) \
{ \
DODEBUG_ASSIST(ecpsvm_cpstats._inst.debug,x) \
}
#else
#define DEBUG_CPASSISTX(_cond,x)
#endif
/* Utility macros because I am very lazy */
#define EVM_IC( x ) ARCH_DEP(vfetchb) ( ( ( x ) & ADDRESS_MAXWRAP(regs) ) , USE_REAL_ADDR , regs )
#define EVM_LH( x ) ARCH_DEP(vfetch2) ( ( ( x ) & ADDRESS_MAXWRAP(regs) ) , USE_REAL_ADDR , regs )
#define EVM_L( x ) ARCH_DEP(vfetch4) ( ( ( x ) & ADDRESS_MAXWRAP(regs) ) , USE_REAL_ADDR , regs )
#define EVM_LD( x ) ARCH_DEP(vfetch8) ( ( ( x ) & ADDRESS_MAXWRAP(regs) ) , USE_REAL_ADDR , regs )
#define EVM_STD( x , y ) ARCH_DEP(vstore8) ( ( x ) , ( ( y ) & ADDRESS_MAXWRAP(regs) ) , USE_REAL_ADDR , regs )
#define EVM_ST( x , y ) ARCH_DEP(vstore4) ( ( x ) , ( ( y ) & ADDRESS_MAXWRAP(regs) ) , USE_REAL_ADDR , regs )
#define EVM_STH( x , y ) ARCH_DEP(vstore2) ( ( x ) , ( ( y ) & ADDRESS_MAXWRAP(regs) ) , USE_REAL_ADDR , regs )
#define EVM_STC( x , y ) ARCH_DEP(vstoreb) ( ( x ) , ( ( y ) & ADDRESS_MAXWRAP(regs) ) , USE_REAL_ADDR , regs )
#define EVM_MVC( x , y , z ) ARCH_DEP(vfetchc) ( ( x ) , ( z ) , ( y ) , USE_REAL_ADDR , regs )
#define BR14 do { \
regs->psw.IA=regs->GR_L(14) & ADDRESS_MAXWRAP(regs); \
VALIDATE_AIA(regs); \
} while(0)
#define INITPSEUDOIP(_regs) \
do { \
(_regs).ip=(BYTE*)"\0\0"; \
} while(0)
#define INITPSEUDOREGS(_regs) \
do { \
memset(&(_regs),0,sizeof((_regs))); \
INITPSEUDOIP((_regs)); \
} while(0)
#define CPASSIST_HIT(_stat) ecpsvm_cpstats._stat.hit++
#define SASSIST_HIT(_stat) ecpsvm_sastats._stat.hit++
#define SASSIST_LPSW(_regs) \
do { \
regs->psw.IA=(_regs.psw.IA & ADDRESS_MAXWRAP(_regs)); \
regs->psw.cc=_regs.psw.cc; \
regs->psw.pkey=_regs.psw.pkey; \
regs->psw.progmask=_regs.psw.progmask; \
VALIDATE_AIA(regs); \
} \
while(0)
#define SASSIST_PROLOG( _instname) \
VADR amicblok; \
VADR vpswa; \
BYTE *vpswa_p; \
REGS vpregs; \
BYTE micpend; \
U32 CR6; \
ECPSVM_MICBLOK micblok; \
BYTE micevma; \
BYTE micevma2; \
BYTE micevma3; \
BYTE micevma4; \
if(SIE_STATE(regs)) \
return(1); \
if(!PROBSTATE(®s->psw)) \
{ \
return(1); \
} \
if(!sysblk.ecpsvm.available) \
{ \
DEBUG_SASSISTX(_instname,logmsg(_("HHCEV300D : SASSIST "#_instname" ECPS:VM Disabled in configuration\n"))); \
return(1); \
} \
if(!ecpsvm_sastats._instname.enabled) \
{ \
DEBUG_SASSISTX(_instname,logmsg(_("HHCEV300D : SASSIST "#_instname" ECPS:VM Disabled by command\n"))); \
return(1); \
} \
CR6=regs->CR_L(6); \
regs->ecps_vtmrpt = NULL; /* Assume vtimer off until validated */ \
if(!(CR6 & ECPSVM_CR6_VMASSIST)) \
{ \
DEBUG_SASSISTX(_instname,logmsg(_("HHCEV300D : EVMA Disabled by guest\n"))); \
return(1); \
} \
/* Increment call now (don't count early misses) */ \
ecpsvm_sastats._instname.call++; \
amicblok=CR6 & ECPSVM_CR6_MICBLOK; \
/* Ensure MICBLOK resides on a single 2K page */ \
/* Then set ref bit by calling LOG_TO_ABS */ \
if((amicblok & 0x007ff) > 0x7e0) \
{ \
DEBUG_SASSISTX(_instname,logmsg(_("HHCEV300D : SASSIST "#_instname" Micblok @ %6.6X crosses page frame\n"),amicblok)); \
return(1); \
} \
/* Load the micblok copy */ \
micblok.MICRSEG=EVM_L(amicblok); \
micblok.MICCREG=EVM_L(amicblok+4); \
micblok.MICVPSW=EVM_L(amicblok+8); \
micblok.MICWORK=EVM_L(amicblok+12); \
micblok.MICVTMR=EVM_L(amicblok+16); \
micblok.MICACF=EVM_L(amicblok+20); \
micpend=(micblok.MICVPSW >> 24); \
vpswa=micblok.MICVPSW & ADDRESS_MAXWRAP(regs); \
micevma=(micblok.MICACF >> 24); \
micevma2=((micblok.MICACF & 0x00ff0000) >> 16); \
micevma3=((micblok.MICACF & 0x0000ff00) >> 8); \
micevma4=(micblok.MICACF & 0x000000ff); \
if((CR6 & ECPSVM_CR6_VIRTTIMR)) \
{ \
regs->ecps_vtmrpt = MADDR(micblok.MICVTMR,USE_REAL_ADDR,regs,ACCTYPE_READ,0); \
} \
/* Set ref bit on page where Virtual PSW is stored */ \
vpswa_p=MADDR(vpswa,USE_REAL_ADDR,regs,ACCTYPE_READ,0); \
DEBUG_SASSISTX(_instname,logmsg(_("HHCEV300D : SASSIST "#_instname" VPSWA= %8.8X Virtual "),vpswa)); \
DEBUG_SASSISTX(_instname,logmsg(_("HHCEV300D : SASSIST "#_instname" CR6= %8.8X\n"),CR6)); \
DEBUG_SASSISTX(_instname,logmsg(_("HHCEV300D : SASSIST "#_instname" MICVTMR= %8.8X\n"),micblok.MICVTMR)); \
DEBUG_SASSISTX(_instname,logmsg(_("HHCEV300D : SASSIST "#_instname" Real "))); \
DEBUG_SASSISTX(_instname,display_psw(regs)); \
/* Load the Virtual PSW in a temporary REGS structure */ \
INITPSEUDOREGS(vpregs); \
ARCH_DEP(load_psw) (&vpregs,vpswa_p); \
DEBUG_SASSISTX(_instname,display_psw(&vpregs)); \
#define ECPSVM_PROLOG(_inst) \
int b1, b2; \
VADR effective_addr1, \
effective_addr2; \
SSE(inst, regs, b1, effective_addr1, b2, effective_addr2); \
PRIV_CHECK(regs); \
SIE_INTERCEPT(regs); \
if(!sysblk.ecpsvm.available) \
{ \
DEBUG_CPASSISTX(_inst,logmsg(_("HHCEV300D : CPASSTS "#_inst" ECPS:VM Disabled in configuration "))); \
ARCH_DEP(program_interrupt) (regs, PGM_OPERATION_EXCEPTION); \
} \
PRIV_CHECK(regs); /* No problem state please */ \
if(!ecpsvm_cpstats._inst.enabled) \
{ \
DEBUG_CPASSISTX(_inst,logmsg(_("HHCEV300D : CPASSTS "#_inst" Disabled by command"))); \
return; \
} \
if(!(regs->CR_L(6) & 0x02000000)) \
{ \
return; \
} \
ecpsvm_cpstats._inst.call++; \
DEBUG_CPASSISTX(_inst,logmsg(_("HHCEV300D : "#_inst" called\n")));
/* DISPx Utility macros */
#define STPT(_x) \
{ \
EVM_STD(cpu_timer(regs),_x); \
}
#define SPT(_x) \
{ \
set_cpu_timer(regs,EVM_LD(_x)); \
obtain_lock(&sysblk.intlock); \
if(CPU_TIMER(regs) < 0) \
{ \
ON_IC_PTIMER(regs); \
} \
else \
{ \
OFF_IC_PTIMER(regs); \
} \
release_lock(&sysblk.intlock); \
}
#define CHARGE_STOP(_x) \
{ \
STPT(_x+VMTTIME); \
}
#define CHARGE_START(_x) \
{ \
SPT(_x+VMTTIME); \
}
#define CHARGE_SWITCH(_x,_y) \
{ \
CHARGE_STOP(_x); \
CHARGE_START(_y); \
(_x)=(_y); \
}
int ecpsvm_do_fretx(REGS *regs,VADR block,U16 numdw,VADR maxsztbl,VADR fretl);
/* CPASSIST FREE (Basic) Not supported */
/* This is part of ECPS:VM Level 18 and 19 */
/* ECPS:VM Level 20 use FREEX */
DEF_INST(ecpsvm_basic_freex)
{
ECPSVM_PROLOG(FREE);
}
/* CPASSIST FRET (Basic) Not supported */
/* This is part of ECPS:VM Level 18 and 19 */
/* ECPS:VM Level 20 use FRETX */
DEF_INST(ecpsvm_basic_fretx)
{
ECPSVM_PROLOG(FRET);
}
/* Lockpage common code (LCKPG/TRLOK) */
static void ecpsvm_lockpage1(REGS *regs,RADR cortab,RADR pg)
{
BYTE corcode;
VADR corte;
U32 lockcount;
RADR cortbl;
DEBUG_CPASSISTX(LCKPG,logmsg(_("HHCEV300D : LKPG coreptr = "F_RADR" Frame = "F_RADR"\n"),cortab,pg));
cortbl=EVM_L(cortab);
corte=cortbl+((pg & 0xfff000)>>8);
DEBUG_CPASSISTX(LCKPG,logmsg(_("HHCEV300D : LKPG corete = %6.6X\n"),corte));
corcode=EVM_IC(corte+8);
if(corcode & 0x80)
{
lockcount=EVM_L(corte+4);
lockcount++;
}
else
{
lockcount=1;
corcode|=0x80;
EVM_STC(corcode,corte+8);
}
EVM_ST(lockcount,corte+4);
DEBUG_CPASSISTX(LCKPG,logmsg(_("HHCEV300D : LKPG Page locked. Count = %6.6X\n"),lockcount));
return;
}
/* E602 LCKPG Instruction */
/* LCKPG D1(R1,B1),D2(R2,B2) */
/* 1st operand : PTR_PL -> Address of coretable */
/* 2nd Operand : Page address to be locked */
DEF_INST(ecpsvm_lock_page)
{
VADR ptr_pl;
VADR pg;
ECPSVM_PROLOG(LCKPG);
ptr_pl=effective_addr1;
pg=effective_addr2;
DEBUG_CPASSISTX(LCKPG,logmsg(_("HHCEV300D : LKPG PAGE=%6.6X, PTRPL=%6.6X\n"),pg,ptr_pl));
ecpsvm_lockpage1(regs,ptr_pl,pg);
regs->psw.cc=0;
BR14;
CPASSIST_HIT(LCKPG);
return;
}
/* E603 ULKPG Instruction */
/* ULKPG D1(R1,B1),D2(R2,B2) */
/* 1st operand : PTR_PL -> +0 - Maxsize, +4 Coretable */
/* 2nd Operand : Page address to be unlocked */
DEF_INST(ecpsvm_unlock_page)
{
VADR ptr_pl;
VADR pg;
VADR corsz;
VADR cortbl;
VADR corte;
BYTE corcode;
U32 lockcount;
ECPSVM_PROLOG(ULKPG);
ptr_pl=effective_addr1;
pg=effective_addr2;
DEBUG_CPASSISTX(ULKPG,logmsg(_("HHCEV300D : ULKPG PAGE=%6.6X, PTRPL=%6.6X\n"),pg,ptr_pl));
corsz=EVM_L(ptr_pl);
cortbl=EVM_L(ptr_pl+4);
if((pg+4095)>corsz)
{
DEBUG_CPASSISTX(ULKPG,logmsg(_("HHCEV300D : ULKPG Page beyond core size of %6.6X\n"),corsz));
return;
}
corte=cortbl+((pg & 0xfff000)>>8);
corcode=EVM_IC(corte+8);
if(corcode & 0x80)
{
lockcount=EVM_L(corte+4);
lockcount--;
}
else
{
DEBUG_CPASSISTX(ULKPG,logmsg(_("HHCEV300D : ULKPG Attempting to unlock page that is not locked\n")));
return;
}
if(lockcount==0)
{
corcode &= ~(0x80|0x02);
EVM_STC(corcode,corte+8);
DEBUG_CPASSISTX(ULKPG,logmsg(_("HHCEV300D : ULKPG now unlocked\n")));
}
else
{
DEBUG_CPASSISTX(ULKPG,logmsg(_("HHCEV300D : ULKPG Page still locked. Count = %6.6X\n"),lockcount));
}
EVM_ST(lockcount,corte+4);
CPASSIST_HIT(ULKPG);
BR14;
return;
}
/* DNCCW : Not supported */
DEF_INST(ecpsvm_decode_next_ccw)
{
ECPSVM_PROLOG(DNCCW);
}
/* FCCWS : Not supported */
DEF_INST(ecpsvm_free_ccwstor)
{
ECPSVM_PROLOG(FCCWS);
}
/* SCNVU : Scan for Virtual Device blocks */
DEF_INST(ecpsvm_locate_vblock)
{
U32 vdev;
U32 vchix;
U32 vcuix;
U32 vdvix;
VADR vchtbl;
VADR vch;
VADR vcu;
VADR vdv;
ECPSVM_PROLOG(SCNVU);
vdev=regs->GR_L(1);
vchtbl=effective_addr1;
vchix=EVM_LH(vchtbl+((vdev & 0xf00)>>7)); /* Get Index */
if(vchix & 0x8000)
{
DEBUG_CPASSISTX(SCNVU,logmsg(_("HHCEV300D SCNVU Virtual Device %4.4X has no VCHAN block\n"),vdev));
return;
}
vch=EVM_L(effective_addr2)+vchix;
vcuix=EVM_LH(vch+8+((vdev & 0xf0)>>3));
if(vcuix & 0x8000)
{
DEBUG_CPASSISTX(SCNVU,logmsg(_("HHCEV300D SCNVU Virtual Device %4.4X has no VCU block\n"),vdev));
return;
}
vcu=EVM_L(effective_addr2+4)+vcuix;
vdvix=EVM_LH(vcu+8+((vdev & 0xf)<<1));
if(vdvix & 0x8000)
{
DEBUG_CPASSISTX(SCNVU,logmsg(_("HHCEV300D SCNVU Virtual Device %4.4X has no VDEV block\n"),vdev));
return;
}
vdv=EVM_L(effective_addr2+8)+vdvix;
DEBUG_CPASSISTX(SCNVU,logmsg(_("HHCEV300D SCNVU %4.4X : VCH = %8.8X, VCU = %8.8X, VDEV = %8.8X\n"),
vdev,
vch,
vcu,
vdv));
regs->GR_L(6)=vch;
regs->GR_L(7)=vcu;
regs->GR_L(8)=vdv;
regs->psw.cc=0;
CPASSIST_HIT(SCNVU);
BR14;
return;
}
/* DISP1 Core */
/* rc : 0 - Done */
/* rc : 1 - No-op */
/* rc : 2 - Invoke DISP2 */
int ecpsvm_do_disp1(REGS *regs,VADR dl,VADR el)
{
VADR vmb;
U32 F_VMFLGS; /* Aggregate for quick test */
U32 F_SCHMASK; /* Flags to test */
U32 F_SCHMON; /* Flags allowed on for quick dispatch */
VADR F_ASYSVM; /* System VMBLOK */
VADR SCHDL; /* SCHDL Exit */
BYTE B_VMOSTAT;
BYTE B_VMQSTAT;
BYTE B_VMRSTAT;
vmb=regs->GR_L(11);
DEBUG_CPASSISTX(DISP1,logmsg("DISP1 Data list = %6.6X VM=%6.6X\n",dl,vmb));
F_VMFLGS=EVM_L(vmb+VMRSTAT);
F_SCHMASK=EVM_L(dl+64);
F_SCHMON=EVM_L(dl+68);
if((F_VMFLGS & F_SCHMASK) == F_SCHMON)
{
DEBUG_CPASSISTX(DISP1,logmsg("DISP1 Quick Check complete\n"));
return(2);
}
else
{
DEBUG_CPASSISTX(DISP1,logmsg("DISP1 Quick Check failed : %8.8X != %8.8X\n",(F_VMFLGS & F_SCHMASK),F_SCHMON));
}
F_ASYSVM=EVM_L(ASYSVM);
if(vmb==F_ASYSVM)
{
DEBUG_CPASSISTX(DISP1,logmsg("DISP1 VMB is SYSTEM VMBLOCK\n"));
return(2);
}
SCHDL=EVM_L(el+4);
B_VMOSTAT=EVM_IC(vmb+VMOSTAT);
if(!(B_VMOSTAT & VMKILL))
{
DEBUG_CPASSISTX(DISP1,logmsg("DISP1 Call SCHEDULE because VMKILL not set\n"));
regs->psw.IA=SCHDL;
VALIDATE_AIA(regs);
return(0);
}
B_VMQSTAT=EVM_IC(vmb+VMQSTAT);
if(!(B_VMQSTAT & VMCFREAD))
{
if(B_VMOSTAT & VMCF)
{
DEBUG_CPASSISTX(DISP1,logmsg("DISP1 Call SCHEDULE because VMKILL & VMCF & !VMCFREAD set\n"));
regs->psw.IA=SCHDL;
VALIDATE_AIA(regs);
return(0);
}
}
/* At DSP - OFF */
B_VMQSTAT &= ~VMCFREAD;
B_VMOSTAT &= ~VMKILL;
EVM_STC(B_VMQSTAT,vmb+VMQSTAT);
EVM_STC(B_VMOSTAT,vmb+VMOSTAT);
B_VMRSTAT=EVM_IC(vmb+VMRSTAT);
if(B_VMRSTAT & VMLOGOFF)
{
DEBUG_CPASSISTX(DISP1,logmsg("DISP1 Continue because already logging off\n"));
return(2);
}
B_VMRSTAT |= VMLOGOFF;
EVM_STC(B_VMRSTAT,vmb+VMRSTAT);
regs->psw.IA=EVM_L(el+0);
VALIDATE_AIA(regs);
DEBUG_CPASSISTX(DISP1,logmsg("DISP1 : Call USOFF\n"));
return(0);
}
/* DISP2 Core */
int ecpsvm_do_disp2(REGS *regs,VADR dl,VADR el)
{
VADR vmb; /* Current VMBLOK */
VADR svmb; /* ASYSVM */
VADR runu; /* RUNUSER */
VADR lastu; /* LASTUSER */
VADR F_TRQB;
VADR F_CPEXB;
VADR F,B;
U16 HW1;
U32 FW1;
U64 DW1;
U32 CPEXBKUP[15]; /* CPEXBLOK Regs backup except GPR15 which is useless */
VADR F_ECBLOK; /* Pointer to user's EC block for extended VM */
VADR F_CPEXADD;
U32 F_QUANTUM;
REGS wregs; /* Work REGS structure of PSW manipulation for Virtual PSW */
REGS rregs; /* Work REGS structure of PSW manipulation for Real PSW */
int i;
BYTE B_VMDSTAT,B_VMRSTAT,B_VMESTAT,B_VMPSTAT,B_VMMCR6,B_MICVIP;
BYTE B_VMOSTAT,B_VMPEND;
VADR F_MICBLOK;
U32 F_VMIOINT,F_VMPXINT;
U32 F_VMVCR0;
U32 NCR0,NCR1;
BYTE *work_p;
vmb=regs->GR_L(11);
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 Data list=%6.6X VM=%6.6X\n",dl,vmb));
CHARGE_STOP(vmb);
if(EVM_IC(XTENDLOCK) == XTENDLOCKSET)
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 Exit 8 : System extending\n"));
/* System in Extend process */
regs->psw.IA=EVM_L(el+8);
VALIDATE_AIA(regs);
return(0);
}
if(EVM_IC(APSTAT2) & CPMCHLK)
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 Exit 8 : MCH Recovery\n"));
/* Machine Check recovery in progress */
regs->psw.IA=EVM_L(el+8);
VALIDATE_AIA(regs);
return(0);
}
svmb=EVM_L(ASYSVM);
/* Check IOB/TRQ for dispatch */
F_TRQB=EVM_L(dl+8);
if(F_TRQB!=dl)
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 TRQ/IOB @ %6.6X Exit being routed\n",F_TRQB));
/* We have a TRQ/IOB */
/* Update stack */
F=EVM_L(F_TRQB+8);
B=EVM_L(F_TRQB+12);
EVM_ST(F,B+8);
EVM_ST(B,F+12);
/* Get VMBLOK Responsible for this block */
vmb=EVM_L(F_TRQB+0x18);
/* Update stack count for the VMBLOK */
HW1=EVM_LH(vmb+VMSTKCNT);
HW1--;
EVM_STH(HW1,vmb+VMSTKCNT);
/* Start charging user for processor time */
CHARGE_START(vmb);
EVM_ST(vmb,STACKVM);
/* Update registers for TRQ/IOB exit */
regs->GR_L(10)=F_TRQB;
regs->GR_L(11)=vmb;
regs->GR_L(12)=EVM_L(F_TRQB+0x1C);
regs->psw.IA=regs->GR_L(12) & ADDRESS_MAXWRAP(regs);
VALIDATE_AIA(regs);
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 TRQ/IOB @ %6.6X IA = %6.6X\n",F_TRQB,regs->GR_L(12)));
return(0);
}
/* Check CPEX BLOCK for dispatch */
F_CPEXB=EVM_L(dl+0);
if(F_CPEXB!=dl)
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 CPEXBLOK Exit being routed CPEX=%6.6X\n",F_CPEXB));
/* We have a CPEXBLOCK */
/* Update stack */
F=EVM_L(F_CPEXB+0);
B=EVM_L(F_CPEXB+4);
EVM_ST(F,B+0);
EVM_ST(B,F+4);
vmb=EVM_L(F_CPEXB+0x10+(11*4));
HW1=EVM_LH(vmb+VMSTKCNT);
HW1--;
EVM_STH(HW1,vmb+VMSTKCNT);
CHARGE_START(vmb);
/* Copy CPEXBLOCK Contents, and attempt FRET */
/* If fret fails, use exit #12 */
for(i=0;i<15;i++)
{
CPEXBKUP[i]=EVM_L(F_CPEXB+0x10+(i*4));
}
F_CPEXADD=EVM_L(F_CPEXB+0x0C);
if(ecpsvm_do_fretx(regs,F_CPEXB,10,EVM_L(dl+28),EVM_L(dl+32))!=0)
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 CPEXBLOK CPEX=%6.6X Fret Failed\n",F_CPEXB));
regs->GR_L(0)=10;
regs->GR_L(1)=F_CPEXB;
for(i=2;i<12;i++)
{
regs->GR_L(i)=CPEXBKUP[i];
}
/* Save GPRS 12-1 (wraping) in DSPSAVE (datalist +40) */
/* So that LM 12,1,DSPSAVE in DMKDSP works after call to DMKFRET */
EVM_ST(dl+40,CPEXBKUP[12]);
EVM_ST(dl+44,CPEXBKUP[13]);
EVM_ST(dl+48,CPEXBKUP[14]);
EVM_ST(dl+52,CPEXBKUP[15]);
EVM_ST(dl+56,CPEXBKUP[0]);
EVM_ST(dl+60,CPEXBKUP[1]); /* Note : DMKDSP Is wrong - SCHMASK is at +64 (not +60) */
/* Upon taking this exit, GPRS 12-15 are same as entry */
regs->psw.IA=EVM_L(el+12);
VALIDATE_AIA(regs);
return(0);
}
for(i=0;i<15;i++)
{
regs->GR_L(i)=CPEXBKUP[i];
}
regs->GR_L(15)=F_CPEXADD;
regs->psw.IA=F_CPEXADD & ADDRESS_MAXWRAP(regs);
VALIDATE_AIA(regs);
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 CPEXBLOK CPEX=%6.6X IA=%6.6X\n",F_CPEXB,F_CPEXADD));
return(0); /* CPEXBLOCK Branch taken */
}
/* Check for a USER run */
/* AT DMKDSP - DONE */
if(EVM_IC(CPSTAT2) & CPSHRLK)
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 Exit 24 : CPSHRLK Set in CPSTAT2\n"));
regs->psw.IA=EVM_L(el+24); /* IDLEECPS */
VALIDATE_AIA(regs);
return(0);
}
/* Scan Scheduler IN-Q */
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : Scanning Scheduler IN-Queue\n"));
FW1=EVM_L(dl+24);
for(vmb=EVM_L(FW1);vmb!=FW1;vmb=EVM_L(vmb))
{
if(!(EVM_IC(vmb+VMDSTAT) & VMRUN))
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : VMB @ %6.6X Not eligible : VMRUN not set\n",vmb));
continue;
}
if(EVM_IC(vmb+VMRSTAT) & VMCPWAIT)
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : VMB @ %6.6X Not eligible : VMCPWAIT set\n",vmb));
continue;
}
if(EVM_IC(vmb+VMNOECPS))
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : Exit 20 : VMB @ %6.6X Has VMNOECPS Set to %2.2X\n",vmb,EVM_IC(vmb+VMNOECPS)));
regs->GR_L(1)=vmb;
regs->GR_L(11)=EVM_L(ASYSVM);
regs->psw.IA=EVM_L(el+20); /* FREELOCK */
VALIDATE_AIA(regs);
return(0);
}
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : VMB @ %6.6X Will now be dispatched\n",vmb));
runu=EVM_L(RUNUSER);
F_QUANTUM=EVM_L(QUANTUM);
if(vmb!=runu)
{
/* User switching */
/* DMKDSP - FNDUSRD */
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : User switch from %6.6X to %6.6X\n",runu,vmb));
runu=EVM_L(RUNUSER);
EVM_STC(EVM_IC(runu+VMDSTAT) & ~VMDSP,runu+VMDSTAT);
lastu=EVM_L(LASTUSER);
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : RUNU=%6.6X, LASTU=%6.6X\n",runu,lastu));
if(lastu!=svmb && lastu!=vmb)
{
if(EVM_IC(lastu+VMOSTAT) & VMSHR) /* Running shared sys */
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : Exit 16 : LASTU=%6.6X has shared sys & LCSHPG not impl\n",lastu));
CHARGE_START(lastu);
/* LCSHRPG not implemented yet */
regs->GR_L(10)=vmb;
regs->GR_L(11)=lastu;
regs->psw.IA=EVM_L(el+16);
VALIDATE_AIA(regs);
return(0);
/* A CHARGE_STOP(runu) is due when LCSHRPG is implemented */
}
}
}
if(vmb!=runu || (vmb==runu && (F_QUANTUM & 0x80000000)))
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : Restarting Time Slice\n"));
F_QUANTUM=EVM_L(dl+16);
if(EVM_IC(vmb+VMQLEVEL) & VMCOMP)
{
F_QUANTUM <<= 2;
}
}
EVM_ST(F_QUANTUM,INTTIMER);
CHARGE_START(vmb);
EVM_ST(vmb,LASTUSER);
EVM_ST(vmb,RUNUSER);
/*** Prepare to run a user ***/
/* Cache some important VMBLOK flag bytes */
B_VMDSTAT=EVM_IC(vmb+VMDSTAT);
B_VMRSTAT=EVM_IC(vmb+VMRSTAT);
B_VMPSTAT=EVM_IC(vmb+VMPSTAT);
B_VMESTAT=EVM_IC(vmb+VMESTAT);
B_VMOSTAT=EVM_IC(vmb+VMOSTAT);
B_VMPEND =EVM_IC(vmb+VMPEND);
B_VMMCR6=EVM_IC(vmb+VMMCR6);
F_MICBLOK=EVM_L(vmb+VMMCR6) & ADDRESS_MAXWRAP(regs);
/* LOAD FPRS */
for(i=0;i<8;i+=2)
{
FW1=EVM_L(vmb+VMFPRS+(i*16));
regs->fpr[i*4]=FW1;
FW1=EVM_L(vmb+VMFPRS+(i*16)+4);
regs->fpr[i*4+1]=FW1;
FW1=EVM_L(vmb+VMFPRS+(i*16)+8);
regs->fpr[i*4+2]=FW1;
FW1=EVM_L(vmb+VMFPRS+(i*16)+12);
regs->fpr[i*4+3]=FW1;
}
INITPSEUDOREGS(wregs);
work_p=MADDR(vmb+VMPSW,0,regs,USE_REAL_ADDR,0);
ARCH_DEP(load_psw) (&wregs,work_p); /* Load user's Virtual PSW in work structure */
/* Build REAL PSW */
INITPSEUDOREGS(rregs);
/* Copy IAR */
rregs.psw.IA=wregs.psw.IA & ADDRESS_MAXWRAP(regs);
VALIDATE_AIA(&rregs);
/* Copy CC, PSW KEYs and PGM Mask */
rregs.psw.cc=wregs.psw.cc;
rregs.psw.pkey=wregs.psw.pkey;
/* Indicate Translation + I/O + Ext + Ecmode + Problem + MC */
rregs.psw.sysmask=0x07; /* I/O + EXT + Trans */
rregs.psw.states = BIT(PSW_EC_BIT) /* ECMODE */
| BIT(PSW_PROB_BIT) /* Problem state */
| BIT(PSW_MACH_BIT); /* MC Enabled */
rregs.psw.intcode=0; /* Clear intcode */
rregs.psw.progmask=wregs.psw.progmask;
NCR0=EVM_L(CPCREG0); /* Assume for now */
NCR1=EVM_L(vmb+VMSEG); /* Ditto */
/* Disable ECPS:VM in VM-REAL CR6 For now */
B_VMMCR6&=~(VMMSHADT|VMMPROB|VMMNOSK|VMMFE);
/* We load VMECEXT Even if it's not a ECMODE VM */
/* in which case F_ECBLOK is also Virtual CR0 */
F_ECBLOK=EVM_L(vmb+VMECEXT);
/* ECMODE VM ? */
if(B_VMPSTAT & VMV370R)
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : VMB @ %6.6X has ECMODE ON\n",vmb));
/* Is this an ECMODE PSW Machine ? */
if(B_VMESTAT & VMEXTCM)
{
if((B_VMESTAT & (VMINVSEG|VMNEWCR0)) == (VMINVSEG|VMNEWCR0))
{
/* CP Say this is NOT good */
/* Take exit 28 */
logmsg(_("HHCEV004W : Abend condition detected in DISP2 instr\n"));
regs->psw.IA=EVM_L(el+28);
VALIDATE_AIA(regs);
return(0);
}
/* Check 3rd level translation */
if(wregs.psw.sysmask & 0x04)
{
NCR0=EVM_L(F_ECBLOK+EXTSHCR0);
NCR1=EVM_L(F_ECBLOK+EXTSHCR1);
B_VMMCR6|=VMMSHADT; /* re-enable Shadow Table management in CR6 */
}
}
}
/* Invalidate Shadow Tables if necessary */
if(B_VMESTAT & (VMINVPAG | VMSHADT))
{
DEBUG_CPASSISTX(DISP2,logmsg("DISP2 : VMB @ %6.6X Refusing to simulate DMKVATAB\n",vmb));
/* Really looks like DMKVATAB is a huge thing to simulate */
/* My belief is that the assist can't handle this one */
/* Return to caller as a NO-OP on this one */
return(1);
/* ecpsvm_inv_shadtab_pages(regs,vmb); */
}
B_VMESTAT&=~VMINVPAG;
B_VMDSTAT|=VMDSP;
/* Test for CPMICON in DMKDSP useless here */
/* if CPMICON was off, we would have never */
/* been called anyway */
if(F_MICBLOK!=0) /* That is SET ASSIST ON */
{
B_MICVIP=0;
/* Check tracing (incompatible with assist) */
if(!(EVM_IC(vmb+VMTRCTL) & (VMTRSVC|VMTRPRV|VMTRBRIN)))
{
B_VMMCR6|=VMMFE;
if(B_VMOSTAT & VMSHR)
{
/* Cannot allow ISK/SSK in shared sys VM */
B_VMMCR6|=VMMNOSK;
}
if(PROBSTATE(&wregs.psw))
{
B_VMMCR6|=VMMPROB;
}
/* Set MICPEND if necessary */
/* (assist stuff to ensure LPSW/SSM/SVC sim */
/* does not re-enable VPSW when an interrupt */
/* is pending) */
while(1)
{
B_MICVIP=0;
F_VMIOINT=EVM_LH(vmb+VMIOINT);
if(EVM_LH(vmb+VMIOINT)!=0)
{
F_VMIOINT<<=16;
if(B_VMESTAT & VMEXTCM)
{
if(F_VMIOINT&=EVM_L(F_ECBLOK))
{
B_MICVIP|=0x80;
break;
}
}
else
{
B_MICVIP|=0x80;
break;
}
}
if(B_VMESTAT & VMEXTCM)
{
if(B_VMPEND & VMPGPND)
{
B_MICVIP|=0x80;
}
}
if(B_VMPSTAT & VMV370R)
{
F_VMVCR0=EVM_L(F_ECBLOK+0);
}
else
{
F_VMVCR0=F_ECBLOK;
}
for(F_VMPXINT=EVM_L(vmb+VMPXINT);F_VMPXINT;F_VMPXINT=EVM_L(F_VMPXINT)) /* XINTNEXT at +0 */
{
if(F_VMVCR0 & EVM_LH(F_VMPXINT+10))
{
B_MICVIP|=0x80;
break;
}
}
break; /* Terminate dummy while loop */
} /* While dummy loop for MICPEND */
} /* if(Not tracing) */
EVM_STC(B_MICVIP,F_MICBLOK+8); /* Save new MICVIP */
} /* if(F_MICBLOCK!=0) */
/* If an Extended VM, Load CRs 3-13 */