forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathashxdi3.S
294 lines (271 loc) · 4.93 KB
/
ashxdi3.S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/m32r/lib/ashxdi3.S
*
* Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata
*
*/
;
; input (r0,r1) src
; input r2 shift val
; r3 scratch
; output (r0,r1)
;
#ifdef CONFIG_ISA_DUAL_ISSUE
#ifndef __LITTLE_ENDIAN__
.text
.align 4
.globl __ashrdi3
__ashrdi3:
cmpz r2 || ldi r3, #32
jc r14 || cmpu r2, r3
bc 1f
; case 32 =< shift
mv r1, r0 || srai r0, #31
addi r2, #-32
sra r1, r2
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r0 || srl r1, r2
sra r0, r2 || neg r2, r2
sll r3, r2
or r1, r3 || jmp r14
.align 4
.globl __ashldi3
.globl __lshldi3
__ashldi3:
__lshldi3:
cmpz r2 || ldi r3, #32
jc r14 || cmpu r2, r3
bc 1f
; case 32 =< shift
mv r0, r1 || addi r2, #-32
sll r0, r2 || ldi r1, #0
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r1 || sll r0, r2
sll r1, r2 || neg r2, r2
srl r3, r2
or r0, r3 || jmp r14
.align 4
.globl __lshrdi3
__lshrdi3:
cmpz r2 || ldi r3, #32
jc r14 || cmpu r2, r3
bc 1f
; case 32 =< shift
mv r1, r0 || addi r2, #-32
ldi r0, #0 || srl r1, r2
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r0 || srl r1, r2
srl r0, r2 || neg r2, r2
sll r3, r2
or r1, r3 || jmp r14
#else /* LITTLE_ENDIAN */
.text
.align 4
.globl __ashrdi3
__ashrdi3:
cmpz r2 || ldi r3, #32
jc r14 || cmpu r2, r3
bc 1f
; case 32 =< shift
mv r0, r1 || srai r1, #31
addi r2, #-32
sra r0, r2
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r1 || srl r0, r2
sra r1, r2 || neg r2, r2
sll r3, r2
or r0, r3 || jmp r14
.align 4
.globl __ashldi3
.globl __lshldi3
__ashldi3:
__lshldi3:
cmpz r2 || ldi r3, #32
jc r14 || cmpu r2, r3
bc 1f
; case 32 =< shift
mv r1, r0 || addi r2, #-32
sll r1, r2 || ldi r0, #0
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r0 || sll r1, r2
sll r0, r2 || neg r2, r2
srl r3, r2
or r1, r3 || jmp r14
.align 4
.globl __lshrdi3
__lshrdi3:
cmpz r2 || ldi r3, #32
jc r14 || cmpu r2, r3
bc 1f
; case 32 =< shift
mv r0, r1 || addi r2, #-32
ldi r1, #0 || srl r0, r2
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r1 || srl r0, r2
srl r1, r2 || neg r2, r2
sll r3, r2
or r0, r3 || jmp r14
#endif
#else /* not CONFIG_ISA_DUAL_ISSUE */
#ifndef __LITTLE_ENDIAN__
.text
.align 4
.globl __ashrdi3
__ashrdi3:
beqz r2, 2f
cmpui r2, #32
bc 1f
; case 32 =< shift
mv r1, r0
srai r0, #31
addi r2, #-32
sra r1, r2
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r0
srl r1, r2
sra r0, r2
neg r2, r2
sll r3, r2
or r1, r3
.fillinsn
2:
jmp r14
.align 4
.globl __ashldi3
.globl __lshldi3
__ashldi3:
__lshldi3:
beqz r2, 2f
cmpui r2, #32
bc 1f
; case 32 =< shift
mv r0, r1
addi r2, #-32
sll r0, r2
ldi r1, #0
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r1
sll r0, r2
sll r1, r2
neg r2, r2
srl r3, r2
or r0, r3
.fillinsn
2:
jmp r14
.align 4
.globl __lshrdi3
__lshrdi3:
beqz r2, 2f
cmpui r2, #32
bc 1f
; case 32 =< shift
mv r1, r0
ldi r0, #0
addi r2, #-32
srl r1, r2
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r0
srl r1, r2
srl r0, r2
neg r2, r2
sll r3, r2
or r1, r3
.fillinsn
2:
jmp r14
#else
.text
.align 4
.globl __ashrdi3
__ashrdi3:
beqz r2, 2f
cmpui r2, #32
bc 1f
; case 32 =< shift
mv r0, r1
srai r1, #31
addi r2, #-32
sra r0, r2
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r1
srl r0, r2
sra r1, r2
neg r2, r2
sll r3, r2
or r0, r3
.fillinsn
2:
jmp r14
.align 4
.globl __ashldi3
.globl __lshldi3
__ashldi3:
__lshldi3:
beqz r2, 2f
cmpui r2, #32
bc 1f
; case 32 =< shift
mv r1, r0
addi r2, #-32
sll r1, r2
ldi r0, #0
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r0
sll r1, r2
sll r0, r2
neg r2, r2
srl r3, r2
or r1, r3
.fillinsn
2:
jmp r14
.align 4
.globl __lshrdi3
__lshrdi3:
beqz r2, 2f
cmpui r2, #32
bc 1f
; case 32 =< shift
mv r0, r1
ldi r1, #0
addi r2, #-32
srl r0, r2
jmp r14
.fillinsn
1: ; case shift <32
mv r3, r1
srl r0, r2
srl r1, r2
neg r2, r2
sll r3, r2
or r0, r3
.fillinsn
2:
jmp r14
#endif
#endif /* not CONFIG_ISA_DUAL_ISSUE */
.end