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pinctrl-gemini.c
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/*
* Driver for the Gemini pin controller
*
* Copyright (C) 2017 Linus Walleij <[email protected]>
*
* This is a group-only pin controller.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include "pinctrl-utils.h"
#define DRIVER_NAME "pinctrl-gemini"
/**
* struct gemini_pin_conf - information about configuring a pin
* @pin: the pin number
* @reg: config register
* @mask: the bits affecting the configuration of the pin
*/
struct gemini_pin_conf {
unsigned int pin;
u32 reg;
u32 mask;
};
/**
* struct gemini_pmx - state holder for the gemini pin controller
* @dev: a pointer back to containing device
* @virtbase: the offset to the controller in virtual memory
* @map: regmap to access registers
* @is_3512: whether the SoC/package is the 3512 variant
* @is_3516: whether the SoC/package is the 3516 variant
* @flash_pin: whether the flash pin (extended pins for parallel
* flash) is set
* @confs: pin config information
* @nconfs: number of pin config information items
*/
struct gemini_pmx {
struct device *dev;
struct pinctrl_dev *pctl;
struct regmap *map;
bool is_3512;
bool is_3516;
bool flash_pin;
const struct gemini_pin_conf *confs;
unsigned int nconfs;
};
/**
* struct gemini_pin_group - describes a Gemini pin group
* @name: the name of this specific pin group
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @num_pins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @mask: bits to clear to enable this when doing pin muxing
* @value: bits to set to enable this when doing pin muxing
*/
struct gemini_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int num_pins;
u32 mask;
u32 value;
};
/* Some straight-forward control registers */
#define GLOBAL_WORD_ID 0x00
#define GLOBAL_STATUS 0x04
#define GLOBAL_STATUS_FLPIN BIT(20)
#define GLOBAL_GMAC_CTRL_SKEW 0x1c
#define GLOBAL_GMAC0_DATA_SKEW 0x20
#define GLOBAL_GMAC1_DATA_SKEW 0x24
/*
* Global Miscellaneous Control Register
* This register controls all Gemini pad/pin multiplexing
*
* It is a tricky register though:
* - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
* be brought back online, so it means permanent disablement of the
* corresponding pads.
* - For the bits named *_DISABLE, once you enable something, it cannot be
* DISABLED again. So you select a flash configuration once, and then
* you are stuck with it.
*/
#define GLOBAL_MISC_CTRL 0x30
#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
/* Not really used */
#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
/* Activated with GMAC1 */
#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
/* This will be the default */
#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
#define TVC_CLK_PAD_ENABLE BIT(20)
#define PCI_CLK_PAD_ENABLE BIT(17)
#define LPC_CLK_PAD_ENABLE BIT(16)
#define TVC_PADS_ENABLE BIT(9)
#define SSP_PADS_ENABLE BIT(8)
#define LCD_PADS_ENABLE BIT(7)
#define LPC_PADS_ENABLE BIT(6)
#define PCI_PADS_ENABLE BIT(5)
#define IDE_PADS_ENABLE BIT(4)
#define DRAM_PADS_POWERDOWN BIT(3)
#define NAND_PADS_DISABLE BIT(2)
#define PFLASH_PADS_DISABLE BIT(1)
#define SFLASH_PADS_DISABLE BIT(0)
#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
#define PADS_MAXBIT 27
/* Ordered by bit index */
static const char * const gemini_padgroups[] = {
"serial flash",
"parallel flash",
"NAND flash",
"DRAM",
"IDE",
"PCI",
"LPC",
"LCD",
"SSP",
"TVC",
NULL, NULL, NULL, NULL, NULL, NULL,
"LPC CLK",
"PCI CLK",
NULL, NULL,
"TVC CLK",
NULL, NULL, NULL, NULL, NULL,
"GMAC1",
};
static const struct pinctrl_pin_desc gemini_3512_pins[] = {
/* Row A */
PINCTRL_PIN(0, "A1 VREF CTRL"),
PINCTRL_PIN(1, "A2 VCC2IO CTRL"),
PINCTRL_PIN(2, "A3 DRAM CK"),
PINCTRL_PIN(3, "A4 DRAM CK N"),
PINCTRL_PIN(4, "A5 DRAM A5"),
PINCTRL_PIN(5, "A6 DRAM CKE"),
PINCTRL_PIN(6, "A7 DRAM DQ11"),
PINCTRL_PIN(7, "A8 DRAM DQ0"),
PINCTRL_PIN(8, "A9 DRAM DQ5"),
PINCTRL_PIN(9, "A10 DRAM DQ6"),
PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
PINCTRL_PIN(11, "A12 DRAM BA1"),
PINCTRL_PIN(12, "A13 DRAM A2"),
PINCTRL_PIN(13, "A14 PCI GNT1 N"),
PINCTRL_PIN(14, "A15 PCI REQ9 N"),
PINCTRL_PIN(15, "A16 PCI REQ2 N"),
PINCTRL_PIN(16, "A17 PCI REQ3 N"),
PINCTRL_PIN(17, "A18 PCI AD31"),
/* Row B */
PINCTRL_PIN(18, "B1 VCCK CTRL"),
PINCTRL_PIN(19, "B2 PWR EN"),
PINCTRL_PIN(20, "B3 RTC CLKI"),
PINCTRL_PIN(21, "B4 DRAM A4"),
PINCTRL_PIN(22, "B5 DRAM A6"),
PINCTRL_PIN(23, "B6 DRAM A12"),
PINCTRL_PIN(24, "B7 DRAM DQS1"),
PINCTRL_PIN(25, "B8 DRAM DQ15"),
PINCTRL_PIN(26, "B9 DRAM DQ4"),
PINCTRL_PIN(27, "B10 DRAM DQS0"),
PINCTRL_PIN(28, "B11 DRAM WE N"),
PINCTRL_PIN(29, "B12 DRAM A10"),
PINCTRL_PIN(30, "B13 DRAM A3"),
PINCTRL_PIN(31, "B14 PCI GNT0 N"),
PINCTRL_PIN(32, "B15 PCI GNT3 N"),
PINCTRL_PIN(33, "B16 PCI REQ1 N"),
PINCTRL_PIN(34, "B17 PCI AD30"),
PINCTRL_PIN(35, "B18 PCI AD29"),
/* Row C */
PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */
PINCTRL_PIN(37, "C2 XTALI"),
PINCTRL_PIN(38, "C3 PWR BTN"),
PINCTRL_PIN(39, "C4 RTC CLKO"),
PINCTRL_PIN(40, "C5 DRAM A7"),
PINCTRL_PIN(41, "C6 DRAM A11"),
PINCTRL_PIN(42, "C7 DRAM DQ10"),
PINCTRL_PIN(43, "C8 DRAM DQ14"),
PINCTRL_PIN(44, "C9 DRAM DQ3"),
PINCTRL_PIN(45, "C10 DRAM DQ7"),
PINCTRL_PIN(46, "C11 DRAM CAS N"),
PINCTRL_PIN(47, "C12 DRAM A0"),
PINCTRL_PIN(48, "C13 PCI INT0 N"),
PINCTRL_PIN(49, "C14 EXT RESET N"),
PINCTRL_PIN(50, "C15 PCI GNT2 N"),
PINCTRL_PIN(51, "C16 PCI AD28"),
PINCTRL_PIN(52, "C17 PCI AD27"),
PINCTRL_PIN(53, "C18 PCI AD26"),
/* Row D */
PINCTRL_PIN(54, "D1 AVCCKHA"),
PINCTRL_PIN(55, "D2 AGNDIOHA"),
PINCTRL_PIN(56, "D3 XTALO"),
PINCTRL_PIN(57, "D4 AVCC3IOHA"),
PINCTRL_PIN(58, "D5 DRAM A8"),
PINCTRL_PIN(59, "D6 DRAM A9"),
PINCTRL_PIN(60, "D7 DRAM DQ9"),
PINCTRL_PIN(61, "D8 DRAM DQ13"),
PINCTRL_PIN(62, "D9 DRAM DQ2"),
PINCTRL_PIN(63, "D10 DRAM A13"),
PINCTRL_PIN(64, "D11 DRAM RAS N"),
PINCTRL_PIN(65, "D12 DRAM A1"),
PINCTRL_PIN(66, "D13 PCI INTC N"),
PINCTRL_PIN(67, "D14 PCI CLK"),
PINCTRL_PIN(68, "D15 PCI AD25"),
PINCTRL_PIN(69, "D16 PCI AD24"),
PINCTRL_PIN(70, "D17 PCI CBE3 N"),
PINCTRL_PIN(71, "D18 PCI AD23"),
/* Row E */
PINCTRL_PIN(72, "E1 AVCC3IOHA"),
PINCTRL_PIN(73, "E2 EBG"),
PINCTRL_PIN(74, "E3 AVCC3IOHB"),
PINCTRL_PIN(75, "E4 REXT"),
PINCTRL_PIN(76, "E5 GND"),
PINCTRL_PIN(77, "E6 DRAM DQM1"),
PINCTRL_PIN(78, "E7 DRAM DQ8"),
PINCTRL_PIN(79, "E8 DRAM DQ12"),
PINCTRL_PIN(80, "E9 DRAM DQ1"),
PINCTRL_PIN(81, "E10 DRAM DQM0"),
PINCTRL_PIN(82, "E11 DRAM BA0"),
PINCTRL_PIN(83, "E12 PCI INTA N"),
PINCTRL_PIN(84, "E13 PCI INTB N"),
PINCTRL_PIN(85, "E14 GND"),
PINCTRL_PIN(86, "E15 PCI AD22"),
PINCTRL_PIN(87, "E16 PCI AD21"),
PINCTRL_PIN(88, "E17 PCI AD20"),
PINCTRL_PIN(89, "E18 PCI AD19"),
/* Row F */
PINCTRL_PIN(90, "F1 SATA0 RXDP"),
PINCTRL_PIN(91, "F2 SATA0 RXDN"),
PINCTRL_PIN(92, "F3 AGNDK 0"),
PINCTRL_PIN(93, "F4 AVCC3 S"),
PINCTRL_PIN(94, "F5 AVCCK P"),
PINCTRL_PIN(95, "F6 GND"),
PINCTRL_PIN(96, "F7 VCC2IOHA 2"),
PINCTRL_PIN(97, "F8 VCC2IOHA 2"),
PINCTRL_PIN(98, "F9 V1"),
PINCTRL_PIN(99, "F10 V1"),
PINCTRL_PIN(100, "F11 VCC2IOHA 2"),
PINCTRL_PIN(101, "F12 VCC2IOHA 2"),
PINCTRL_PIN(102, "F13 GND"),
PINCTRL_PIN(103, "F14 PCI AD18"),
PINCTRL_PIN(104, "F15 PCI AD17"),
PINCTRL_PIN(105, "F16 PCI AD16"),
PINCTRL_PIN(106, "F17 PCI CBE2 N"),
PINCTRL_PIN(107, "F18 PCI FRAME N"),
/* Row G */
PINCTRL_PIN(108, "G1 SATA0 TXDP"),
PINCTRL_PIN(109, "G2 SATA0 TXDN"),
PINCTRL_PIN(110, "G3 AGNDK 1"),
PINCTRL_PIN(111, "G4 AVCCK 0"),
PINCTRL_PIN(112, "G5 TEST CLKOUT"),
PINCTRL_PIN(113, "G6 AGND"),
PINCTRL_PIN(114, "G7 GND"),
PINCTRL_PIN(115, "G8 VCC2IOHA 2"),
PINCTRL_PIN(116, "G9 V1"),
PINCTRL_PIN(117, "G10 V1"),
PINCTRL_PIN(118, "G11 VCC2IOHA 2"),
PINCTRL_PIN(119, "G12 GND"),
PINCTRL_PIN(120, "G13 VCC3IOHA"),
PINCTRL_PIN(121, "G14 PCI IRDY N"),
PINCTRL_PIN(122, "G15 PCI TRDY N"),
PINCTRL_PIN(123, "G16 PCI DEVSEL N"),
PINCTRL_PIN(124, "G17 PCI STOP N"),
PINCTRL_PIN(125, "G18 PCI PAR"),
/* Row H */
PINCTRL_PIN(126, "H1 SATA1 TXDP"),
PINCTRL_PIN(127, "H2 SATA1 TXDN"),
PINCTRL_PIN(128, "H3 AGNDK 2"),
PINCTRL_PIN(129, "H4 AVCCK 1"),
PINCTRL_PIN(130, "H5 AVCCK S"),
PINCTRL_PIN(131, "H6 AVCCKHB"),
PINCTRL_PIN(132, "H7 AGND"),
PINCTRL_PIN(133, "H8 GND"),
PINCTRL_PIN(134, "H9 GND"),
PINCTRL_PIN(135, "H10 GND"),
PINCTRL_PIN(136, "H11 GND"),
PINCTRL_PIN(137, "H12 VCC3IOHA"),
PINCTRL_PIN(138, "H13 VCC3IOHA"),
PINCTRL_PIN(139, "H14 PCI CBE1 N"),
PINCTRL_PIN(140, "H15 PCI AD15"),
PINCTRL_PIN(141, "H16 PCI AD14"),
PINCTRL_PIN(142, "H17 PCI AD13"),
PINCTRL_PIN(143, "H18 PCI AD12"),
/* Row J (for some reason I is skipped) */
PINCTRL_PIN(144, "J1 SATA1 RXDP"),
PINCTRL_PIN(145, "J2 SATA1 RXDN"),
PINCTRL_PIN(146, "J3 AGNDK 3"),
PINCTRL_PIN(147, "J4 AVCCK 2"),
PINCTRL_PIN(148, "J5 IDE DA1"),
PINCTRL_PIN(149, "J6 V1"),
PINCTRL_PIN(150, "J7 V1"),
PINCTRL_PIN(151, "J8 GND"),
PINCTRL_PIN(152, "J9 GND"),
PINCTRL_PIN(153, "J10 GND"),
PINCTRL_PIN(154, "J11 GND"),
PINCTRL_PIN(155, "J12 V1"),
PINCTRL_PIN(156, "J13 V1"),
PINCTRL_PIN(157, "J14 PCI AD11"),
PINCTRL_PIN(158, "J15 PCI AD10"),
PINCTRL_PIN(159, "J16 PCI AD9"),
PINCTRL_PIN(160, "J17 PCI AD8"),
PINCTRL_PIN(161, "J18 PCI CBE0 N"),
/* Row K */
PINCTRL_PIN(162, "K1 IDE CS1 N"),
PINCTRL_PIN(163, "K2 IDE CS0 N"),
PINCTRL_PIN(164, "K3 AVCCK 3"),
PINCTRL_PIN(165, "K4 IDE DA2"),
PINCTRL_PIN(166, "K5 IDE DA0"),
PINCTRL_PIN(167, "K6 V1"),
PINCTRL_PIN(168, "K7 V1"),
PINCTRL_PIN(169, "K8 GND"),
PINCTRL_PIN(170, "K9 GND"),
PINCTRL_PIN(171, "K10 GND"),
PINCTRL_PIN(172, "K11 GND"),
PINCTRL_PIN(173, "K12 V1"),
PINCTRL_PIN(174, "K13 V1"),
PINCTRL_PIN(175, "K14 PCI AD3"),
PINCTRL_PIN(176, "K15 PCI AD4"),
PINCTRL_PIN(177, "K16 PCI AD5"),
PINCTRL_PIN(178, "K17 PCI AD6"),
PINCTRL_PIN(179, "K18 PCI AD7"),
/* Row L */
PINCTRL_PIN(180, "L1 IDE INTRQ"),
PINCTRL_PIN(181, "L2 IDE DMACK N"),
PINCTRL_PIN(182, "L3 IDE IORDY"),
PINCTRL_PIN(183, "L4 IDE DIOR N"),
PINCTRL_PIN(184, "L5 IDE DIOW N"),
PINCTRL_PIN(185, "L6 VCC3IOHA"),
PINCTRL_PIN(186, "L7 VCC3IOHA"),
PINCTRL_PIN(187, "L8 GND"),
PINCTRL_PIN(188, "L9 GND"),
PINCTRL_PIN(189, "L10 GND"),
PINCTRL_PIN(190, "L11 GND"),
PINCTRL_PIN(191, "L12 VCC3IOHA"),
PINCTRL_PIN(192, "L13 VCC3IOHA"),
PINCTRL_PIN(193, "L14 GPIO0 30"),
PINCTRL_PIN(194, "L15 GPIO0 31"),
PINCTRL_PIN(195, "L16 PCI AD0"),
PINCTRL_PIN(196, "L17 PCI AD1"),
PINCTRL_PIN(197, "L18 PCI AD2"),
/* Row M */
PINCTRL_PIN(198, "M1 IDE DMARQ"),
PINCTRL_PIN(199, "M2 IDE DD15"),
PINCTRL_PIN(200, "M3 IDE DD0"),
PINCTRL_PIN(201, "M4 IDE DD14"),
PINCTRL_PIN(202, "M5 IDE DD1"),
PINCTRL_PIN(203, "M6 VCC3IOHA"),
PINCTRL_PIN(204, "M7 GND"),
PINCTRL_PIN(205, "M8 VCC2IOHA 1"),
PINCTRL_PIN(206, "M9 V1"),
PINCTRL_PIN(207, "M10 V1"),
PINCTRL_PIN(208, "M11 VCC3IOHA"),
PINCTRL_PIN(209, "M12 GND"),
PINCTRL_PIN(210, "M13 VCC3IOHA"),
PINCTRL_PIN(211, "M14 GPIO0 25"),
PINCTRL_PIN(212, "M15 GPIO0 26"),
PINCTRL_PIN(213, "M16 GPIO0 27"),
PINCTRL_PIN(214, "M17 GPIO0 28"),
PINCTRL_PIN(215, "M18 GPIO0 29"),
/* Row N */
PINCTRL_PIN(216, "N1 IDE DD13"),
PINCTRL_PIN(217, "N2 IDE DD2"),
PINCTRL_PIN(218, "N3 IDE DD12"),
PINCTRL_PIN(219, "N4 IDE DD3"),
PINCTRL_PIN(220, "N5 IDE DD11"),
PINCTRL_PIN(221, "N6 GND"),
PINCTRL_PIN(222, "N7 VCC2IOHA 1"),
PINCTRL_PIN(223, "N8 VCC2IOHA 1"),
PINCTRL_PIN(224, "N9 V1"),
PINCTRL_PIN(225, "N10 V1"),
PINCTRL_PIN(226, "N11 VCC3IOHA"),
PINCTRL_PIN(227, "N12 VCC3IOHA"),
PINCTRL_PIN(228, "N13 GND"),
PINCTRL_PIN(229, "N14 GPIO0 20"),
PINCTRL_PIN(230, "N15 GPIO0 21"),
PINCTRL_PIN(231, "N16 GPIO0 22"),
PINCTRL_PIN(232, "N17 GPIO0 23"),
PINCTRL_PIN(233, "N18 GPIO0 24"),
/* Row P (for some reason O is skipped) */
PINCTRL_PIN(234, "P1 IDE DD4"),
PINCTRL_PIN(235, "P2 IDE DD10"),
PINCTRL_PIN(236, "P3 IDE DD5"),
PINCTRL_PIN(237, "P4 IDE DD9"),
PINCTRL_PIN(238, "P5 GND"),
PINCTRL_PIN(239, "P6 USB XSCO"),
PINCTRL_PIN(240, "P7 GMAC0 TXD3"),
PINCTRL_PIN(241, "P8 GMAC0 TXEN"),
PINCTRL_PIN(242, "P9 GMAC0 RXD2"),
PINCTRL_PIN(243, "P10 GMAC1 TXC"),
PINCTRL_PIN(244, "P11 GMAC1 RXD1"),
PINCTRL_PIN(245, "P12 MODE SEL 1"),
PINCTRL_PIN(246, "P13 GPIO1 28"),
PINCTRL_PIN(247, "P14 GND"),
PINCTRL_PIN(248, "P15 GPIO0 5"),
PINCTRL_PIN(249, "P16 GPIO0 17"),
PINCTRL_PIN(250, "P17 GPIO0 18"),
PINCTRL_PIN(251, "P18 GPIO0 19"),
/* Row R (for some reason Q us skipped) */
PINCTRL_PIN(252, "R1 IDE DD6"),
PINCTRL_PIN(253, "R2 IDE DD8"),
PINCTRL_PIN(254, "R3 IDE DD7"),
PINCTRL_PIN(255, "R4 IDE RESET N"),
PINCTRL_PIN(256, "R5 ICE0 DBGACK"),
PINCTRL_PIN(257, "R6 USB XSCI"),
PINCTRL_PIN(258, "R7 GMAC0 TXD2"),
PINCTRL_PIN(259, "R8 GMAC0 RXDV"),
PINCTRL_PIN(260, "R9 GMAC0 RXD3"),
PINCTRL_PIN(261, "R10 GMAC1 TXD0"),
PINCTRL_PIN(262, "R11 GMAC1 RXD0"),
PINCTRL_PIN(263, "R12 MODE SEL 0"),
PINCTRL_PIN(264, "R13 MODE SEL 3"),
PINCTRL_PIN(265, "R14 GPIO0 0"),
PINCTRL_PIN(266, "R15 GPIO0 4"),
PINCTRL_PIN(267, "R16 GPIO0 9"),
PINCTRL_PIN(268, "R17 GPIO0 15"),
PINCTRL_PIN(269, "R18 GPIO0 16"),
/* Row T (for some reason S is skipped) */
PINCTRL_PIN(270, "T1 ICE0 DBGRQ"),
PINCTRL_PIN(271, "T2 ICE0 IDO"),
PINCTRL_PIN(272, "T3 ICE0 ICK"),
PINCTRL_PIN(273, "T4 ICE0 IMS"),
PINCTRL_PIN(274, "T5 ICE0 IDI"),
PINCTRL_PIN(275, "T6 USB RREF"),
PINCTRL_PIN(276, "T7 GMAC0 TXD1"),
PINCTRL_PIN(277, "T8 GMAC0 RXC"),
PINCTRL_PIN(278, "T9 GMAC0 CRS"),
PINCTRL_PIN(279, "T10 GMAC1 TXD1"),
PINCTRL_PIN(280, "T11 GMAC1 RXC"),
PINCTRL_PIN(281, "T12 GMAC1 CRS"),
PINCTRL_PIN(282, "T13 EXT CLK"),
PINCTRL_PIN(283, "T14 GPIO1 31"),
PINCTRL_PIN(284, "T15 GPIO0 3"),
PINCTRL_PIN(285, "T16 GPIO0 8"),
PINCTRL_PIN(286, "T17 GPIO0 12"),
PINCTRL_PIN(287, "T18 GPIO0 14"),
/* Row U */
PINCTRL_PIN(288, "U1 ICE0 IRST N"),
PINCTRL_PIN(289, "U2 USB0 VCCHSRT"),
PINCTRL_PIN(290, "U3 USB0 DP"),
PINCTRL_PIN(291, "U4 USB VCCA U20"),
PINCTRL_PIN(292, "U5 USB1 DP"),
PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"),
PINCTRL_PIN(294, "U7 GMAC0 TXD0"),
PINCTRL_PIN(295, "U8 GMAC0 RXD0"),
PINCTRL_PIN(296, "U9 GMAC1 COL"),
PINCTRL_PIN(297, "U10 GMAC1 TXD2"),
PINCTRL_PIN(298, "U11 GMAC1 RXDV"),
PINCTRL_PIN(299, "U12 GMAC1 RXD3"),
PINCTRL_PIN(300, "U13 MODE SEL 2"),
PINCTRL_PIN(301, "U14 GPIO1 30"),
PINCTRL_PIN(302, "U15 GPIO0 2"),
PINCTRL_PIN(303, "U16 GPIO0 7"),
PINCTRL_PIN(304, "U17 GPIO0 11"),
PINCTRL_PIN(305, "U18 GPIO0 13"),
/* Row V */
PINCTRL_PIN(306, "V1 USB0 GNDHSRT"),
PINCTRL_PIN(307, "V2 USB0 DM"),
PINCTRL_PIN(308, "V3 USB GNDA U20"),
PINCTRL_PIN(309, "V4 USB1 DM"),
PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"),
PINCTRL_PIN(311, "V6 GMAC0 COL"),
PINCTRL_PIN(312, "V7 GMAC0 TXC"),
PINCTRL_PIN(313, "V8 GMAC0 RXD1"),
PINCTRL_PIN(314, "V9 REF CLK"),
PINCTRL_PIN(315, "V10 GMAC1 TXD3"),
PINCTRL_PIN(316, "V11 GMAC1 TXEN"),
PINCTRL_PIN(317, "V12 GMAC1 RXD2"),
PINCTRL_PIN(318, "V13 M30 CLK"),
PINCTRL_PIN(319, "V14 GPIO1 29"),
PINCTRL_PIN(320, "V15 GPIO0 1"),
PINCTRL_PIN(321, "V16 GPIO0 6"),
PINCTRL_PIN(322, "V17 GPIO0 10"),
PINCTRL_PIN(323, "V18 SYS RESET N"),
};
/* Digital ground */
static const unsigned int gnd_3512_pins[] = {
76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169,
170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247
};
static const unsigned int dram_3512_pins[] = {
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29,
30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77,
78, 79, 80, 81, 82
};
static const unsigned int rtc_3512_pins[] = { 57, 20, 39 };
static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 };
static const unsigned int system_3512_pins[] = {
318, 264, 300, 245, 263, 282, 314, 323, 49,
};
static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 };
static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 };
static const unsigned int ide_3512_pins[] = {
162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202,
216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255
};
static const unsigned int sata_3512_pins[] = {
75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129,
128, 127, 126, 147, 146, 145, 144, 164
};
static const unsigned int usb_3512_pins[] = {
306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293
};
/* GMII, ethernet pins */
static const unsigned int gmii_gmac0_3512_pins[] = {
240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
};
static const unsigned int gmii_gmac1_3512_pins[] = {
243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
};
static const unsigned int pci_3512_pins[] = {
13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69,
70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123,
124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177,
178, 179, 195, 196, 197
};
/*
* Apparently the LPC interface is using the PCICLK for the clocking so
* PCI needs to be active at the same time.
*/
static const unsigned int lpc_3512_pins[] = {
285, /* LPC_LAD[0] */
304, /* LPC_SERIRQ */
286, /* LPC_LAD[2] */
305, /* LPC_LFRAME# */
287, /* LPC_LAD[3] */
268, /* LPC_LAD[1] */
};
/* Character LCD */
static const unsigned int lcd_3512_pins[] = {
262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211
};
static const unsigned int ssp_3512_pins[] = {
285, /* SSP_97RST# SSP AC97 Reset, active low */
304, /* SSP_FSC */
286, /* SSP_ECLK */
305, /* SSP_TXD */
287, /* SSP_RXD */
268, /* SSP_SCLK */
};
static const unsigned int uart_rxtx_3512_pins[] = {
267, /* UART_SIN serial input, RX */
322, /* UART_SOUT serial output, TX */
};
static const unsigned int uart_modem_3512_pins[] = {
285, /* UART_NDCD DCD carrier detect */
304, /* UART_NDTR DTR data terminal ready */
286, /* UART_NDSR DSR data set ready */
305, /* UART_NRTS RTS request to send */
287, /* UART_NCTS CTS clear to send */
268, /* UART_NRI RI ring indicator */
};
static const unsigned int tvc_3512_pins[] = {
246, /* TVC_DATA[0] */
319, /* TVC_DATA[1] */
301, /* TVC_DATA[2] */
283, /* TVC_DATA[3] */
265, /* TVC_CLK */
320, /* TVC_DATA[4] */
302, /* TVC_DATA[5] */
284, /* TVC_DATA[6] */
266, /* TVC_DATA[7] */
};
/* NAND flash pins */
static const unsigned int nflash_3512_pins[] = {
199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252,
253, 254, 249, 250, 232, 233, 211, 193, 194
};
/* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
static const unsigned int pflash_3512_pins[] = {
162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
214, 215, 193, 194
};
/*
* The parallel flash can be set up in a 26-bit address bus mode exposing
* A[0-15] (A[15] takes the place of ALE), but it has the
* side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
* used at the same time.
*/
static const unsigned int pflash_3512_pins_extended[] = {
162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
214, 215, 193, 194,
/* The extra pins */
296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281,
265,
};
/* Serial flash pins CE0, CE1, DI, DO, CK */
static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 };
/* The GPIO0A (0) pin overlap with TVC and extended parallel flash */
static const unsigned int gpio0a_3512_pins[] = { 265 };
/* The GPIO0B (1-4) pins overlap with TVC and ICE */
static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 };
/* The GPIO0C (5-7) pins overlap with ICE */
static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 };
/* The GPIO0D (9,10) pins overlap with UART RX/TX */
static const unsigned int gpio0d_3512_pins[] = { 267, 322 };
/* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 };
/* The GPIO0F (16) pins overlap with LCD */
static const unsigned int gpio0f_3512_pins[] = { 269 };
/* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
static const unsigned int gpio0g_3512_pins[] = { 249, 250 };
/* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
static const unsigned int gpio0h_3512_pins[] = { 251, 229 };
/* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
static const unsigned int gpio0i_3512_pins[] = { 230, 231 };
/* The GPIO0J (23) pins overlap with all flash */
static const unsigned int gpio0j_3512_pins[] = { 232 };
/* The GPIO0K (24,25) pins overlap with all flash and LCD */
static const unsigned int gpio0k_3512_pins[] = { 233, 211 };
/* The GPIO0L (26-29) pins overlap with parallel flash */
static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 };
/* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
static const unsigned int gpio0m_3512_pins[] = { 193, 194 };
/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 };
/* The GPIO1B (5-10, 27) pins overlap with just IDE */
static const unsigned int gpio1b_3512_pins[] = {
180, 181, 182, 183, 184, 198, 255
};
/* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
static const unsigned int gpio1c_3512_pins[] = {
199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237,
252, 253, 254
};
/* The GPIO1D (28-31) pins overlap with LCD and TVC */
static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
/* The GPIO2C (8-31) pins overlap with PCI */
static const unsigned int gpio2c_3512_pins[] = {
17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105,
140, 141, 142, 143, 157, 158, 159, 160
};
/* Groups for the 3512 SoC/package */
static const struct gemini_pin_group gemini_3512_pin_groups[] = {
{
.name = "gndgrp",
.pins = gnd_3512_pins,
.num_pins = ARRAY_SIZE(gnd_3512_pins),
},
{
.name = "dramgrp",
.pins = dram_3512_pins,
.num_pins = ARRAY_SIZE(dram_3512_pins),
.mask = DRAM_PADS_POWERDOWN,
},
{
.name = "rtcgrp",
.pins = rtc_3512_pins,
.num_pins = ARRAY_SIZE(rtc_3512_pins),
},
{
.name = "powergrp",
.pins = power_3512_pins,
.num_pins = ARRAY_SIZE(power_3512_pins),
},
{
.name = "systemgrp",
.pins = system_3512_pins,
.num_pins = ARRAY_SIZE(system_3512_pins),
},
{
.name = "vcontrolgrp",
.pins = vcontrol_3512_pins,
.num_pins = ARRAY_SIZE(vcontrol_3512_pins),
},
{
.name = "icegrp",
.pins = ice_3512_pins,
.num_pins = ARRAY_SIZE(ice_3512_pins),
/* Conflict with some GPIO groups */
},
{
.name = "idegrp",
.pins = ide_3512_pins,
.num_pins = ARRAY_SIZE(ide_3512_pins),
/* Conflict with all flash usage */
.value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
},
{
.name = "satagrp",
.pins = sata_3512_pins,
.num_pins = ARRAY_SIZE(sata_3512_pins),
},
{
.name = "usbgrp",
.pins = usb_3512_pins,
.num_pins = ARRAY_SIZE(usb_3512_pins),
},
{
.name = "gmii_gmac0_grp",
.pins = gmii_gmac0_3512_pins,
.num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
},
{
.name = "gmii_gmac1_grp",
.pins = gmii_gmac1_3512_pins,
.num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
/* Bring out RGMII on the GMAC1 pins */
.value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
},
{
.name = "pcigrp",
.pins = pci_3512_pins,
.num_pins = ARRAY_SIZE(pci_3512_pins),
/* Conflict only with GPIO2 */
.value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
},
{
.name = "lpcgrp",
.pins = lpc_3512_pins,
.num_pins = ARRAY_SIZE(lpc_3512_pins),
/* Conflict with SSP and UART modem pins */
.mask = SSP_PADS_ENABLE,
.value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
},
{
.name = "lcdgrp",
.pins = lcd_3512_pins,
.num_pins = ARRAY_SIZE(lcd_3512_pins),
/* Conflict with TVC and ICE */
.mask = TVC_PADS_ENABLE,
.value = LCD_PADS_ENABLE,
},
{
.name = "sspgrp",
.pins = ssp_3512_pins,
.num_pins = ARRAY_SIZE(ssp_3512_pins),
/* Conflict with LPC and UART modem pins */
.mask = LPC_PADS_ENABLE,
.value = SSP_PADS_ENABLE,
},
{
.name = "uartrxtxgrp",
.pins = uart_rxtx_3512_pins,
.num_pins = ARRAY_SIZE(uart_rxtx_3512_pins),
/* No conflicts except GPIO */
},
{
.name = "uartmodemgrp",
.pins = uart_modem_3512_pins,
.num_pins = ARRAY_SIZE(uart_modem_3512_pins),
/*
* Conflict with LPC and SSP,
* so when those are both disabled, modem UART can thrive.
*/
.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
},
{
.name = "tvcgrp",
.pins = tvc_3512_pins,
.num_pins = ARRAY_SIZE(tvc_3512_pins),
/* Conflict with character LCD and ICE */
.mask = LCD_PADS_ENABLE,
.value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE,
},
/*
* The construction is done such that it is possible to use a serial
* flash together with a NAND or parallel (NOR) flash, but it is not
* possible to use NAND and parallel flash together. To use serial
* flash with one of the two others, the muxbits need to be flipped
* around before any access.
*/
{
.name = "nflashgrp",
.pins = nflash_3512_pins,
.num_pins = ARRAY_SIZE(nflash_3512_pins),
/* Conflict with IDE, parallel and serial flash */
.mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
},
{
.name = "pflashgrp",
.pins = pflash_3512_pins,
.num_pins = ARRAY_SIZE(pflash_3512_pins),
/* Conflict with IDE, NAND and serial flash */
.mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
},
{
.name = "sflashgrp",
.pins = sflash_3512_pins,
.num_pins = ARRAY_SIZE(sflash_3512_pins),
/* Conflict with IDE, NAND and parallel flash */
.mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
},
{
.name = "gpio0agrp",
.pins = gpio0a_3512_pins,
.num_pins = ARRAY_SIZE(gpio0a_3512_pins),
/* Conflict with TVC */
.mask = TVC_PADS_ENABLE,
},
{
.name = "gpio0bgrp",
.pins = gpio0b_3512_pins,
.num_pins = ARRAY_SIZE(gpio0b_3512_pins),
/* Conflict with TVC and ICE */
.mask = TVC_PADS_ENABLE,
},
{
.name = "gpio0cgrp",
.pins = gpio0c_3512_pins,
.num_pins = ARRAY_SIZE(gpio0c_3512_pins),
/* Conflict with ICE */
},
{
.name = "gpio0dgrp",
.pins = gpio0d_3512_pins,
.num_pins = ARRAY_SIZE(gpio0d_3512_pins),
/* Conflict with UART RX/TX */
},
{
.name = "gpio0egrp",
.pins = gpio0e_3512_pins,
.num_pins = ARRAY_SIZE(gpio0e_3512_pins),
/* Conflict with LPC, UART modem pins, SSP */
.mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
},
{
.name = "gpio0fgrp",
.pins = gpio0f_3512_pins,
.num_pins = ARRAY_SIZE(gpio0f_3512_pins),
/* Conflict with LCD */
.mask = LCD_PADS_ENABLE,
},
{
.name = "gpio0ggrp",
.pins = gpio0g_3512_pins,
.num_pins = ARRAY_SIZE(gpio0g_3512_pins),
/* Conflict with NAND flash */
.value = NAND_PADS_DISABLE,
},
{
.name = "gpio0hgrp",
.pins = gpio0h_3512_pins,
.num_pins = ARRAY_SIZE(gpio0h_3512_pins),
/* Conflict with parallel flash */
.value = PFLASH_PADS_DISABLE,
},
{
.name = "gpio0igrp",
.pins = gpio0i_3512_pins,
.num_pins = ARRAY_SIZE(gpio0i_3512_pins),
/* Conflict with serial flash */
.value = SFLASH_PADS_DISABLE,
},
{
.name = "gpio0jgrp",
.pins = gpio0j_3512_pins,
.num_pins = ARRAY_SIZE(gpio0j_3512_pins),
/* Conflict with all flash */
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
SFLASH_PADS_DISABLE,
},
{
.name = "gpio0kgrp",
.pins = gpio0k_3512_pins,
.num_pins = ARRAY_SIZE(gpio0k_3512_pins),
/* Conflict with all flash and LCD */
.mask = LCD_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
SFLASH_PADS_DISABLE,
},
{
.name = "gpio0lgrp",
.pins = gpio0l_3512_pins,
.num_pins = ARRAY_SIZE(gpio0l_3512_pins),
/* Conflict with parallel flash */
.value = PFLASH_PADS_DISABLE,
},
{
.name = "gpio0mgrp",
.pins = gpio0m_3512_pins,
.num_pins = ARRAY_SIZE(gpio0m_3512_pins),
/* Conflict with parallel and NAND flash */
.value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
},
{
.name = "gpio1agrp",
.pins = gpio1a_3512_pins,
.num_pins = ARRAY_SIZE(gpio1a_3512_pins),
/* Conflict with IDE and parallel flash */
.mask = IDE_PADS_ENABLE,
.value = PFLASH_PADS_DISABLE,
},
{
.name = "gpio1bgrp",
.pins = gpio1b_3512_pins,
.num_pins = ARRAY_SIZE(gpio1b_3512_pins),
/* Conflict with IDE only */
.mask = IDE_PADS_ENABLE,
},
{
.name = "gpio1cgrp",
.pins = gpio1c_3512_pins,
.num_pins = ARRAY_SIZE(gpio1c_3512_pins),
/* Conflict with IDE, parallel and NAND flash */
.mask = IDE_PADS_ENABLE,
.value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
},
{
.name = "gpio1dgrp",
.pins = gpio1d_3512_pins,
.num_pins = ARRAY_SIZE(gpio1d_3512_pins),
/* Conflict with LCD and TVC */
.mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE,
},
{
.name = "gpio2agrp",
.pins = gpio2a_3512_pins,
.num_pins = ARRAY_SIZE(gpio2a_3512_pins),
.mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
/* Conflict with GMII GMAC1 and extended parallel flash */
},
{
.name = "gpio2bgrp",
.pins = gpio2b_3512_pins,
.num_pins = ARRAY_SIZE(gpio2b_3512_pins),
/* Conflict with GMII GMAC1, extended parallel flash and LCD */
.mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
},
{
.name = "gpio2cgrp",
.pins = gpio2c_3512_pins,
.num_pins = ARRAY_SIZE(gpio2c_3512_pins),
/* Conflict with PCI */
.mask = PCI_PADS_ENABLE,
},
};
/* Pin names for the pinmux subsystem, 3516 variant */
static const struct pinctrl_pin_desc gemini_3516_pins[] = {
/* Row A */
PINCTRL_PIN(0, "A1 AVCC3IOHA"),
PINCTRL_PIN(1, "A2 DRAM CK N"),
PINCTRL_PIN(2, "A3 DRAM CK"),