diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
index 6cc63f40e253..d7688916d2cc 100644
--- a/arch/arm/mach-aspeed/ast2600/platform.S
+++ b/arch/arm/mach-aspeed/ast2600/platform.S
@@ -2,7 +2,6 @@
 /*
  * Copyright (C) ASPEED Technology Inc.
  * Chia-Wei Wang <chiawei_wang@aspeedtech.com>
- *
  */
 
 #include <config.h>
@@ -70,38 +69,7 @@ ENDPROC(ast_bootmode)
 	str	r0, [r1]
 .endm
 
-.macro clock_init
-	ldr	r0, =AST_SCU_REV_ID
-	ldr	r0, [r0]
-
-	ldr	r1, =REV_ID_AST2600A0
-	cmp	r0, r1
-
-	bne	0f
-
-	/* setup CPU clocks */
-	ldr	r1, =AST_SCU_HW_STRAP1
-	ldr	r2, [r1]
-	bic	r2, #0x1800
-	orr	r2, #0x1000
-	str	r2, [r1]
-
-	ldr	r1, =AST_SCU_HPLL_PARAM
-	movw	r2, #0x408F
-	movt	r2, #0x1000
-	str	r2, [r1]
-
-	ldr	r1, =AST_SCU_HPLL_PARAM_EXT
-	mov	r2, #0x47
-	str	r2, [r1]
-
-wait_lock:
-	ldr	r2, [r1]
-	tst	r2, #0x80000000
-	beq	wait_lock
-
-0:
-	/* setup timer clocks*/
+.macro timer_init
 #ifdef CONFIG_FPGA_ASPEED
 	movw	r0, #0x7840
 	movt	r0, #0x17D
@@ -119,11 +87,8 @@ lowlevel_init:
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 	mov	pc, lr
 #else
-	/* unlock SCU */
-	scu_unlock
-
-	/* setup platform-dependent clock frequency */
-	clock_init
+	/* setup ARM arch timer frequency */
+	timer_init
 
 	/* reset SMP mailbox as early as possible */
 	mov	r0, #0x0
@@ -165,6 +130,40 @@ poll_mailbox_ready:
 	ldr	pc, =AST_SMP_MBOX_FIELD_POLLINSN
 
 do_primary_core_setup:
+	/* unlock system control unit */
+	scu_unlock
+
+	/* tune-up CPU clock for AST2600 A0 */
+	ldr	r0, =AST_SCU_REV_ID
+	ldr	r0, [r0]
+
+	ldr	r1, =REV_ID_AST2600A0
+	cmp	r0, r1
+
+	bne	0f
+
+	/* setup CPU clocks */
+	ldr	r0, =AST_SCU_HW_STRAP1
+	ldr	r1, [r0]
+	bic	r1, #0x1800
+	orr	r1, #0x1000
+	str	r1, [r0]
+
+	ldr	r0, =AST_SCU_HPLL_PARAM
+	movw	r1, #0x408F
+	movt	r1, #0x1000
+	str	r1, [r0]
+
+	ldr	r0, =AST_SCU_HPLL_PARAM_EXT
+	mov	r1, #0x47
+	str	r1, [r0]
+
+wait_lock:
+	ldr	r1, [r0]
+	tst	r1, #0x80000000
+	beq	wait_lock
+
+0:
 	/* enable cache & SRAM parity check */
 	mov	r0, #0
 	ldr	r1, =AST_SCU_CA7_PARITY_CLR